UNIT-II 8085 Microprocessor &8051

Microcontroller

Introduction

Systems using microprocessors basically have

three parts.

• CPU –to recognise and carry out program

instructions

• Input and output interfaces-to handle

communications between the MP and the outside

world.

• Memory- to hold the program instructions and data.

The 8085 Microprocessor

Architecture

The 8085 and Its Busses

• The 8085 is an 8-bit general purpose microprocessor that can

address 64K Byte of memory.

• It has 40 pins and uses +5V for power. It can run at a maximum

frequency of 3 MHz.

– The pins on the chip can be grouped into 6 groups:

• Address Bus.

• Data Bus.

• Control and Status Signals.

• Power supply and frequency.

• Externally Initiated Signals.

• Serial I/O ports.

The Address and Data Busses

• The address bus has 8 signal lines A8 – A15 which are

unidirectional.

• The other 8 address bits are multiplexed (time shared) with the 8

data bits.

– So, the bits AD0 – AD7 are bi-directional and serve as A0 –

A7 and D0 – D7 at the same time.

• During the execution of the instruction, these lines carry

the address bits during the early part, then during the

late parts of the execution, they carry the 8 data bits.

– In order to separate the address from the data, we can use a

latch to save the value before the function of the bits

changes.

The Control and Status Signals

• There are 4 main control and status signals. These are:

• ALE: Address Latch Enable. This signal is a pulse that

become 1 when the AD0 – AD7 lines have an address on

them. It becomes 0 after that. This signal can be used to

enable a latch to save the address bits from the AD lines.

• RD: Read. Active low.

• WR: Write. Active low.

• IO/M: This signal specifies whether the operation is a

memory operation (IO/M=0) or an I/O operation

(IO/M=1).

• S1 and S0 : Status signals to specify the kind of

operation being performed .Usually un-used in small

systems. www.yesnarayanan.blogspot.com

Frequency Control Signals

• There are 3 important pins in the frequency control group.

– X0 and X1 are the inputs from the crystal or clock

generating circuit.

• The frequency is internally divided by 2.

– So, to run the microprocessor at 3 MHz, a clock

running at 6 MHz should be connected to the X0

and X1 pins.

– CLK (OUT): An output clock pin to drive the clock of the

rest of the system.

• We will discuss the rest of the control signals as we get to them.

Microprocessor Communication and Bus Timing

• To understand how the microprocessor operates and uses these

different signals, we should study the process of communication

between the microprocessor and memory during a memory read

or write operation.

• Lets look at timing and the data flow of an instruction fetch

operation. (Example 3.1)

Steps For Fetching an

Instruction • Lets assume that we are trying to fetch the instruction at memory

location 2005. That means that the program counter is now set

to that value.

– The following is the sequence of operations:

• The program counter places the address value on the

address bus and the controller issues a RD signal.

• The memory’s address decoder gets the value and

determines which memory location is being accessed.

• The value in the memory location is placed on the data

bus.

• The value on the data bus is read into the instruction

decoder inside the microprocessor.

• After decoding the instruction, the control unit issues the

proper control signals to perform the operation.

Timing Signals For Fetching an Instruction

• Now, lets look at the exact timing of this sequence of events as that

is extremely important. (figure 3.3)

– At T1 , the high order 8 address bits (20H) are placed on the

address lines A8 – A15 and the low order bits are placed on

AD7–AD0. The ALE signal goes high to indicate that AD0 –

AD8 are carrying an address. At exactly the same time, the

IO/M signal goes low to indicate a memory operation.

– At the beginning of the T2 cycle, the low order 8 address bits

are removed from AD7– AD0 and the controller sends the Read

(RD) signal to the memory. The signal remains low (active) for

two clock periods to allow for slow devices. During T2 , memory

places the data from the memory location on the lines AD7–

AD0 .

– During T3 the RD signal is Disabled (goes high). This turns off

the output Tri-state buffers in the memory. That makes the

AD7– AD0 lines go to high impedence mode.

Demultiplexing AD7-AD0

– From the above description, it becomes obvious that

the AD7– AD0 lines are serving a dual purpose and

that they need to be demultiplexed to get all the

information.

– The high order bits of the address remain on the bus

for three clock periods. However, the low order bits

remain for only one clock period and they would be

lost if they are not saved externally. Also, notice that

the low order bits of the address disappear when they

are needed most.

– To make sure we have the entire address for the full

three clock cycles, we will use an external latch to save

the value of AD7– AD0 when it is carrying the address

bits. We use the ALE signal to enable this latch.

Demultiplexing AD7-AD0

– Given that ALE operates as a pulse during T1,

we will be able to latch the address. Then

when ALE goes low, the address is saved and

the AD7– AD0 lines can be used for their

purpose as the bi-directional data lines.

A15-A8

Latch AD7-AD0

D7- D0

A7- A0

8085

ALE

Cycles and States

• From the above discussion, we can define terms that will become

handy later on:

– T- State: One subdivision of an operation. A T-state lasts for

one clock period.

• An instruction’s execution length is usually measured in

a number of T-states. (clock cycles).

– Machine Cycle: The time required to complete one operation

of accessing memory, I/O, or acknowledging an external

request.

• This cycle may consist of 3 to 6 T-states.

– Instruction Cycle: The time required to complete the

execution of an instruction.

• In the 8085, an instruction cycle may consist of 1 to 6

machine cycles.

Generating Control Signals

• The 8085 generates a single RD signal. However, the signal

needs to be used with both memory and I/O. So, it must be

combined with the IO/M signal to generate different control

signals for the memory and I/O.

– Keeping in mind the operation of the IO/M signal we can

use the following circuitry to generate the right set of

signals:

A closer look at the 8085

Architecture

• Previously we discussed the 8085 from a

programmer’s perspective.

• Now, lets look at some of its features

with more detail.

The ALU

• In addition to the arithmetic & logic circuits, the ALU

includes the accumulator, which is part of every

arithmetic & logic operation.

• Also, the ALU includes a temporary register used for

holding data temporarily during the execution of the

operation. This temporary register is not accessible by

the programmer.

The Flags register – There is also the flags register whose bits are affected by the arithmetic &

logic operations.

• S-sign flag

– The sign flag is set if bit D7 of the accumulator is set after an

arithmetic or logic operation.

• Z-zero flag

– Set if the result of the ALU operation is 0. Otherwise is reset. This

flag is affected by operations on the accumulator as well as other

registers. (DCR B).

• AC-Auxiliary Carry

– This flag is set when a carry is generated from bit D3 and passed

to D4 . This flag is used only internally for BCD operations.

(Section 10.5 describes BCD addition including the DAA

instruction).

• P-Parity flag

– After an ALU operation if the result has an even # of 1’s the p-

flag is set. Otherwise it is cleared. So, the flag can be used to

indicate even parity.

• CY-carry flag

– Discussed earlier

More on the 8085 machine

cycles • The 8085 executes several types of instructions with

each requiring a different number of operations of

different types. However, the operations can be

grouped into a small set.

• The three main types are:

• Memory Read and Write.

• I/O Read and Write.

• Request Acknowledge.

• These can be further divided into various operations

(machine cycles).

Opcode Fetch Machine Cycle

• The first step of executing any instruction is the Opcode fetch

cycle.

– In this cycle, the microprocessor brings in the instruction’s

Opcode from memory.

• To differentiate this machine cycle from the very similar

“memory read” cycle, the control & status signals are set

as follows:

– IO/M=0, s0 and s1 are both 1.

– This machine cycle has four T-states.

• The 8085 uses the first 3 T-states to fetch the opcode.

• T4 is used to decode and execute it.

– It is also possible for an instruction to have 6 T-states in an

opcode fetch machine cycle.

Memory Read Machine Cycle

• The memory read machine cycle is

exactly the same as the opcode fetch

except:

– It only has 3 T-states

– The s0 signal is set to 0 instead.

The Memory Read Machine

Cycle

– To understand the memory read machine cycle, let’s study

the execution of the following instruction:

• MVI A, 32

– In memory, this instruction looks like:

• The first byte 3EH represents the opcode for loading a

byte into the accumulator (MVI A), the second byte is the

data to be loaded.

– The 8085 needs to read these two bytes from memory before

it can execute the instruction. Therefore, it will need at least

two machine cycles.

– The first machine cycle is the opcode fetch discussed

earlier.

– The second machine cycle is the Memory Read Cycle.

– Figure 3.10 page 83.

2000H

2001H

3E

32

Machine Cycles vs. Number of bytes in the instruction

• Machine cycles and instruction length, do not

have a direct relationship.

– To illustrate lets look at the machine cycles

needed to execute the following instruction.

• STA 2065H • This is a 3-byte instruction requiring 4 machine cycles and 13

T-states.

• The machine code will be stored

in memory as shown to the right

• This instruction requires the following 4 machine cycles:

– Opcode fetch to fetch the opcode (32H) from location 2010H, decode it and

determine that 2 more bytes are needed (4 T-states).

– Memory read to read the low order byte of the address (65H) (3 T-states).

– Memory read to read the high order byte of the address (20H) (3 T-states).

– A memory write to write the contents of the accumulator into the memory

location.

2010H

2011H

2012H

32H

65H

20H

The Memory Write Operation

• In a memory write operation:

– The 8085 places the address (2065H) on

the address bus

– Identifies the operation as a memory write

(IO/M=0, s1=0, s0=1).

– Places the contents of the accumulator on

the data bus and asserts the signal WR.

– During the last T-state, the contents of the

data bus are saved into the memory

location.

Memory interfacing

• There needs to be a lot of interaction between the

microprocessor and the memory for the exchange of

information during program execution.

– Memory has its requirements on control signals

and their timing.

– The microprocessor has its requirements as well.

• The interfacing operation is simply the matching of

these requirements.

Memory structure & its requirements

• The process of interfacing the above two chips is the

same.

– However, the ROM does not have a WR signal.

Address

Lines

Date

Lines

CS

RD Output Buffer

ROM

Address

Lines

Data Lines

CS

RD Output Buffer

RAM WR Input Buffer

Data Lines

Interfacing Memory

– Accessing memory can be summarized into the following

three steps:

– Select the chip.

– Identify the memory register.

– Enable the appropriate buffer.

– Translating this to microprocessor domain:

– The microprocessor places a 16-bit address on the

address bus.

– Part of the address bus will select the chip and the

other part will go through the address decoder to

select the register.

– The signals IO/M and RD combined indicate that a

memory read operation is in progress. The MEMR

signal can be used to enable the RD line on the

memory chip.

Address decoding

• The result of address decoding is the identification of

a register for a given address.

– A large part of the address bus is usually

connected directly to the address inputs of the

memory chip.

– This portion is decoded internally within the chip.

– What concerns us is the other part that must be

decoded externally to select the chip.

– This can be done either using logic gates or a

decoder.

The Overall Picture • Putting all of the concepts together, we

get:

A15-A8

Latch AD7-AD0

D7- D0

A7- A0

8085

ALE

IO/M RD WR

1K Byte

Memory

Chip

WR RD

CS

A9- A0

A15- A10 Chip Selection

Circuit

PIN DIAGRAM OF 8085

Pin Diagram of 8085

X1 & X2

Pin 1 and Pin 2 (Input)

These are also called

Crystal Input Pins.

8085 can generate clock

signals internally.

To generate clock signals

internally, 8085 requires

external inputs from X1

and X2.

RESET IN and RESET OUT

Pin 36 (Input) and Pin 3 (Output)

RESET IN:

◦ It is used to reset the

microprocessor.

◦ It is active low signal.

◦ When the signal on

this pin is low for at

least 3 clocking

cycles, it forces the

microprocessor to

reset itself.

RESET IN and RESET OUT

Pin 36 (Input) and Pin 3 (Output)

Resetting the

microprocessor

means:

◦ Clearing the PC and

IR.

◦ Disabling all

interrupts (except

TRAP).

◦ Disabling the SOD

pin.

RESET IN and RESET OUT

Pin 36 (Input) and Pin 3 (Output)

RESET OUT:

◦ It is used to reset the

peripheral devices

and other ICs on the

circuit.

◦ It is an output signal.

◦ It is an active high

signal.

SID and SOD

Pin 4 (Input) and Pin 5 (Output)

SID (Serial Input

Data):

o It takes 1 bit input

from serial port of

8085.

o Stores the bit at the

8th position (MSB) of

the Accumulator.

o RIM (Read Interrupt

Mask) instruction is

used to transfer the

bit.

SID and SOD

Pin 4 (Input) and Pin 5 (Output)

SOD (Serial Output

Data):

o It takes 1 bit from

Accumulator to serial

port of 8085.

o Takes the bit from

the 8th position

(MSB) of the

Accumulator.

o SIM (Set Interrupt

Mask) instruction is

used to transfer the

bit.

Interrupt Pins

Interrupt:

• It means interrupting the normal execution

of the microprocessor.

• When microprocessor receives interrupt

signal, it discontinues whatever it was

executing.

• It starts executing new program indicated

by the interrupt signal.

• Interrupt signals are generated by external

peripheral devices.

TRAP

Pin 6 (Input)

It is an non-maskable interrupt.

It has the highest priority.

It cannot be disabled.

It is both edge and level triggered.

It means TRAP signal must go from low to high.

And must remain high for a certain period of time.

TRAP is usually used for power failure and

emergency shutoff.

RST 6.5

Pin 8 (Input) It is a maskable

interrupt.It has the

third highest

priority.

It is level triggered

only.The pin has to

be held high for a

specific period of

time.

RST 6.5 can be

enabled by EI

instruction.

RST 5.5

Pin 9 (Input)

It is a maskable

interrupt.

It has the fourth

highest priority.

It is also level triggered.

The pin has to be held

high for a specific

period of time.

This interrupt is very

similar to RST 6.5.

INTR

Pin 10 (Input)

It is a maskable

interrupt.It has the

lowest priority.

It is also level triggered.

It is a general purpose

interrupt. By general

purpose we mean that it

can be used to vector

microprocessor to any

specific subroutine

having any address.

INTA

Pin 11 (Output)

It stands for interrupt

acknowledge.

It is an out going

signal.

It is an active low

signal.

Low output on this pin

indicates that

microprocessor has

acknowledged the

INTR request.

AD0 – AD7

Pin 19-12 (Bidirectional)

• These pins serve the dual

purpose of transmitting

lower order address and data

byte.

• During 1st clock cycle, these

pins act as lower half of

address.

• In remaining clock cycles,

these pins act as data bus.

• The separation of lower

order address and data is

done by address latch.

A8 – A15

Pin 21-28 (Unidirectional)

• These pins carry the

higher order of address

bus.

• The address is sent

from microprocessor to

memory.

• These 8 pins are

switched to high

impedance state during

HOLD and RESET

mode.

ALE

Pin 30 (Output)

• It is used to enable Address

Latch.

• It indicates whether bus

functions as address bus or

data bus.

• If ALE = 1 then

– Bus functions as address

bus.

• If ALE = 0 then

– Bus functions as data

bus.

S0 and S1

Pin 29 (Output) and Pin 33 (Output

• S0 and S1 are called

Status Pins.

• They tell the current

operation which is

in progress in 8085.

IO/M

Pin 34 (Output)

• This pin tells

whether I/O or

memory operation is

being performed.

• If IO/M = 1 then

– I/O operation is

being performed.

• If IO/M = 0 then

– Memory operation is

being performed.

IO/M

Pin 34 (Output)

• The operation being performed is indicated by S0 and

S1.

• If S0 = 0 and S1 = 1 then

– It indicates WRITE operation.

• If IO/M = 0 then

– It indicates Memory operation.

• Combining these two we get Memory Write

Operation.

RD

Pin 32 (Output)

• RD stands for Read.It is

an active low signal.

• It is a control signal

used for Read operation

either from memory or

from Input device.

• A low signal indicates

that data on the data

bus must be placed

either from selected

memory location or

from input device.

WR

Pin 31 (Output)

• WR stands for Write. It

is also active low

signal.It is a control

signal used for Write

operation either into

memory or into output

device. A low signal

indicates that data on

the data bus must be

written into selected

memory location or into

output device.

READY

Pin 35 (Input)

• This pin is used to

synchronize slower

peripheral devices with

fast microprocessor.A

low value causes the

microprocessor to enter

into wait state.The

microprocessor remains

in wait state until the

input at this pin

goes high.

HOLD

Pin 38 (Input)

• HOLD pin is used to request

the microprocessor for DMA

transfer.

• A high signal on this pin is a

request to microprocessor to

relinquish the hold on buses.

• This request is sent by DMA

controller.

• Intel 8257 and Intel 8237 are

two DMA controllers.

HLDA

Pin 39 (Output)

• HLDA stands for Hold

Acknowledge.

• The microprocessor uses this

pin to acknowledge the

receipt of HOLD signal.

• When HLDA signal goes

high, address bus, data bus,

RD, WR, IO/M pins are tri-

stated.

• This means they are cut-off

from external environment.

HLDA

Pin 39 (Output)

• The control of these buses goes to DMA

Controller.

• Control remains at DMA Controller

until HOLD is held high.

• When HOLD goes low, HLDA also goes

low and the microprocessor takes

control of the buses.

VSS and VCC

Pin 20 (Input) and Pin 40 (Input)

• +5V power supply is

connected to VCC.

• Ground signal is

connected to VSS.

The 8051 Microcontroller

8051 Basic Component

• 4K bytes internal ROM

• 128 bytes internal RAM

• Four 8-bit I/O ports (P0 - P3).

• Two 16-bit timers/counters

• One serial interface

BLOCK DIAGRAM

CPU

Interrupt

Control

OSC Bus

Control

4k

ROM

Timer 1

Timer 2

Serial

128 bytes

RAM

4 I/O Ports

TXD RXD

External Interrupts

P0 P2 P1 P3

Addr/Data

Other 8051 featurs • only 1 On chip oscillator (external crystal)

• 6 interrupt sources (2 external , 3 internal, Reset)

• 64K external code (program) memory(only

read)PSEN

• 64K external data memory(can be read and write) by

RD,WR

• Code memory is selectable by EA (internal or

external)

• We may have External memory as data and code

8051 Schematic Pin out

IMPORTANT PINS (IO Ports) • One of the most useful features of the 8051 is that it

contains four I/O ports (P0 - P3)

• Port 0 （pins 32-39）：P0（P0.0～P0.7）

– 8-bit R/W - General Purpose I/O

– Or acts as a multiplexed low byte address and data bus for external memory design

• Port 1 （pins 1-8） ：P1（P1.0～P1.7）

– Only 8-bit R/W - General Purpose I/O

• Port 2 （pins 21-28）：P2（P2.0～P2.7）

– 8-bit R/W - General Purpose I/O

– Or high byte of the address bus for external memory design

• Port 3 （pins 10-17）：P3（P3.0～P3.7）

– General Purpose I/O

– if not using any of the internal peripherals (timers) or external interrupts.

• Each port can be used as input or output (bi-direction)

Port 3 Alternate Functions

IMPORTANT PINS

• PSEN (out): Program Store Enable, the read signal for external program memory (active low).

• ALE (out): Address Latch Enable, to latch address outputs at Port0 and Port2

• EA (in): External Access Enable, active low to access external program memory locations 0 to 4K

• RXD,TXD: UART pins for serial I/O on Port 3

• XTAL1 & XTAL2: Crystal inputs for internal oscillator.

Pins of 8051

• Vcc（pin 40）：

– Vcc provides supply voltage to the chip.

– The voltage source is +5V.

• GND（pin 20）：ground

• XTAL1 and XTAL2（pins 19,18）：

– These 2 pins provide external clock.

– Way 1：using a quartz crystal oscillator

– Way 2：using a TTL oscillator

– Example 4-1 shows the relationship between XTAL and the machine cycle

Pins of 8051

• RST（pin 9）：reset

– input pin and active high（normally low）.

• The high pulse must be high at least 2

machine cycles.

– power-on reset.

• Upon applying a high pulse to RST, the

microcontroller will reset and all values in

registers will be lost.

• Reset values of some 8051 registers

– power-on reset circuit

Pins of 8051

• EA（pin 31）：external access

– There is no on-chip ROM in 8031 and 8032 .

– The /EA pin is connected to GND to indicate the code

is stored externally.

– /PSEN ＆ ALE are used for external ROM.

– For 8051, /EA pin is connected to Vcc.

– “/” means active low.

• PSEN（pin 29）：program store enable

– This is an output pin and is connected to the OE pin of

the ROM.

Pins of 8051

• ALE（pin 30）：address latch enable

– It is an output pin and is active high.

– 8051 port 0 provides both address and data.

– The ALE pin is used for de-multiplexing the

address and data by connecting to the G pin

of the 74LS373 latch.

Addressing Modes

Immediate Mode – specify data by its value

mov A, #0 ;put 0 in the accumulator

;A = 00000000

mov R4, #11h ;put 11hex in the R4 register

;R4 = 00010001

mov B, #11 ;put 11 decimal in b register

;B = 00001011

mov DPTR,#7521h ;put 7521 hex in DPTR

;DPTR = 0111010100100001

Addressing Modes

Direct Mode – specify data by its 8-bit address Usually for 30h-7Fh of RAM

Mov a, 70h ; copy contents of RAM at 70h to a Mov R0,40h ; copy contents of RAM at 70h to a Mov 56h,a ; put contents of a at 56h to a Mov 0D0h,a ; put contents of a into PSW

TIMING DIAGRAM

• Timing Diagram is a graphical

representation.

• It represents the execution time taken by

each instruction in a graphical format.

• The execution time is represented in

T-states.

CONTROL SIGNALS

INSTRUCTION CYCLE

• The time required to execute an

instruction is called instruction cycle.

MACHINE CYCLE

• The time required to access the memory

or input/output devices is called

machine cycle.

T-STATE

• The machine cycle and instruction cycle

takes multiple clock periods.

• A portion of an operation carried out in

one system clock period is called as T-

state

MACHINE CYCLES OF 8085

The 8085 microprocessor has 5 basic

machine cycles.

They are

1. Opcode fetch cycle (4T)

2. Memory read cycle (3 T)

3. Memory write cycle (3 T)

4. I/O read cycle (3 T)

5. I/O write cycle (3 T)

MACHINE CYCLES OF 8085

• The processor takes a definite time to execute the machine cycles. The time taken by the processor to execute a machine cycle is expressed in T-states.

• One T-state is equal to the time period of the internal clock signal of the processor.

• The T-state starts at the falling edge of a clock.

OPCODE FETCH MACHINE CYCLE OF

8085

OPCODE FETCH MACHINE CYCLE OF

8085

• Each instruction of the processor has one byte opcode.

• The opcodes are stored in memory. So, the processor executes the opcode fetch machine cycle to fetch the opcode from memory.

• Hence, every instruction starts with opcode fetch machine cycle.

• The time taken by the processor to execute the opcode fetch cycle is 4T.

• In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor.

MEMORY READ MACHINE CYCLE OF

8085

MEMORY READ MACHINE CYCLE

OF 8085

• The memory read machine cycle is executed

by the processor to read a data byte from

memory.

• The processor takes 3T states to execute this

cycle

• The instructions which have more than one

byte word size will use the machine cycle after

the opcode fetch machine cycle

MEMORY WRITE MACHINE CYCLE

OF 8085

MEMORY WRITE MACHINE CYCLE OF

8085

• The memory write machine cycle is

executed by the processor to write a data

byte in a memory location.

• The processor takes, 3T states to

execute this machine cycle

I/O READ CYCLE OF 8085

• The I/O Read cycle is executed by the

processor to read a data byte from I/O

port or from the peripheral.

• The processor takes 3T states to execute

this machine cycle.

• The IN instruction uses this machine

cycle during the execution.

I/O READ CYCLE OF 8085

I/O WRITE CYCLE OF 8085

• The I/O write machine cycle is executed

by the processor to write a data byte in

the I/O port or to a peripheral, which is

I/O, mapped in the system.

• The processor takes, 3T states to

execute this machine cycle.

I/O WRITE CYCLE OF 8085