unit 3 finite state machine

Department of Communication Engineering, NCTU 1

Unit 3 Finite State Machine

If we hear, we forget;

if we see, we remember;

if we do, we understand. -- Proverb


3.1 Derivation of State Graphs and Tables


Hardware Project

Unit 3 Finite State Machine Sau-Hsuan Wu

A Finite State Machine (FSM) is simply a state register that holds the current state and some combinational logic which calculates the next state and outputs based on the current state and the inputs

FSM types Moore machine : the outputs are functions of the present

state only Mealy machine : the outputs are functions of both the

present state and the inputs


Hardware Project


A Moore FSM MTS turnstile

UnlockedLocked

Easy Cards

PassingViolation

(Unlocked)

Passing

Alarm Reset

Initialization


Hardware Project


State diagram representation Locked ST: S0, Unlocked ST : S1 and Violation ST: S2

Inputs Presence of Easy Card u0 =1, otherwise u0 =0

Passenger passing u1 =1, otherwise u1 =0

Alarm reset u2 =1, otherwise u2 =0

Outputs (Z) S0 Locked

S1 Unlocked

S2 Unlocked

S0

S2 S1

u1=1 u0=1

u0=0 XNOR u1=0

u1=1

u1=0u2=0

u2=1


Hardware Project


State transition table

S0

S2 S1

u1=1 u0=1

u0=0 XNOR u1=0

u1=1

u1=0u2=0

u2=1

S S+ Z

u2u1u0= 000 001 010 011 100 101 110 111

S0 S0 S1 S2 S0 S0 S0 S0 S0 1S1 S1 − S0 S1 − − − − 0S2 S2 − S2 − S0 S0 S0 S0 0


Hardware Project


Binary state assignmentS S+ Z

u2u1u0= 000 001 010 011 100 101 110 111

S0 S0 S1 S2 S0 S0 S0 S0 S0 1S1 S1 − S0 S1 − − − − 0S2 S2 − S2 − S0 S0 S0 S0 0

SQ1 Q0

Q1+ Q0

+ Z

u2u1u0= 000 001 010 011 100 101 110 111

00 00 01 10 00 00 00 00 00 101 01 − 00 01 − − − − 010 10 − 10 − 00 00 00 00 011 − − − − − − − − −


Hardware Project


Next-State maps

0

0

0

0

0

0

0

1

X

0

X

X

X

0

X

0

X

X

X

X

X

X

X

X

0

1

0

X

0

X

0

1

0

0

0

1

0

0

0

0

X

1

X

X

X

1

X

0

X

X

X

X

X

X

X

X

0

0

0

X

0

X

0

0

Q1 Q0 u2u1u0= 000 001 010 011 100 101 110 111 Z

00 00 01 10 00 00 00 00 00 101 01 − 00 01 − − − − 010 10 − 10 − 00 00 00 00 011 − − − − − − − − −

Q1Q0 Q1Q0

u1u0 u1u0

u2

1/0u2

1/0

Q1+ Q0

+

00

01

11

10

00

01

11

10

01 11 10 01 11 10


Hardware Project


Characteristic equations

Q1+= Q1u2’ + Q0’u2’u1u0’ Q0

+= Q0u1’ + Q0u0 + u2’u1’u0

0

0

0

0

0

0

0

1

X

0

X

X

X

0

X

0

X

X

X

X

X

X

X

X

0

1

0

X

0

X

0

1

0

0

0

1

0

0

0

0

X

1

X

X

X

1

X

0

X

X

X

X

X

X

X

X

0

0

0

X

0

X

0

0

Q1Q0 Q1Q0

u1u0 u1u0

u2

1/0u2

1/0

Q1+ Q0

+

00

01

11

10

00

01

11

10

01 11 10 01 11 1000 00


Hardware Project


Output equations

Characteristic equations:Q1

+= Q1u2’ + Q0’u2’u1u0’ Q0+= Q0u1’ + Q0u0 + u2’u1’u0

Output equation :Z = Q1 Q0 (or = (Q1|| Q0)’

Q1 Q0 u2u1u0= 000 001 010 011 100 101 110 111 Z

00 00 01 10 00 00 00 00 00 101 01 − 00 01 − − − − 010 10 − 10 − 00 00 00 00 011 − − − − − − − − −/

(1)


Hardware Project


Circuit realization with D-FFs Characteristic equations:

Q1+= Q1u2’ + Q0’u2’u1u0’ Q0

+= Q0u1’ + Q0u0 + u2’u1’u0

Output equation :Z = Q1 Q0

D

CK

Q

CLR

u2

u1u0

Q1

Q0

Q1+

D

CK

Q

CLR

u1

u0

u2

Q0+

Z

CLK


Hardware Project


Another Moore FSM An elevator controller (Up, Down, Open and Timer start)

Idle

GoingUp

req > floor

req < floor

!(req > floor)

!(timer < 10)

req < floor

DoorOpen

GoingDn

req > floor

u,d,o, t = 1,0,0,0

u,d,o,t = 0,0,1,0

u,d,o,t = 0,1,0,0

u,d,o,t = 0,0,1,1

u is up, d is down, o is open

req == floor

!(req<floor)

timer < 10

t is timer_start


Hardware Project


The general model of a Moore machine

Com.Logic

Com.Logic

X1

X2

Xm

Q1+

Q2+

Qm+

Z1

Z2

Zm

Q1

Q2

Qm

D

CK

Q

CLR

D

CK

Q

CLR

D

CK

Q

CLR


Hardware Project


A Mealy FSM A traffic light controller

Highway

Highway

Farmroad

Farmroad

HL

HL

FL

FL

C

C


Hardware Project


Tabulation of inputs and outputs

Tabulation of unique states

Input SignalResetCTSTL

Output SignalHG, HY, HRFG, FY, FRST

Descriptionplace FSM in initial statedetect vehicle on farmroadshort time interval expiredlong time interval expired

Descriptionassert green/yellow/red highway lightsassert green/yellow/red farmroad lightsstart timing a short or long interval

StateS0

S1

S2

S3

DescriptionHighway green (farmroad red)Highway yellow (farmroad red)Farmroad green (highway red)Farmroad yellow (highway red)


Hardware Project


The state diagram

S0: HG (FR)

S1: HY (FR)

S2: FG (HR)

S3: FY (HR)

S0

S1 S3

TL & C /STTS/ST

TL’ + C’

TS’TS’

S2

Reset

TS/ST

TL’ + C

TL & C’/ST


Hardware Project


State transition table

S S+|ST

CTLTS =000 001 010 011 100 101 110 111

S0 S0|ST’ S0|ST’ S0|ST’ S0|ST’ S0|ST’ S0|ST’ S1|ST S1|ST

S1 S1|ST’ S2|ST S1|ST’ S2|ST S1|ST’ S2|ST S1|ST’ S2|ST

S2 S2|ST’ S2|ST’ S3|ST S3|ST S2|ST’ S2|ST’ S2|ST’ S2|ST’


S0

S1S3

TL & C /ST TS/ST

TL’ + C’

TS’TS’

S2

Reset

TS/ST

TL’ + C

TL & C’/ST

HG = S0

FR = S0+ S1 HY = S1

FG = S2 HR = S2+ S3 FY = S3

ST = ?


Hardware Project


S S+|ST

CTLTS =000 001 010 011 100 101 110 111

S0 S0|ST’ S0|ST’ S0|ST’ S0|ST’ S0|ST’ S0|ST’ S1|ST S1|ST


S2 S2|ST’ S2|ST’ S3|ST S3|ST S2|ST’ S2|ST’ S2|ST’ S2|ST’


S S+|ST

CTLTS =000 001 010 011 100 101 110 111

00 00 |0 00 |0 00 |0 00 |0 00 |0 00 |0 01 |1 01 |1

01 01|0 11 |1 01 |0 11 |1 01 |0 11 |1 01 |0 11 |1

11 11 |0 11 |0 10|1 10|1 11 |0 11 |0 11 |0 11|0

10 10 |0 00|1 10 |0 00|1 10 |0 00|1 10 |0 00|1


Hardware Project


0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

1

1

1

1

1

1

1

1

1

1

0

0

0

0

1

1

0

0

0

0

1

0

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

Q1Q0 Q1Q0

TLTS TLTS

C1/0

C1/0

Q1+ Q0

+

00

01

11

10

00

01

11

10

01 11 10 01 11 10

S S+|ST

CTLTS =000 001 010 011 100 101 110 111

00 00 |0 00 |0 00 |0 00 |0 00 |0 00 |0 01 |1 01 |1

01 01|0 11 |1 01 |0 11 |1 01 |0 11 |1 01 |0 11 |1

11 11 |0 11 |0 10|1 10|1 11 |0 11 |0 11 |0 11|0

10 10 |0 00|1 10 |0 00|1 10 |0 00|1 10 |0 00|1


Hardware Project


0

0

0

0

1

0

1

0

0

0

1

1

1

1

0

0

0

0

0

0

0

1

0

1

0

0

1

1

1

1

0

0

Q1Q0

TLTS

C1/0

ST

00

01

11

10

01 11 10

S S+|ST

CTLTS =000 001 010 011 100 101 110 111

00 00 |0 00 |0 00 |0 00 |0 00 |0 00 |0 01 |1 01 |1

01 01|0 11 |1 01 |0 11 |1 01 |0 11 |1 01 |0 11 |1

11 11 |0 11 |0 10|1 10|1 11 |0 11 |0 11 |0 11|0

10 10 |0 00|1 10 |0 00|1 10 |0 00|1 10 |0 00|1

HG = S0

FR = S0+ S1 HY = S1

FG = S2 HR = S2+ S3 FY = S3

ST = Q1Q0’ TS + Q1’ Q0 TS + Q1’ Q0’ CTL + Q1Q0C’TL


Hardware Project


The general model of a Mealy machine

Com.Logic

X1

X2

Xm

Q1+

Q2+

Qm+

Z1

Z2

Zm

Q1

Q2

Qm

D

CK

Q

CLR

D

CK

Q

CLR

D

CK

Q

CLR


Hardware Project


Circuit realization using a Mealy machine

CLK

TS’S0

S1S3

TL & C /ST TS/ST

TL’ + C’

TS’

S2

Reset

TS/ST

TL’ + C

TL & C’/ST

FSM

DN

CK

D

Pre

D

CK

Q

CLR

Counter for TS

DN

CK

D

Pre

Counter for TL

D

CK

Q

CLR

ST

TS

TL

VDD

Plant

CntPre


Hardware Project


Timing diagram using a Mealy machine

S0

S1S3

TL & C /ST TS/ST

TL’ + C’

TS’

S2

Reset

TS/ST

TL’ + C

TL & C’/STST = Q1Q0’ TS + Q1’ Q0 TS + Q1’ Q0’ CTL + Q1Q0C’TL

CLK

Q1Q0

TL

S0 S1

C

ST

TS

S2

HG = S0

S3

CntPre


Hardware Project


An alternative realization with a Moore machine

TS’TL & C TS

TL’ + C’

TS’

Reset

TS

TL’ + C

TL & C’

FSM

STS1

ST

S0

ST’

S3

ST

S2

ST’

ST = Q1Q0’ + Q1’ Q0

CLK

Counter for TS

Counter for TL

ST TS

TL

VDD

Plant

ENA

CK

D

Pre

DN

ENA

CK

D

Pre

DN

Notice: need more states to generate the Pre signal if needed!! Notice: need more states to generate the Pre signal if needed!!


Hardware Project


Timing diagram using a Moore machine

ST = Q1Q0’ + Q1’ Q0

TS’TL & C TS

TL’ + C’

TS’

Reset

TS

TL’ + C

TL & C’

STS1

ST

S0

ST’

S3

ST

S2

ST’

CLK

Q1Q0

TL

S0 S1

C

ST

TS

S2

HG = S0

S3


Hardware Project


The general model of a digital circuit

Plant

X1

X2

XP

IN1

IN2

INR

Z1

Z2

ZQ

CS1

CS2

CSM

FSM


Hardware Project


Difference between a Moore machine and a Mealy machine The outputs of a Moore FSM are synchronized with the

CLK, however the outputs of a Mealy machine are not The disadvantages of Moore FSMs

In general, more states are required to generate outputs The action of the plant that the FSM controls is always one

CLK period lagging behind the control signals The above two points are right the advantages of Mealy FSMs

The disadvantages of Mealy FSMs Outputs of FSMs must be

sampled with FFs if synchronization is required

Glitches and spikes

D

CK

Q

CLR

D

CK

Q

CLR

ST

CntPre


Hardware Project


Serial data code converter Design a code converter that convert an NRZ-coded bit

stream to a Manchester-coded bit stream


Hardware Project


Realize the code converter with a Mealy machine Use a clock Clock2 which is twice the data rate The only two possible input sequences are 00 and 11

S0

S1

0 /0 1/1

S2

Reset

0/1 1/0

S S+ Z

X= 0 X=1 X= 0 X=1S0 S1 S2 0 1S1 S0 − 1 −S2 − S0 − 0


Hardware Project


The timing diagram using the Mealy machine

CLK2

NRZ

S0

S1

0 /0 1/1

S20/1 1/0

Manchester(ideal)

00 1111

1111

11 00

0011 11 00 11 00 0000

11110011 11 00 11 00 0000

S1S0S2S1 S0 S2 S0 S2 S0S0

Z(actual)


Hardware Project


Redesign the data converter with a Moore machine


Hardware Project


The timing diagram using the Moore machine

Output is one-clock lagging

behind the input sequence


3.2 Data Path and FSM


Hardware Project


The general model of a digital circuit

Plant

X1

X2

XP

IN1

IN2

INR

Z1

Z2

ZQ

CS1

CS2

CSM

FSM


Hardware Project


A plant usually includes A data path over which data are processed

A data path may include An arithmetic and logic unit (ALU) Registers Counters Decoders

Peripherals which may include Input devices like key boards and mice Storages devices like memories and disks Output devices

Communications interface like USB, RS232, and Eithernet Speaker Printer Displays like LCD and 7-segment displays


Hardware Project


Data path and FSM go hand in hand in digital design A signal processing scheme is usually partitioned into a

sequence of processing stages Data path decides the number of stages the data is processed

and the paths of data flow in between the stages Data at the outputs of each stage are stores in registers The complexity or in other words the levels of logics in

each stage decides the processing speed On the other hand the number of stages decides the

processing delay FSM controls data’s movement in data path


Hardware Project


Data path for bubble sorting of 4 words

CS3

Reg 0

Reg 1

Reg 2

Reg 3M

UX

A

B

CO

MP

DIPSW

MU

XA

B

A > B

A = B

S0 S1 S2 S3

CS0

CS1

CS2

CS4

CS5


Hardware Project


Draw a flow chart

Idle

St

Load DataCounter --

Cnt3=0

Cnt1=Cnt0

Load B

Load A

B>A

Load LW

Load HW

Cnt 1 --

Y

Cnt1=0

Cnt0=0

N

N

N

Cnt 0 --

Cnt 0 = 2

Load


Hardware Project


Checking the Timing diagram

CLK

St

Cnt 3 11 10 01 00

Idle

Load

Cnt 0 10XX

10XXCnt 1

XX


Hardware Project


Sequential machines are commonly partitioned into data path units and control units

The synthesis of a sequential machine usually includes: Constructing the datapath units Designing FSMs to control the data flow Realizing the control signals Checking the timing of signals

FSMFSM

Datapath LogicDatapath Logic

DatapathDatapathRegistersRegisters

Control inputsControl inputs

ClockClockControlControl signalssignals

Datapath UnitDatapath Unit


3.3 Algorithm State Machine


Hardware Project


Datapath units consist of: Arithmetic units :

Arithmetic and logic units (ALU) Storage registers Logic for moving data :

through the system between the computation units and internal registers to and from the external environments

Control units are commonly modeled by State transition graphs (STGs) Algorithm state machine (ASM) charts for FSM

A combined control-dataflow sequential machine is modeled by ASM and datapath (ASMD) charts


Hardware Project


Algorithm State Machine (ASM) Charts State transition graphs only indicate the transitions that

result from inputs Not only does ASM display the state transitions, it also

models the evolution of states under the application of input datas

An ASM chart is formed with three fundamental elements


Hardware Project


Both Mealy and Moore machines can be represented by ASM The outputs of a Moore machine are listed inside a state box Conditional outputs (Mealy outputs) are placed in

conditional output boxes

StartStart

C <= C+1C <= C+1

EnEn


Hardware Project


A sequential machine is partitioned into a controller and a datapath, and the controller is described by an ASM

The ASM chart can be modified to link to the datapath that is under control of the ASM

The modified ASM is referred to as the algorithm state machine and datapath (ASMD) chart

ASMD is different from ASM in that :each of the transition path of an ASM is annotated with the associated concurrent register operations of datapath


Hardware Project


An ASMD chart for a up-down counter

StartStart

ClrClr

UpUp

StartStart

UpUp

Count <= 0Count <= 0

Count <= Count + 1Count <= Count + 1

Count <= Count - 1Count <= Count - 1

ResetReset

Count <= 0Count <= 0

Count <= Count + 1Count <= Count + 1

Count <= Count - 1Count <= Count - 1

Up-down counter Up-down counter with asynchronous resetwith asynchronous reset

Up-down counter Up-down counter with synchronous resetwith synchronous reset


Hardware Project


ASM v.s. ASMD charts for a counter with enable

Count <= Count + 1Count <= Count + 1StartStart

C <= C+1C <= C+1

EnEn

StartStart

Enable DPEnable DP

EnEn

ASM chart ASM chart representationrepresentation

ASMD chart ASMD chart representationrepresentation


Hardware Project


A electronic dice game


Hardware Project


Flowchart for dice game


Hardware Project


Convert flowchart to state machine chart


Hardware Project


State machine chart


Hardware Project


State graph


Hardware Project


Next-state map


Hardware Project


Realization

unit 3 finite state machine

Documents

current state

state register

derivation of state

x0 x0 0q1 q0u2u1u0

inputshardware projectunit

inputsfsm typesmoore

tables hardware projectunit

q1u2 q0u2u1u0 q0