unit 11 registers and counters - national chiao tung ...moblie123.cm.nctu.edu.tw/101 logical...
TRANSCRIPT
Department of Communication Engineering, NCTU 1
Unit 11 Registers and Counters
Department of Communication Engineering, NCTU 2
11.1 Register and RegisterTransfers
Department of Communication Engineering, NCTU 3
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
A 4-bit register is composed of 4 D-type FFs which sharea common clock, clear (Clr) and chip enable (CE)
Department of Communication Engineering, NCTU 4
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
The symbol notation for a 4-bit register
Department of Communication Engineering, NCTU 5
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
Data are passed from one register to another. In this case,whether Ai or Bi is sent to Di depends on En
Department of Communication Engineering, NCTU 6
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
A 8-bit register with tri-state output enable (En), and itscorresponding symbol
Department of Communication Engineering, NCTU 7
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
Registers use output enable (for releasing data) and chipenable (for accepting data) to transfer data on a bus
Department of Communication Engineering, NCTU 8
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
Accumulator : the output of adder is fed back as one of aaddend
Department of Communication Engineering, NCTU 9
11.2 Shift Registers
Department of Communication Engineering, NCTU 10
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
A shift register is a register whose data can be shiftedright or left
A 4-bit right-shift register
Department of Communication Engineering, NCTU 11
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
The timing diagram of a 4-bit right shift register
Department of Communication Engineering, NCTU 12
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
A right-shift register with inverted rotation feedback Two possible output patterns which depend on the initial
state This is called Johnson counter
Department of Communication Engineering, NCTU 13
11.3 Design of Binary Counters
Department of Communication Engineering, NCTU 14
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
A synchronous counter is a counter whose FFs are alldriven by a clock. While for a asynchronous counter, theoutput of FF serves as a driving clock of the next FF
A 3-bit synchronous counter implemented with T-FFs
Department of Communication Engineering, NCTU 15
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
Design the functions of TC , TB , and TA with a state tableand a truth table
First, draw a stable which lists the present state and thenext state, then draw the truth table of the functions
Department of Communication Engineering, NCTU 16
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
Logic minimizations with the Karnaugh map
Department of Communication Engineering, NCTU 17
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
For D-FFs, DA is equal to the next state of FF A. So weonly need a state table for counters designed with D-FFs
Department of Communication Engineering, NCTU 18
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
An alternative design with D-FFs
Department of Communication Engineering, NCTU 19
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
Design of up-down counter The state table and the state graph of a up-down counter
Department of Communication Engineering, NCTU 20
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
The logic functions of inputs
One can verify the function by setting U=0 and D=1, orvice versus. For example, U=0 and D=1
Department of Communication Engineering, NCTU 21
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
A up-down counter synthesized with D-FFs
Department of Communication Engineering, NCTU 22
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
Design of loadable counter with count enable
Department of Communication Engineering, NCTU 23
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
The next-state equations
Department of Communication Engineering, NCTU 24
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
Design of loadable up-dn counter with count enable? Realize this counter with GAL 22V10 Due on the next meet
Department of Communication Engineering, NCTU 25
11.4 Counter of Other Sequences
Department of Communication Engineering, NCTU 26
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
A five state counter Define the next states
of three unused states001、101、110 asunspecified
The counter can berealized with T-FFs T =present state’
next state List the truth table for
the next states of Use the Karnaugh map
, ,A B CT T T
Department of Communication Engineering, NCTU 27
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
Notice that T = Q+Q So, first design Q+ = f (A,B,C) Use Karnaugh map for Q=0 and Q=1, respectively
For Q=0, have T = Q+
For Q=1, have T = (Q+ )’
Department of Communication Engineering, NCTU 28
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
Department of Communication Engineering, NCTU 29
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
After simplification
Notice that even if the next state of 001,101 and 110 arenot specified at the beginning, they are assigned certainvalues implicitly while being used as the don’t careconditions for circuit simplifications
A
B
C
T C B
T C A CB
T C B CB
Department of Communication Engineering, NCTU 30
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
Circuit realization
Department of Communication Engineering, NCTU 31
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
The effects of don’t care conditions When CBA=001, TC TB TA = 110, then C+B+A+ =111 When CBA=101, TC TB TA = 011, then C+B+A+ =110 When CBA=110, TC TB TA = 101, then C+B+A+ =011
The final counter
Department of Communication Engineering, NCTU 32
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
An alternative design with D-FFs This is much easier since DC = C+, DB = B+ and DA = A+
So, the functions are
( )
C
B
A
D B
D C BA
D CA BA A C B
Department of Communication Engineering, NCTU 33
11.5 Derivation of Flip-Flop InputEquations
Department of Communication Engineering, NCTU 34
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
In counter design, we mainly derive the input equations ofFFs. This can be done either with the true table of thepresent states and the next states, or with the next-statemap
Department of Communication Engineering, NCTU 35
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu
Department of Communication Engineering, NCTU 36
Logic Design Unit 11 Registers and Counters Sau-Hsuan Wu