IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 3, MARCH 2000 569

Ultra-Thin Elevated Channel Poly-Si TFT Technologyfor Fully-Integrated AMLCD System on Glass

Shengdong Zhang, Chunxiang Zhu, Johnny K. O. Sin, Senior Member, IEEE, J. N. Li, andPhilip K. T. Mok, Member, IEEE

Abstract—A novel low temperature poly-Si (LTPS) TFT tech-nology called the ultra-thin elevated channel TFT (UT-ECTFT)technology is proposed. The devices fabricated using this tech-nology have an ultra-thin channel region (300 Å) and a thickdrain/source region (3000 Å). The ultra-thin channel region isconnected to the heavily doped thick drain/source region througha lightly doped overlapped region. The ultra-thin channel regionis used to obtain a low grain-boundary trap density in the channel,and the overlapped lightly doped region provides an effectiveway for electric field spreading at the drain, thereby reduces theelectric field there significantly. With the low grain-boundary trapdensity and low drain electric field, excellent current saturationcharacteristics and high drain breakdown voltage are obtained inthe UT-ECTFT. Moreover, this technology provides complemen-tary LTPS TFT’s with more than two times increase in on-current,3.5 times reduction in off-current compared to conventional thickchannel LTPS TFT’s.

Index Terms—AMLCD, ECTFT, LTPS, polysilicon, thin-filmtransistors, ultra-thin channel.

I. INTRODUCTION

L OW temperature poly-Si (LTPS) TFT technology appearsto be one of the most promising technologies for the ulti-

mate goal of building fully-integrated AMLCD system on glass[1]. The research efforts so far have been focused on the realiza-tion of digital circuits on glass [2], [3]. However, analog func-tionality must also be included in the data driving scheme inorder to achieve grey scale or full-color images [4], [5]. Thebasic building block for the analog circuits is an operationalamplifier. Due to the poor saturation and low on-current char-acteristics of the LTPS TFT’s, it is extremely difficult to im-plement the operational amplifier with useful voltage gain andbandwidth [4]. Moreover, the low on-current in the LTPS TFT,salso prevents the digital circuits on glass to meet the speed anddriving requirements for high resolution display.

For high on-current, TFTs with ultra-thin film have been pro-posed [6], [7]. However, these devices have the problems ofpoor drain/source contact, large series resistance, and low drainbreakdown. Short channel poly-Si devices were considered forhigh-speed digital circuit applications [4], [8]. Unfortunately,they suffer from a low drain breakdown voltage and cannot sat-

Manuscript received April 26, 1999; revised August 25, 1999. This work wassupported by the RGC Competitive Earmarked Research Grant, Hong KongS.A.R. Government, HKUST 6209/98E. The review of this paper was arrangedby Editor C. Y. Yang.

The authors are with the Department of Electrical and Electronic Engi-neering, The Hong Kong University of Science and Technology, Hong Kong,P.R.C (e-mail: eesin@ee.ust.hk).

Publisher Item Identifier S 0018-9383(00)01946-8.

isfy the driving requirements for digital circuits. On the otherhand, for good saturation characteristics, the elevated channelTFT (ECTFT) technology was proposed [9], [10]. However, thistechnology cannot provide ultra-thin film devices.

In this paper, a novel LTPS TFT technology called theultra-thin elevated channel TFT (UT-ECTFT) technologyis proposed. Experimental results show that this technologyprovides LTPS TFT devices with excellent saturation charac-teristics, much increased drain breakdown voltage, high currentdriving capability, and low leakage current. This technology isvery attractive for use in fully-integrated high resolution andfull-color AMLCD system on glass applications.

II. DEVICE STRUCTURE AND ANALYSIS

It is well known that poor saturation characteristics inLTPS TFT’s places a severe limitation on the application ofTFT devices for analog circuits. The poor saturation charac-teristics in poly-Si TFTs are caused by a similar mechanismwhich is responsible for the kink effect in SOI MOSFETs.The kink effect in SOI MOSFET’s is a combination of thechannel avalanche multiplication occurred in the high-fieldregion near the drain and the floating body effect at thechannel of the device [11]. However, in poly-Si TFTs, thereis an additional mechanism that causes the poor saturationcharacteristics. It is the high grain-boundary trap densityin the poly-Si material that exaggerates the effect of theavalanche multiplication [12]. So both the high electric fieldand high grain-boundary trap density at the channel nearthe drain have to be reduced effectively in order to obtainexcellent current saturation characteristics in the LTPS TFT’s[10]. The following paragraphs will show that the proposedUT-ECTFT devices will have both low electric field and lowgrain-boundary trap density at the channel near the drain.

The schematic cross-section of the n-channel UT-ECTFT isshown in Fig. 1. The device has an ultra-thin channel region(300 Å) and thick drain/source regions (3000 Å), and theultra-thin channel is connected with the thick source/drainregions through lightly doped n-regions. It has been foundin the earlier work that LTPS films with a thickness of morethan 200 Å will have a nearly constant grain-boundary trapconcentration [6]. This means that the trap density in LTPSfilms with a thickness of more than 200 Å is proportional tothe film thickness. Here, the trap density is defined as the ratioof the total traps in the channel to the channel area. Hence,the ultra-thin LTPS film (200 Å–300 Å) will have a lower trap

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570 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 3, MARCH 2000

Fig. 1. Schematic cross-section of the n-channel UT-ECTFT.

density, and the ultra-thin ECTFT devices will have improvedsaturation characteristics.

Another unique feature of the UT-ECTFT structure isthat the undoped ultra-thin channel region is connected to theheavily-doped thick drain/source region through a lightly-dopedoverlapped region. In addition to providing a graded impurityconcentration profile (similar to a conventional lightly dopeddrain (LDD) structure [13]), the lightly doped overlappedregion also provides a much increased drain junction depthassociated with the thick drain region [7]. At high drain biases,both the graded impurity concentration profile and the muchincreased drain junction depth provide an effective way forelectric field spreading at the drain, thereby reduces signifi-cantly the lateral electric field there. At the same time, the thickdrain/source region can be used to obtain good drain/sourcecontacts and reduced series resistance.

In order to demonstrate how much drain electric field isreduced in the UT-ECTFT compared to the conventional TFTdevices, two-dimensional (2-D) numerical simulations werecarried out using MEDICI [14]. MEDICI is a commonly used2-D numerical simulator for device analysis. For the sake ofsimplicity, the single crystalline silicon model available inMEDICI was employed to estimate the electric field in the var-ious LTPS TFT’s. In particular, the conventional drift-diffusionmodel, the local impact-ionization model, and the parametersreflecting the nature of LTPS material were used. In additionto the UT-ECTFT, the conventional TFT and ECTFT werealso simulated for the purpose of comparison. The schematiccross-sections of the conventional TFT and ECTFT used in thesimulations are shown in Fig. 2(a) and (b), respectively. Fig. 3shows the simulated lateral electric field distribution near thedrain/channel region for the various devices. Where theand are the gate length, channel thickness, and gate oxidethickness of the devices, respectively. It can be seen that thepeak lateral electric field in the UT-ECTFT is only 50% that ofin the conventional TFT, and 65% that of in the ECTFT. Withthe much reduced electric field at the channel/drain junctionand the minimized grain-boundary trap density in the channel,good current saturation and high drain breakdown voltage inthe UT-ECTFT are expected.

Fig. 2. Schematic cross-sections of the conventional TFT (a) and ECTFT (b).

Fig. 3. Simulated electric field distribution along the channel/drain junctionregion for the various TFT’s.

III. D EVICE FABRICATION

The complementary UT-ECTFT devices have been fabri-cated using a simple low temperature process (600 C). Fig. 4shows the schematic cross-sections of the major fabricationsteps of the UT-ECTFT technology with both n- and p-channeldevices. Silicon wafers with 8000 Å thermally grown oxidewere used as starting substrates. First, the thermal oxide ispatterned using dry etching to form grooves with a depth ofabout 3000 Å for the thick drain/source region as shown inFig. 4(a). Then, a 2000 Å-Si film was deposited at 550Cby LPCVD. After phosphorusDose cm ) andboron Dose cm ) implantations, another layer

ZHANG et al.: ULTRA-THIN ELEVATED CHANNEL POLY-Si TFT TECHNOLOGY 571

Fig. 4. Schematic cross-section of the major fabrication steps of theUT-ECTFT technology with complementary devices.

of 2000 Å of -Si film was deposited. Subsequently, the waferwas chemo-mechanically polished (CMP) down to the thermaloxide which is used as polish stop [Fig. 4(b)]. After that, a 300Å -Si film for the channel region was deposited at 550Cby LPCVD and patterned. The deposited-Si films were thenrecrystallized for 20 h in nitrogen ambient at 600C. Duringrecrystallization, the second deposited silicon film was alsolightly doped due to the phosphorus and boron out-diffusionfrom the bottom layer as shown in Fig. 4(c). Following thatwas the deposition of a 1000 Å APCVD gate oxide, anddeposition and patterning of a 2000 Å gate poly-Si. PhosphorusDose cm ) and boron Dose

cm ) implantations were then carried out again to heavilydope the gate and drain/source regions for the n- and p-channeldevices, respectively. Following that, a 0.4m thick LTO (lowtemperature oxide) was deposited, and the contact holes togate, source, and drain were defined after the LTO densificationat 600 C in oxygen ambient for 10 h. The dopants were alsoactivated during the densification of the LTO. The wafers werethen sintered at 400C after the metallization and patterning.Finally, the devices were hydrogenated using H2 rf plasma for2 h.

It is worth to point out that the process steps used in thefabrication are highly compatible to the conventional commer-cial TFT process. Only an extra chemo-mechanical polishing(CMP) step is needed. CMP process has been commonly usedin VLSI technology for multilevel metallization, shallow trenchisolation, etc. It is used here for the formation of the thickdrain/source regions only. It is not a critical step for determiningthe thickness of the channel as in the ECTFT technology [9],[10], in which ultra-thin channel was not possible, and the

Fig. 5. ExperimentalI–V characteristics of the complementary UT-ECTFTand conventional TFT. (a) n-channel, (b) p-channel.

ultra-thin channel with uniform thickness can be obtained heresimply by LPCVD.

IV. RESULTS AND DISCUSSION

Fig. 5 shows the experimental I-V characteristics of the com-plementary UT-ECTFTs and conventional uniform film TFTsfabricated on the same substrate. The channel thicknessofthe UT-ECTFTs is 300 Å, and those of the conventional TFTsare 300 Å and 1200 Å, correspondingly. It can be seen that theconventional TFT’s with thick channel (1200 Å) do not exhibita severe kink effect, but have only about half of the on-current ofthe UT-ECTFT devices at V. The conventional TFT’swith ultra-thin channel (300 Å) show good current saturationat low biases, but suffer from a severe kink at higher biases.However, in the UT-ECTFTs, kink effect is suppressed signif-icantly even at high biases (e.g., at V, Vfor n-channel and V, V for p-channel),and excellent current saturation characteristics were obtained.It is believed that the moderate kink in the thick film deviceis due mainly to a relatively low electric field at the channelnear the drain since the electric field decreases with increasingchannel thickness space [7]. For the conventional ultra-thin TFT,the good current saturation at low drain biases is due to fully-de-pletion at the channel [15], and the severe kink at high drainbiases is a result of the exaggerated avalanche multiplication atthe drain/channel junction caused by the high drain field and the

572 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 3, MARCH 2000

Fig. 6. Experimental output resistance as a function of drain-source voltagefor n-channel devices atV = 20 V.

large amount of grain-boundary traps. The excellent current sat-uration characteristics in the UT-ECTFT are attributed to a com-bination of the effective reduction in the drain electric field asshown in Fig. 4 and the fully-depletion of the ultra-thin channel.

Fig. 6 shows the experimental output resistance of thevarious n-channel TFT’s as a function of at V.The output resistance was measured using the reciprocal of theslope of the current–voltage (I–V) curves. It can be seen that theoutput resistance of the n-channel UT-ECTFT is about fourand20 times that of the conventional thick and thin channel TFT’s,respectively. For the p-channel devices, it is about 3.7 and 22times that of the conventional thick and thin channel TFT’s,respectively. Moreover, the UT-ECTFT has about two times (forn-channel) and four times (for p-channel) the on-current of theconventional thick channel device at V as shown inFig. 5. Based on these results, a simple voltage gain comparisonbetween the UT-ECTFTs and the conventional TFT’s can bemade. The simplified voltage gain for poly-Si TFT devicescan be shown as

(1)

where, and are the output resistance, tran-conductance, drain-source current in saturation regime, gate-source voltage, and threshold voltage, respectively. It can beshown from (1) that for n-channel devices, the voltage gain ofthe UT-ECTFTs is about eighttimes and 18 times that of theconventional thick and thin channel TFT’s, respectively, and forp-channel devices are 15 times and 20 times, respectively. Theseresults show that the UT-ECTFT devices can be used for highperformance analog circuit applications.

Fig. 7 shows the experimental gate transfer characteristicsof the various TFT’s. It is seen that the UT-ECTFT’s exhibitthe best device performance compared to the conventional de-vices. The threshold voltage was measured at a drain current of100 nA × (W/L) and a drain bias of 5 V for the n-channel de-vices (a drain current of−100nA × (W/L) and a drain bias of−5 V for the p-channel devices). As expected, the UT-ECTFT’shave the same threshold voltage (2.5 V for n-channel,−8 V forp-channel) as those of the ultra-thin film conventional TFT’s,which is a result of the same channel thickness used. As for

Fig. 7. Experimental gate transfer characteristics of the complementaryUT-ECTFT’s and conventional TFT’s.

Fig. 8. Experimental on-current as a function of channel thickness for theUT-ECTFTs. (a) n-channel, (b) p-channel.

the thick channel conventional TFT’s, higher threshold volt-ages (3.2 V for n-channel,−10.5 V for p-channel) were ob-tained, which implies that more traps exist in the thicker film.This makes the thicker channel more difficult to be inverted.In comparison to the thick channel TFT Å), theUT-ECTFTs have about 2.5 times (for n-channel, at

V and V) and 4.5 times (for p-channel atV and V) increase in on-current, 3.5 times (for

n-channel) and 5 times (for p-channel) reduction in minimumoff-current, and 1.6 times increase in carrier mobility (for bothn- and p-channel). Among the two ultra-thin film devices, theUT-ECTFT has 38% lower off-current at high reverse gate bi-ases V) due to the lower drain field, and 18% higheron-current at high forward gate biases V) due to thelower source/drain series resistance.

Figs. 8 and 9 show the experimental on-current and off-cur-rent, respectively, as a function of channel thickness for both then- and p-channel UT-ECTFT’s. The on-current and off-currentincreases and decreases, respectively, with decreasing channel

ZHANG et al.: ULTRA-THIN ELEVATED CHANNEL POLY-Si TFT TECHNOLOGY 573

Fig. 9. Experimental minimum off-current as a function of channel thicknessfor the UT-ECTFT’s. (a) n-channel, (b) p-channel.

TABLE IA SUMMARY OF THE DEVICE

CHARACTERISTICS FOR THEVARIOUS DEVICES

thickness. The improvement on the on- and off-current is at-tributed to the reduction in the grain-boundary trap density inthe channel with decreasing channel thickness. The lower grain-boundary trap density can lead to a lower threshold voltage andhigher carrier mobility, thereby increasing the on-current. It alsoleads to a reduction in the off-current since the off-current ori-gins from the field emission via the grain-boundary traps [16].Due to the non-optimization of the process, the p-channel de-vices exhibit relatively poor characteristics compared to thatof the n-channel devices. Device characteristics for the variousTFT’s are summarized in Table I.

Fig. 10 shows the experimental on-current as a function ofgate length for the UT-ECTFT with gate width equalto 1. It is seen that the on-current increases significantly (1.7

1It should be noted that the effective channel length will be different from thegate length. Due to the diffusion of the lightly implanted dopants, the ultra-thinpoly-Si layer above the overlapped region will be lightly doped during the sub-sequent annealing step. Thus, for a gate length of 10�m, the effective channellength is approximately 8�m.

Fig. 10. Experimental on-current as a function of gate length for theUT-ECTFT’s withW = L: (a) n-channel, (b) p-channel.

Fig. 11. Experimental breakdown voltage as a function of gate length for theUT-ECTFT’s and conventional TFT’s.

times) with the gate length reduced from 10m to 5 m. Thesignificant increase in on-current is due to the short channel ef-fect. It is very important to point out that short channel devicesshould be more suitable for high-speed digital circuit applica-tions, since they provide both large driving current and smalldevice parasitics. However, those devices fabricated using con-ventional technology suffer from a low drain breakdown voltagethat cannot satisfy the digital circuits driving requirement, andfor poly-Si TFT-LCD’s, a power supply of at least 15 V is gen-erally required.

Fig. 11 shows the experimental breakdown voltage as a func-tion of gate length for the UT-ECTFT (300 Å) and conventionalTFT (1200 Å). The breakdown voltage is defined as theat

nA and V. Note that the breakdown voltage ofthe conventional n-channel TFT decreases from 22 V to 12 Vwhen the gate length is reduced from 10m to 5 m. How-ever, for the UT-ECTFT’s with 10 m and 5 m gate lengths,breakdown voltages of 26 V and 19 V are obtained, respec-tively. The high breakdown voltage is mainly attributed to thelow peak electric field at the channel near the drain. The im-proved breakdown characteristics implies that the UT-ECTFT

574 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 3, MARCH 2000

devices are more suitable for channel scaled down for high per-formance digital circuit applications.

V. CONCLUSION

In this paper, a novel low temperature poly-Si (LTPS) tech-nology called the ultra-thin elevated channel TFT (UT-ECTFT)technology was proposed and experimentally demonstrated.The superior device characteristics of the n- and p-channelUT-ECTFTs were experimentally verified. Results indicatedthat the UT-ECTFT devices provide both excellent currentsaturation characteristics and high drain breakdown voltage.The on- and off-current characteristics of the UT-ECTFTdevices were also improved significantly. Furthermore, itwas shown that the UT-ECTFT devices are very suitable forchannel scaled down for high speed applications. All of thesemake the UT-ECTFT technology to be very attractive for theimplementation of high performance digital and analog circuitsfor fully-integrated AM-LCD system on glass applications.

ACKNOWLEDGMENT

The authors would like to thank Vitelic (H.K.) Ltd. for pro-viding the APCVD and ion implantation processes, and the fab-rication staffs at the HKUST for helping with the processing.

REFERENCES

[1] K. Werner, “The flowering of flat displays,”IEEE Spectrum, vol. 34, pp.45–49, 1997.

[2] Y. Matsuedaet al., “Low-temperature poly-Si TFT-LCD with integrated6-bit digital data drivers,” inDig. SID Int. Symp., 1996, pp. 89–92.

[3] F. Katoet al., “An 8-bit digital data driver for color TFT-LCDs,” inDig.SID Int. Symp., 1996, pp. 247–250.

[4] A. G. Lewis, D. D. Lee, and R. H. Bruce, “Polysilicon TFT circuit designand performance,”IEEE J. Solid State Circuits, vol. 27, pp. 1833–1841,1992.

[5] H. G. Yang, S. Fluxman, C. Reita, and P. Migliorato, “Design, measure-ment and analysis of CMOS polysilicon TFT operational amplifiers,”IEEE J. Solid State Circuits, vol. 29, pp. 727–732, 1994.

[6] M. Miyasakaet al., “Effects of channel thickness on poly-crystallinesilicon thin film transistors,” inExt. Abs. SSDM, 1995, pp. 647–650.

[7] M. Yoshimi et al., “Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 37, pp.2015–2020, 1990.

[8] M. Takabatakeet al., “CMOS circuits for peripheral circuit integratedpoly-Si TFT LCD fabricated at low temperature below 600C,” IEEETrans. Electron Devices, vol. 38, pp. 1303–1309, 1992.

[9] A. Kumar and K. P. and J. K. O. Sin, “A simple polysilicon TFT tech-nology for display systems on glass,” inIEDM Tech. Dig., 1997, pp.515–518.

[10] A. Kumaret al., “Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors,”IEEE Trans. Electron Devices, vol. 45, pp.2514–2520, Dec. 1998.

[11] J. P. Colinge, “Reduction of floating-substrate effect in thin-film SOIMOSFET’s,”Electron. Lett., vol. 22, pp. 187–188, 1986.

[12] M. Hack and A. G. Lewis, “Avalanche-induced effects in polysiliconthin-film transistors,”IEEE Electron Device Lett., vol. 12, pp. 203–205,1991.

[13] K. Tanaka, H. Arai, and S. Kohda, “Characterization of offset-struc-ture polycrystalline silicon thin-film transistors,”IEEE Electron DeviceLett., vol. 9, pp. 23–25, 1988.

[14] MEDICI User’s Manual, Version 1. Fremont, CA: Avant! Corp.,1999.

[15] J. P. Colinge, “Reduction of kink effect in thin-film SOI MOSFET’s,”IEEE Electron Device Lett., vol. 9, pp. 97–99, 1988.

[16] J. G. Fossum, A. Ortiz-Conde, H. Schichijo, and S. K. Banerjee,“Anomalous leakage current in LPCVD polysilicon MOSFET’s,”IEEETrans. Electron Devices, vol. ED-32, pp. 1878–1884, 1985.

Shengdong Zhangwas born in Nanjing, China, onOctober 8, 1964. He received the B.S. and M.S. de-grees from Southeast University, Nanjing, in 1984and 1992, respectively, both in electrical and elec-tronic engineering.

From 1984 to 1985, he was with the Beijing Air-craft Technology Institute, Beijing, as an AssociateEngineer working on the design and fabrication ofpressure sensors. In 1985, he joined the Nanjing Elec-tronic Device Institute (NEDI), where he first workedon the fabrication of optoelectronic devices based on

silicon-target and later was engaged in the development of AM-LCD’s. FromOctober 1996 to September 1998, he was a Research Assistant in the Depart-ment of Electrical and Electronic Engineering, Hong Kong University of Sci-ence and Technology, Hong Kong, where he worked on the research and devel-opment of SOI and poly-Si TFT devices. He is presently with Institute of Mi-croelectronics, Peking University, Beijing. His current research areas are 3-Dpoly-Si device and deep sub-micrometer SOI device technologies.

Chunxiang Zhu was born in Hangzhou, China, in1969. He received the B.S. degree in electronic ma-terial in 1992, and M.S. degree in electronic engi-neering in 1995, both from Xidian University, Xi’an,China. Since 1996, he has been pursuing the Ph.D.degree at the Hong Kong University of Science andTechnology, Hong Kong.

His current research interest is in the area ofthin-film transistors.

Johnny K.O. Sin (S’79–M’88–SM’96) was born inHong Kong. He received the B.A.Sc., M.A.Sc., andPh.D. degrees, all in electrical engineering, in 1981,1983, and 1988, respectively, all from the Universityof Toronto, Toronto, Ont., Canada.

He joined Philips Laboratories, Briarcliff Manor,NY, upon the completion of his Ph.D. studies,where he was a Senior Member of Research Stafffrom 1988 to 1991. He joined the Department ofElectrical and Electronic Engineering, Hong KongUniversity of Science and Technology, Hong Kong,

in August 1991, as an Assistant Professor. He was promoted to AssociateProfessor in 1996. He is one of the founding members of the Department, andhas been serving as the Director of the Undegraduate Studies Program in theDepartment since Fall 1998. His research interests lie in the general area ofmicroelectronic devices and fabrication technology, and is currently workingin the areas of power semiconductor devices and IC’s, thin-film transistors,field emission devices, integrated sensors, silicon-on-insulator rf and powerdevices and technology. He has published over 130 papers in technical journalsand refereed conference proceedings in the above areas. He holds three U.S.patents and has four patents pending.

Dr. Sin is an Editor of IEEE ELECTRONDEVICE LETTERS. He is a member ofthe EDS Power Devices and IC’s Technical Committee. He served as technicalcommittee member of the International Conference on Microelectronics TestStructures (ICMTS). He is also a technical committee member of the Interna-tional Symposium on Power Semiconductor Devices and IC’s (ISPSD). He wasmade an Honorary Visiting Professor of the Dalian University of Technology,Dalian, China, in 1996. In Fall 1998, he was awarded the Teaching ExcellenceAppreciation Award by the School of Engineering at the University.

J. N. Li , photograph and biography not available at the time of publication.

ZHANG et al.: ULTRA-THIN ELEVATED CHANNEL POLY-Si TFT TECHNOLOGY 575

Philip K. T. Mok (S’86–M’95) received hisB.A.Sc., M.A.Sc., and Ph.D. degrees in electricaland computer engineering from the University ofToronto, Toronto, Ont., Canada, in 1986, 1989, and1995, respectively.

While at the University of Toronto, he was aTeaching Assistant in both the Electrical Engi-neering and Industrial Engineering departmentsfrom 1986 to 1992. He taught courses in circuittheory, IC engineering and engineering economics.He was also employed as a Research Assistant

in the Integrated Circuit Laboratory, University of Toronto, from 1992 to1994. He joined the Department of Electrical and Electronic Engineering,Hong Kong University of Science and Technology, Hong Kong, in January1995 as an Assistant Professor, where he is now also the Associate Directorof the Computer Engineering Programme. His research interests includesemiconductor devices, processing technologies, and circuit designs for powerelectronics and telecommunications applications, with current emphasis onpower integrated circuits and low-voltage analogue integrated circuits design.

Dr. Mok received the Henry G. Acres Medal, the W. S. Wilson Medal andTeaching Assistant Award from the University of Toronto, and the TeachingExcellence Appreciation Award from the Hong Kong University of Science andTechnology.