ultra-thin chips - a new paradigm in si technology
TRANSCRIPT
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INSTITUT FÜR MIKROELEKTRONIK STUTTGARTINSTITUT FÜR MIKROELEKTRONIK STUTTGART
Ultra-Thin Chips
- A New Paradigm in Si Technology -
Joachim N. Burghartz
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Outline• Ultra-thin chips: the paradigm shift
• Applications of ultra-thin chips Traditional, recent and potential future applications 3D ICs: Overcoming a bottleneck in CMOS scaling Systems-in-Foil (SiF): enabler for new applications
• Ultra-thin chip fabrication Post-process wafer thinning Thin chips based on SOI Chipfilm™ technology
• Characteristics of ultra-thin chips Warpage of thin chips Mechanical stability of thin chips Apparently anomalous piezoresistive effect
• Constraints for circuit design
• Conclusions
Ultra-Thin Chips: A New Paradigm 2/11 © IMS 20112
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Ultra-Thin vs. Thin Chips: the paradigm shift
• Thick chips and wafers (conventional) 300 μm – 1000 μm:
Mechanically stiff and stable
• Thin chips and wafers (conventional) 100 μm – 300 μm:
Mechanically stiff with limited stability Reduced thermal resistance
• Ultra-thin chips and wafers 50 μm – 100 μm:
Limited stiffness and limited stability
10 μm – 50 μm: Flexibile with good stability
< 10 μm: Flexible with good stability Optically transparent
Ultra-Thin Chips: A New Paradigm 2/11 © IMS 20113
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Properties of Ultra-Thin Chips and Wafers
• Mechanical Warpage, curl-up Young‘s modulus may deviate from bulk-Si value!
Rough edges, e.g. from dicing Rough backside, e.g. from polishing Topographic frontside from layer depositions
• Electrical Piezoresistive effect Backgate effects
• Optical Absorption spectrum limited Back-surface effects
• Thermal Bi-material displacement
Ultra-Thin Chips: A New Paradigm 2/11 © IMS 20114
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Processing Issues for Ultra-Thin Wafers/Chips
• Front-end processes Handle/carrier substrates needed Overheating effects (high-dose implant, RTP)
• Back-end processes Excessive warpage from stress in interconnect layer stack
• Packaging and assembly Edge chipping in dicing processes Chip detachment from tape and transfer in assembly Chip attachment to package Mechanical pressure in wire bonding processes
Ultra-Thin Chips: A New Paradigm 2/11 © IMS 20115
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Outline• Ultra-thin chips: the paradigm shift
• Applications of ultra-thin chips Traditional, recent and potential future applications 3D ICs: Overcoming a bottleneck in CMOS scaling Systems-in-Foil (SiF): enabler for new applications
• Ultra-thin chip fabrication Post-process wafer thinning Thin chips based on SOI Chipfilm™ technology
• Characteristics of ultra-thin chips Warpage of thin chips Mechanical stability of thin chips Apparently anomalous piezoresistive effect
• Constraints for circuit design
• Conclusions
Ultra-Thin Chips: A New Paradigm 2/11 © IMS 20116
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Applications of Ultra-Thin Chips
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/117
Chip card
Ultra-thin and power
Backilluminatedimager
Mini Endoscope
Retinalimplant
Video pill
RF ID
Electronicpaper
Documentsecurity
Mechanical flexibility
Chip form and adaptivity Ultra-thin chips
3D chip stacking
Stacked microsystems
3D IC
Smart dust
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Outline• Ultra-thin chips: the paradigm shift
• Applications of ultra-thin chips Traditional, recent and potential future applications 3D ICs: Overcoming a bottleneck in CMOS scaling Systems-in-Foil (SiF): enabler for new applications
• Ultra-thin chip fabrication Post-process wafer thinning Thin chips based on SOI Chipfilm™ technology
• Characteristics of ultra-thin chips Warpage of thin chips Mechanical stability of thin chips Apparently anomalous piezoresistive effect
• Constraints for circuit design
• Conclusions
Ultra-Thin Chips: A New Paradigm 2/11 © IMS 20118
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Bottlenecks in CMOS Scaling
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/119
45
40
35
30
25
20
15
10
5
0650 500 350 250 180 130 100
Generation (nm)
Delay (ps)
Gate + Al/SiO2
Gate + Cu/Low-k
Gate
Al/SiO2
Cu/Low-k
Interconnect Delay
Transistor Subthreshold slope Gate oxide thickness Shallow junctions # dopants in channel…………
WattChip power
0
40
80
120
160
1985-386CPU
1989-486CPU
1993-Pentium
1997-P2CPU
2001-Itanlium
3D chip stacking:• Shorter interconnects• Relaxed device dimensions• Power-delay tradeoff (?)
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Interconnect Delay and Yield
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1110
2D
3D
0
20
40
60
80
1,E+02 1,E+03 1,E+04 1,E+05 1,E+06 1,E+07
Defects (m-2)
Yiel
d (%
)
(A=10 mm2)
(A=100 mm2)
(A=1 cm2)
(A=10 cm2)
100
Technology Node (nm)
250 180 130 90 65 45 320.1
1.0
10
100
Rel
ativ
e D
elay
Gate delayLocal wires (scaled)Global wires with repeatersGlobal wires without repeaters
• Smaller interconnect RC delays through shorter wires !
• Higher process yield through smaller chip area !
2D
3D
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3D-IC Integration Concepts
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1111
Wafer-to-wafer1. CMOS integration 2. Wafer thinning 4. Wafer attachment3. Through-chip vias
Chip-to-wafer and Chip-to-Chip4. Chip attachment1. CMOS chip 2. Chip thinning 3. Through-chip vias
Minimum thickness? Via diameter? Process yield?
Throughput? Throughput?
Process yield!
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Through-Chip-Via Process
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1112
Source: FhG-IZM
More than 10:1 aspect ratio is difficult to achieve !
Need for ultra-thin chips postulated on ITRS Roadmap
Via Formation for VSI – Via Metal Filling
Process for filling
1.0 µm 3.5 µm 5 µm 10 µm … 100 µm Via-Diameter
CVD of- copper- tungsten- TiN
Electroplating of- copper
& PVD of Seedlayer- Ti:W / Cu
Electroplating of- copper
& CVD of Seedlayer- tungsten
new!
10:1 3:1 2:1 … 7:1 1:1 Aspect Ratio10 µm 70 µm 100 µm Via-Depht
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Outline• Ultra-thin chips: the paradigm shift
• Applications of ultra-thin chips Traditional, recent and potential future applications 3D ICs: Overcoming a bottleneck in CMOS scaling Systems-in-Foil (SiF): enabler for new applications
• Ultra-thin chip fabrication Post-process wafer thinning Thin chips based on SOI Chipfilm™ technology
• Characteristics of ultra-thin chips Warpage of thin chips Mechanical stability of thin chips Apparently anomalous piezoresistive effect
• Constraints for circuit design
• Conclusions
Ultra-Thin Chips: A New Paradigm 2/11 © IMS 201113
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RF ID Tag
Ultra-Thin Chips: A New Paradigm 2/11
Warehouse storage
Department store sales
Low-cost printing
Roll-to-roll assembly
Source: Metro
© IMS 201114
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ePaper
Ultra-Thin Chips: A New Paradigm 2/11 © IMS 201115
Source: Unidym
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Document Security
Ultra-Thin Chips: A New Paradigm 2/11
Source: NXP
© IMS 201116
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Hybrid Systems-in-Foil
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1117
Si Circuit
Organic Circuit
Thin Film Electronics• Pro: devices widely spaced• Con: low integration density• Pro: flexibility
Source: FhG-IZM
Hybrid systems-in-foil = combining technologies with complementary merits!
Si Integration• Con: devices on chip• Pro: high integration• Con: thick Si chips
+
• Pro: thin, flexible chips !
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Outline• Ultra-thin chips: the paradigm shift
• Applications of ultra-thin chips Traditional, recent and potential future applications 3D ICs: Overcoming a bottleneck in CMOS scaling Systems-in-Foil (SiF): enabler for new applications
• Ultra-thin chip fabrication Post-process wafer thinning Thin chips based on SOI Chipfilm™ technology
• Characteristics of ultra-thin chips Warpage of thin chips Mechanical stability of thin chips Apparently anomalous piezoresistive effect
• Constraints for circuit design
• Conclusions
Ultra-Thin Chips: A New Paradigm 2/11 © IMS 201118
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Process Technologies for Ultra-Thin Chips
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1119
Wafer back thinning SOI layer transfer
Additive process
ChipfilmTM
Subtractive processes
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Outline• Ultra-thin chips: the paradigm shift
• Applications of ultra-thin chips Traditional, recent and potential future applications 3D ICs: Overcoming a bottleneck in CMOS scaling Systems-in-Foil (SiF): enabler for new applications
• Ultra-thin chip fabrication Post-process wafer thinning Thin chips based on SOI Chipfilm™ technology
• Characteristics of ultra-thin chips Warpage of thin chips Mechanical stability of thin chips Apparently anomalous piezoresistive effect
• Constraints for circuit design
• Conclusions
Ultra-Thin Chips: A New Paradigm 2/11 © IMS 201120
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Wafer Back-Thinning: Process Sequence
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1121
Economically practical wafer thickness >50 μm ! (NXP)
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Wafer Back-Thinning: Mechanical Stability
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Fast grinding processes introduce more defects than slow etch processes
Combination of fast grinding followed by defect removal steps
Die Strength (Ball Ring Method), 75 µm 10x10 mm2
CMP 3µm
Remote Cold Dry Etch 3µm
Wet Etch 20µm
Characteristic Die Strength @ 63,2%
MDS
CDS*DP 3µm
*GR2
GR1
Minimum Die Strength @ 1%
Source: PVA-TePla
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Process Effects on Mechanical Stability
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1123
CDS
MDS
Flexural Stress
Prob
abili
ty o
f Bre
akag
e
99,9
0.10.20.4
124
102030
7050
%
100 200 400 1000 2000 4000 10000 20000 MPs
Ball-Ring-Method 3-Point-Method
CDS
MDS
Flexural Stress
99,9
0.10.20.4
124
102030
7050
%
100 200 400 1000 2000 4000 10000 20000 MPs
Prob
abili
ty o
f Bre
akag
eSource: PVA-TePla
75 µm 10x10 mm2 75 µm 10x10 mm2
Surface and edge quality of thin chips affect mechanical stability
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Dicing-by-Thinning concept DbyT“
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1124
Manufacture and transfer of 20 µm thin chips
Prepare front side groves by etching or sawing
Reversible bonding onto carrier and wafer thinning
Chip separation by wafer thinning, transfer of thin dies
Wafer thinning: Grinding, etching, polishing
Device wafer
Carrier wafer Carrier wafer
Device wafer
Source: FhG-IZM
Improved edge quality and thus mechanical stability
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Outline• Ultra-thin chips: the paradigm shift
• Applications of ultra-thin chips Traditional, recent and potential future applications 3D ICs: Overcoming a bottleneck in CMOS scaling Systems-in-Foil (SiF): enabler for new applications
• Ultra-thin chip fabrication Post-process wafer thinning Thin chips based on SOI Chipfilm™ technology
• Characteristics of ultra-thin chips Warpage of thin chips Mechanical stability of thin chips Apparently anomalous piezoresistive effect
• Constraints for circuit design
• Conclusions
Ultra-Thin Chips: A New Paradigm 2/11 © IMS 201125
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Philips‘s Circonflex Technology
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1126
a b c d
transmit backantenna @ 345 MHz
Power amplifier
magnetic loop antenna @ 690 MHz
power supply + dividerAccidental detachment of Si-on-GlassLead to Philips‘s Circonflex technology
Source: R. Dekker, Philips
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Outline• Ultra-thin chips: the paradigm shift
• Applications of ultra-thin chips Traditional, recent and potential future applications 3D ICs: Overcoming a bottleneck in CMOS scaling Systems-in-Foil (SiF): enabler for new applications
• Ultra-thin chip fabrication Post-process wafer thinning Thin chips based on SOI Chipfilm™ technology
• Characteristics of ultra-thin chips Warpage of thin chips Mechanical stability of thin chips Apparently anomalous piezoresistive effect
• Constraints for circuit design
• Conclusions
Ultra-Thin Chips: A New Paradigm 2/11 © IMS 201127
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Chipfilm™ Technology
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1128
Chipfilm™ Wafer CMOS Process Pick, Crack & Place™
Buried cavities Chip singulation
Trench & Test
Anchor structures• lateral (Chipfilm™-I)• vertical (Chipfilm™-II)
Device integration
IEDM 2006 Late News: Introduction of Chipfilm™-I
IEDM 2010: Introduction of Chipfilm™-II
Since July 2008: Joint development with Robert Bosch GmbH
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Chipfilm™ vs. Back-Thinning
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1129
CMOSPre-Process Assembly
Standardwafer
thinning
Thinning Dicing Packaging
handle wafer
Handle wafer
handle wafer
Thinning and dicing
Tape Packaging
Waferthinningfor very
thin chips
Chipfilm™ Pick, Crack and Place TM
Chipfilm™Technology
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The ChipfilmTM Pre-Process
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1130
Fine Porous Si
Wafer Surface
Coarse Porous Si
Step1:• Anodic etching of a Si wafer
Dual porous Si formation Masking through n+ doping
Chip Divider Trench Chip Area
Epi Si Layer
Sintered Porous Si Layer
Cavity
Silicon Substrate
Step2:• Sintering in oxygen-free ambient
Silicon reflow Fine porous Si Nano grains Coarse porous Si Buried cavity
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The Paick, Crack & Place™ Post-Process
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Technology Comparison
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1132
• Chipfilm™-I Continuous cavity Lateral anchors
• Chipfilm™-II– Discontinuous cavity– Vertical anchors
Si wafer
Chip
Si wafer
Chips
Pros:+ Thickness limit < 20μm
Cons:- Surface steps (~ 200nm)- Predefined chip size
Pros:+ Thickness limit < 20μm+ High planarity (ravg~ 7nm)+ Generic wafer substrate
IEDM 2006 IEDM 2010
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Chipfilm™-II Technology Process
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• Pre-process module (I) n-implant anodic etching thermal annealing epitaxial growth
• Device Integration
• Post-process module Trench etching Chip detachment
n n nn nn
p-type wafer
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Chipfilm™-II Technology Process
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1134
• Pre-process module (I) n-implant anodic etching thermal annealing epitaxial growth
• Device Integration
• Post-process module Trench etching Chip detachment
n n nn nn
p-type wafer
coarseporous Si
fineporous Si
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Chipfilm™-II Technology Process
© IMS 2011Ultra-Thin Chips: A New Paradigm 2/1135
• Pre-process module (I) n-implant anodic etching thermal annealing epitaxial growth
• Device Integration
• Post-process module Trench etching Chip detachment
n n nn nn
p-type wafer
sinteredporous Si
(sPS)narrow cavity
coarseporous Si
fineporous Si