Ultra-shallow junction formation by spike annealing in alamp-based or hot-walled rapid thermal annealing system:

e�ect of ramp-up rate

Aditya Agarwal a, *, Anthony T. Fioryb, Hans-Joachim L. Gossmannb,Conor S. Ra�ertyb, Peter Frisella c

aSemiconductor Equipment Operations, Eaton Corporation, Beverly, MA 01915, USAbBell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA

cThermal Processing Systems, Eaton Corporation, Beverly, MA 01915, USA

Abstract

Ultra-shallow p-type junction formation has been investigated using 10508C spike anneals in lamp-based and hot-

walled rapid thermal processing (RTP) systems. A spike anneal may be characterized by a fast ramp-up totemperature with only a fraction of a second soak-time at temperature. The e�ects of the ramp-up rate during aspike anneal on junction depth and sheet resistance were measured for rates of 40, 70 and 1558C/s in a lamp-based

RTP, and for 50 and 858C/s in a hot-walled RTP. B+ implants of 0.5, 2 and 5 keV at doses of 2 � 1014 and2 � 1015 cmÿ2 were annealed. A signi®cant reduction in junction depth was observed at the highest ramp-up rate forthe shallower 0.5-keV B implants, while only a marginal improvement was observed for 2- and 5-keV implants. It is

concluded that high ramp-up rates can achieve the desired ultra-shallow junctions with low sheet resistance but onlywhen used in combination with spike anneals and the lowest energy implants. # 1999 Elsevier Science Ltd. Allrights reserved.

1. Introduction

Future device technology requires the ability to form

extremely shallow junctions which simultaneously have

a very low sheet resistance [1]. Though junction depth,

xj, can be limited by annealing for a su�ciently short

time at a greatly reduced temperature, e.g. 7508C/10 s,

this results in decreased dopant activation and insu�-

cient damage removal leading to a large sheet resist-

ance, Rs, and increased junction leakage, respectively.

It is thus necessary to anneal at the highest tempera-

ture possible while limiting the total thermal budget

for dopant di�usion. The thermal budget can be mini-

mized by increasing the temperature ramp-up rate, and

at the same time by decreasing the annealing time, to

the limits allowed by the annealing equipment. Such

an anneal is referred to as a spike anneal in contrast to

a soak standard rapid thermal anneal (RTA), where

the ramp-up rate of 1508C is not maximized and the

soak-time is a few seconds.

The dopant implantation process inevitably results

in implantation-induced damage, i.e. Frenkel pairs

consisting of vacancies and interstitials. During the in-

itial stage of annealing most of the vacancies and inter-

stitials recombine leaving behind a net excess of

interstitials approximately equal to the implanted ion

dose, the ` + 1' approximation [2]. These excess inter-

stitials quickly coalesce into extended defects. The

extended defects are metastable however and sub-

sequently dissolve. As long as extended defects exist,

an interstitial supersaturation is maintained, resulting

in a boron di�usion enhancement. The enhancement

ends soon after the defects have dissolved; the di�usion

enhancement is thus transient. A consideration of the

interstitial supersaturation and of the time to defect

Materials Science in Semiconductor Processing 1 (1998) 237±241

1369-8001/99/$ - see front matter # 1999 Elsevier Science Ltd. All rights reserved.

PII: S1369-8001(98 )00030-4

PERGAMON

* Corresponding author. E-mail: aagarwal@bev.etn.com

dissolution [3] allows the increase in junction depth,Dxj, due to dissolution of interstitial-type defects, to be

expressed as [4]

Dx 2j ARp � exp�ÿ�ÿEf � EB ÿ Em��, �1�

where Rp is the projected ion range, Ef+Em=4.920.1eV, is the activation energy for Si self di�usion and

EB=3.46 eV [5], is the energy barrier for B di�usion.The activation energy of Dxj is therefore 1ÿ 1.4 eVwhen boron di�usion is dominated by interstitial-type

defect dissolution [4]. The linear dependence of TEDon Rp, predicted by Eq. (1), was recently demonstratedexperimentally [6, 7] and is the reason why lower

energy implants result in reduced TED. The secondprediction of Eq. (1), the negative activation energy ofDxj, means that if TED is allowed to run its course at7508C, the resulting junction will be deeper than if it

was formed at 10008C. This is one of the main reasonsthat RTA was adopted as a replacement for traditionalfurnace annealing for junction activation. The negative

activation energy of TED is also the most compellingargument for ramping-up the temperature at a veryhigh rate; the less time spent at the lower temperature,

the less enhanced di�usion of boron will occur. Sincethe ®rst report of ramp-up rates as high as 4008C/s [8]there has been an enormous interest in the industry in

determining the technology node [1] at which highramp rates will be essential for forming su�cientlyshallow junctions with low Rs.In this work we have investigated the e�ect of ramp-

up rate on junction parameters such as Rs and xj forvarious combinations of B energy and doses. Ananalysis of di�usion enhancement during spike anneal-

ing will be reported elsewhere [9].

2. Experimental

B was implanted into 150 mm n-type Si wafers to ahigh dose of 2 � 1015 cmÿ2 at 0.5, 2 or 5 keV; and to alow dose of 2 � 1014 cmÿ2 at 0.5 and 5 keV. Thewafers were then annealed in an AG Associates HP

8108 lamp-based RTA at ramp-up rates of 40, 70 and1558C/s and in an Eaton Reliance 850 hot-walled fur-nace1 at 55 and 858C/s2. The annealing recipes were es-

pecially designed to achieve spike annealing. Standard

3 s soak anneals were also done in the lamp-basedRTA with the maximum ramp-up rate of 1558C/s. Theramp-down rate was constant for all anneals at1708C/s in the lamp-based RTA or 1608C/s in the hot-walledRTA. After annealing, all wafers were Rs-mapped. Rs

uniformity (1ÿastandard deviation) ranged from 0.7to 9.5% for the lamp-based system and 0.5 to 4% forthe hot-walled system. No e�ort was made in this ex-

periment to improve uniformity on either RTA systemsince the goal was to achieve high ramp rates with theshortest anneal time. Pieces from selected wafers were

analyzed by secondary ion mass spectroscopy (SIMS).Care was taken to analyze the portion of the waferwhere the temperature was measured by the pyrometerand Rs values reported here correspond to the same

portion.

3. Results and discussion

The Rs data for all spike-annealed wafers are shownin Fig. 1a. For all energy and dose combinations Rs

increases with the ramp-up rate, regardless of the fur-nace type. It is interesting to note that the percent

increase in Rs (Fig. 1b) is greater when the ramp-uprate is increased from 70 to 1558C/s than when it isincreased from 40 to 708C/s. Though the reduction in

thermal budget by increasing the ramp-up rate from 70to 1558C/s is smaller, the penalty imposed by theincreasing sheet resistance is larger.

For both types of furnaces higher ramp-up rateslead to shallower junctions for the high B dose of2 � 1015 cmÿ2 at 0.5 keV (Fig. 2a). The hot-wall

annealed pro®les are slightly deeper than the compar-able rate pro®les in the lamp-based system (Fig. 2a),consistent with the lower Rs values (Fig. 1a). A com-parison of the lamp-based data for di�erent energies

reveals that the reduction in xj achieved by increasingthe ramp-up rate from 40 to 70 to 1558C/s is greaterfor the shallower 0.5-keV implant (Fig. 2a) than for

the deeper 2-keV implant (Fig. 2b). The same trend isalso observed for the lower B dose of 2 � 1014 cmÿ2

(Fig. 3); while the high ramp-up rate of 1558C leads to

a shallower junction for the 0.5-keV implant, no di�er-ence can be discerned in the 5-keV pro®les for di�erentramp-up rates. Note that the larger percentage increasein Rs with an increase in ramp-up rate from 70 to

1558C/s (Fig. 1b) is not accompanied by a largerdecrease in xj (Fig. 2a and b). Indeed xj decreases lessfrom 70 to 1558C/s than from 40 to 708C/s, for both

0.5 and 2 keV B.The data in Figs. 1±3 can be summarized by consid-

ering Rs as a function of xj (Fig. 4). The data from

this work are grouped by the B energy and dose com-bination. The trend pointed out in the previous sectionof diminishing advantage from a high ramp-up rate

1 The hot-walled furnace consists of a SiC or quartz bell jar,

which is continuously resistively-heated at the top, establish-

ing a thermal gradient from top to bottom. A wafer is heated

by raising it to the appropriate height, while high ramp-up

rates are achieved by varying its height rapidly.2 The ramp-up rate was calculated using the time from 700

to 10508C. Instantaneous rates during the 858C/s ramp-up

exceeded 1008C/s.

A. Agarwal et al. /Materials Science in Semiconductor Processing 1 (1998) 237±241238

with increasing implant energy is also apparent in

Fig. 4 where the vertical and lateral spread (Rs and xj,

respectively) between data points corresponding to

di�erent ramp-up rates decreases with increasing

implant energy, for both furnace types. In other

words, the impact of higher ramp-up rates decreases

with increasing implant energy.

Data points for other annealing conditions are also

included in Fig. 4 to help determine the relative advan-

tages of spike anneals over standard anneals:

1. Soak time at high ramp-up rates: if the soak time

for the high dose 0.5-keV B implant is increased

from 0 to 3 s, xj increases from 45 to 77 nm (Fig. 2a

and Fig. 4). Moreover, despite having had the high-

est ramp-up rate of 1558C/s, after a 3 s anneal the

xj and Rs combination for the 0.5-keV implant is

not signi®cantly di�erent than for the higher energy2-keV implant. It appears then that the advantage

of high ramp-up rate for a low energy 0.5-keVimplant can be fully realized only by a spike anneal,

i.e. with soak time <<1 s. It can also be said thatthe advantage gained by reducing the implant

energy can be compromised by performing a stan-dard anneal instead of a spike anneal. The large

increase in xj upon annealing for 3 s also raises con-cerns about the di�culty in controlling time during

the spike anneal process.

2. Lower temperature standard anneals: also shown inFig. 4 is that a standard 10008C, 10 s anneal of 2

keV B leads to xj and Rs values which are very simi-lar to those from a 10508C spike anneal. These

results imply that for 2 keV B a standard soakanneal at a reduced temperature can lead to the

same junction properties as a more aggressive spikeanneal.

Fig. 4 also includes data points from a process op-

timization experiment which included a preamorphiza-tion step and spike anneals with ramp-up rates as high

Fig. 1. (a) Sheet Resistance, Rs, as a function of ramp-up rate

for various energy and dose combination B implants after

10508C spike annealing. Anneals at 40, 70 and 1558C/s ramp-

up rates were carried out in a lamp-based RTA and at 50 and

858C/s in a furnace-based RTA. (b) Percentage increase in Rs

for a change in ramp-up rate from 40 to 708C/s and 70±

1558C/s.

Fig. 2. SIMS B pro®les as function of ramp-up rate for

10508C spike anneals (a) for 0.5 keV, 2 � 1015 cmÿ2 B in a

lamp-based and hot-walled RTA and (b) 2 keV, 2 � 1015 cmÿ2

B in a lamp-based RTA.

A. Agarwal et al. /Materials Science in Semiconductor Processing 1 (1998) 237±241 239

as 4008C [10]. The data from Ref. [10] are quite similarto the data from this work, making it apparent thatdi�erent implant and annealing options are available

for achieving comparable shallow junction depths andsheet resistance. Our experiment does not howevermeasure leakage current, which is expected to vary

with residual damage following annealing. The ramp-up rate is only one variable which a�ects the junction.

The complete list of variables must include implantspecies, energy and dose; preamorphization species, E,

and dose (if any); annealing temperature and time;

annealing ambient and postprocessing temperature andtime. Of course, the junction anneal process must be

optimized in concert with the impact of temperature,time, ambient and ramp-rates on the n-type junction.

However, despite the large number of contributors

to the junction properties, it is still possible to isolatethe contribution of the ramp-up rate as has been done

here. From the data presented here it is apparent that

a high ramp-up rate can signi®cantly reduce xj andsimultaneously achieve low Rs values for 0.5-keV B

implants. The improvement decreases rapidly howeverwith increasing implant energy.

The ®rst of two parameters we use to describe the

spike anneal is the peak temperature during the anneal.In our experiment the standard deviation in peak tem-

perature increased from <18C at the lowest ramp-uprate of 408C/s to >68C at the highest rate of 1558C/s.It is unknown at this time how much this run-to-runrepeatability can be improved by optimizing the con-

trol system or even what the standard deviation corre-

sponds to in process nonuniformity. It is, however,clear that the repeatability would only degrade with

higher ramp-up rates.

The second metric which we have used is the timespent above 10008C, plotted in Fig. 5 for all anneals in

both furnaces. The time above 10008C for spikeanneals in the hot-wall furnace is 11 s longer than in

the lamp-based system explaining both the slightly dee-per junctions and the better uniformity. As with the

peak temperature standard deviation in time alsoincreases with ramp-up rate. For the highest rate of

1558C/s increasing soak time to 3 s reduces the

Fig. 3. SIMS B pro®les for 2 � 1014 cmÿ2 B at 0.5 and 5 keV

after 10508C lamp-based spike RTA with ramp-up rates of 40

or 1558C/s.

Fig. 4. Comparison Rs vs. xj data for spike and standard

anneals from this work and from Ref. [10], in which

1015 cmÿ2 1 keV B was preceded by preamorphization with

1015 cmÿ2 5 keV Ge. Ramp-up rates of 155, 70 and 408C/scorrespond to the lamp-based system, while 85 and 508C cor-

respond to the hot-walled system.

Fig. 5. Time spent above 10008C for all of the anneals (data

from the dummy wafers run prior to each implanted wafer).

The standard deviation in time (s) is noted for each type of

anneal.

A. Agarwal et al. /Materials Science in Semiconductor Processing 1 (1998) 237±241240

standard deviation. As expected, control of both timeand temperature degrade with increasing ramp-up rate.

It remains to be seen how reliable and repeatable aspike anneal can be made.

4. Summary and conclusions

We have carried out an experiment to determine thee�ect of the ramp-up rate during spike annealing onthe formation of ultra-shallow junctions in a lamp-

based RTP and also for the ®rst time in a hot-walledRTP system. Using various implantation energies anddoses, it has been demonstrated that while there is a

signi®cant advantage from a higher ramp-up rateduring spike annealing for low energy 0.5 keVimplants, the advantage is comparatively marginal forhigher energy 2-keV implants. It is also observed that

the degradation in sheet resistance with increasingramp-up rates is greater than the improvement in junc-tion depth.

Acknowledgement

We thank John Jackson and Michael Walsh ofEaton Implant Systems Division for the low energy B

implants.

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