uart.b
TRANSCRIPT
DESIGN OF UNIVERSAL ASYNCHRONOUS RECEIVER
AND TRANSMITTER BY USING VHDL
A Project report
Submitted In partial fulfillment of the requirements
For the award of degree of
BACHELOR OF TECHNOLOGY
In
ELECTRONICS AND COMMUNICATION ENGINEERING
By
B.RASAZNA (08A51A0417) D.PRIYANKA (08A51A0426)
I.SIVAJI (08A51A0444) B.SRINU (08A51A0418)
Under the esteemed guidance of
Sri K.CHIDAMBARA RAO ,M.Tech
Asso. Professor
E.C.E Department
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
ADITYA INSTITUTE OF TECHNOLOGY AND MANAGEMENT
TEKKALI, ANDHRA PRADESH
2011
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
ADITYA INSTITUTE OF TECHNOLOGY AND MANAGEMENT
TEKKALI
CERTIFICATE
This is to certify that the mini project work entitled “ DESIGN OF UNIVERSAL
ASYNCHRONOUS RECEIVER AND TRANSMITTER BY USING VHDL ”, is a bonafide
work done by RASAZNA.B (08A51A0417), SIVAJI.I (08A51A0444), PRIYANKA.D
(08A51A0426) and SRINU.B (08A51A0418) submitted in partial fulfillment of the
requirements for the award of the degree of BACHELOR OF TECHNOLOGY IN
ELECTRONICS AND COMMUNICATION ENGINEERING during the year 2011-2012 .
HEAD OF THE DEPARTMENT: GUIDE:
Sri.A.S.SRINIVAS RAO M.Tech,(Ph.D) K.CHIDAMBARA RAO, M.Tech
Head of the Department Assoc. Professor
Department of E.C.E
CONTENTS
CONTENT NAME PAGE NO
ACKNOWLEDGEMENT (i)
ABSTRACT (ii)
LIST OF FIGURES (iii)
LIST OF TABLES (iv)
CHAPTER 1:
INTRODUCTION TO UART 1-10
1.1 Introduction 1
1.2 Need of UART 2
1.3 Serial transmission 2
1.4 Baud, Baud rate 3
1.5 Importance of FIFO in UART 4
1.6 UART protocol flow control 5
1.7 Principle of UART 8
1.8 Basic error conditions 9
CHAPTER 2:
ARCHITECTURE OF UART 11-15
2.1 Block diagram of UART 11
2.2 MODEM operation 12
2.3 Connection diagrams 15
CHAPTER 3:
UART REGISTERS 16-20
3.1 Register block diagram 16
3.2 Register description 17
CHAPTER 4:
INTRODUCTION TO VHDL 21-24
4.1 Use of VHDL tools in VLSI design 21
4.2 Scope of VHDL 21
4.3 WHY VHDL? 21
4.4 Design synthesis 23
4.5 Synthesis, optimization, and Fit the design 24
4.6 Simulate the post-layout design model 24
CHAPTER 5:
XILINX 25-29
5.1 Introduction 25
5.2 Overview of ISE and synthesis tool 25
5.3 The RTL viewer 27
CHAPTER 6:
UART SOURCE CODE 30-37
RESULTS 38
CONCLUSION 39
FUTURE SCOPE 40
REFERENCE 41-43
ACKNOWLEDGEMENT
This report would be incomplete without the mention of those who have directly or
indirectly helped us during the tenure of this project.
We would like to thank Prof.V.V.NAGESWARA RAO,DIRECTOR and
Dr.T.K. RAMA KRISHNA RAO, Principal in Aditya institute of technology and management
for having permitted us to take up this project.
We would also like to express our deepest sense of gratitude and thanks towards
Sri SRINIVASA RAO, Head of the Department, Electronics and communication Engineering,
in Adtiya institute of technology and management for his invaluable help during this project.
We would like to thank our internal guide Sri K.CHIDAMBARA RAO , Associate
Professor, Electronics and communication Engineering, Aditya institute of technology and
management for constantly monitoring our progress and suggesting improvements at various
stages in the project.
We would like to thank all the other staff members of Electronics and communication
Engineering Department, Aditya institute of technology and management , for cooperating with
us all through the period of project.
Lastly, we would like to thank everyone who has been involved in the progress of the
project, whose contributions, have added a lot of value.
RASAZNA.B (08A51A0417)
SIVAJI.I (08A51A0444)
PRIYANKA.D (08A51A0426)
SRINU.B (08A51A0418)
(i)
ABSTRACT
The Universal Asynchronous Receiver (UART) is the most widely used serial data
Communication circuit ever. Specifically, UART provides the computer with the RS-232C Data
Terminal Equipment (DTE) interface so that it can "talk" to and exchange data with modems.
Other serial devices Serial transmission is commonly used with modems and for non-networked
communication between computers, terminals and other devices.
A parallel link transmits several streams of data 8 (perhaps representing particular bits of
a stream of bytes) along multiple channels (wires printed circuit tracks, optical fibers, etc.); a
serial link transmits a single stream of data In telecommunications and computer Science, serial
communications is the process sending data one bit at one time sequentially, over a
communications channel computer bus.
The start signal serves to prepare the receiving mechanism for the reception and
registration of a symbol and the stop signal serves to bring the receiving mechanism to rest in
preparation for the reception of the next symbol. A common kind of start-stop transmission is
ASCII over RS-232.
The number of data, formatting bits and the transmission speed, must be pre-agreed by
the communicating parties. After the stop bit the line may remain idle indefinitely or another
character may immediately be started. It will be designed using Xilinx software tool with VHDL
code.
(ii)
LIST OF FIGURES
FIGURE NO FIGURE NAME PAGE NO
1.1 UART’S FPGA diagram 1
1.2 FIFO structure 4
1.3 Protocol flow control diagram 7
1.4 Principle of UART 8
2.1 Block diagram of UART 11
2.2 Receiver sub system 12
2.3 DTE to DCE connection 14
2.4 DTE to DTE connection 14
2.5 Connection diagrams 15
3.1 Block diagramof UART register 16
5.1 Project navigator 26
5.2 RTL schematic 27
5.3 Process source 29
6.1 Result 38
(iii)
LIST OF TABLES
TABLE NO TABLE NAME PAGE NO
2.1 Modem input/output signals in DTE and DCE modes 13
2.2 UART reset configuration 15
(iv)
CHAPTER-1
INTRODUCTION TO UART
1. INTRODUCTION TO UNIVERSAL ASYNCHRONOUS
RECEIVER AND TRANSMITTER
1.1 Introduction:-
A universal asynchronous receiver/transmitter, abbreviated UART is a type of
"asynchronous receiver/transmitter", a piece of computer hardware that translates data between
parallel and serial forms. UARTs are commonly used in conjunction with communication
standards such as EIA RS-232, RS-422 or RS-485. The universal designation indicates that the
data format and transmission speeds are configurable and that the actual electric signaling
levels and methods (such as differential signaling etc.) typically are handled by a special driver
circuit external to the UART.
A UART is usually an individual (or part of an) integrated circuit used for serial
communications over a computer or peripheral device serial port. UARTs are now commonly
included in microcontrollers. A dual UART, or DUART, combines two UARTs into a single
chip. Many modern ICs now come with a UART that can also communicate synchronously;
these devices are called USARTs (universal synchronous/asynchronous receiver/transmitter).
Figure 1.1: UART’s FPGA diagram.
[1]
1.2 Need Of UART:-
UART is one of the most commonly used serial interface peripherals. It is also known as
the serial communications interface, or SCI. The most common use of the UART is to
communicate to a PC serial port using the RS-232 protocol.RS-232 is a standard electrical
interface for serial communications defined by the Electronic Industries Association (EIA).Serial
communications includes most network devices, keyboards, mice, modems, and terminals. When
referring to serial devices or ports, they are either labeled as data communications equipment
(DCE) or data terminal equipment (DTE).
The UART can transmit and receive data serially. It is often necessary to regulate the
flow of data when transferring data between two serial interfaces. The first method is often called
“software" flow control and uses special characters to start (XON or DC1) or stop (XOFF or
DC3) the flow of data. The second method is called "hardware" flow control and uses theRS-232
CTS and RTS signals instead of special characters. Because hardware flow control uses a
separate set of signals, it is much faster than software flow control which needs to send or
receive multiple bits of information to do the same thing.
Asynchronous receiver/ transmitter, a piece of computer hardware that translates data
between parallel and serial forms. UARTs are commonly used in conjunction with
communication standards such as EIA RS-232, RS-422 or RS-485. The universal designation
indicates that the data format and transmission speeds are configurable and that the actual
electric signaling levels and methods (such as differential signaling etc.) typically are handled by
a special driver circuit external to the UART.
1.3 Serial Transmissions:-
In telecommunication and computer science, serial communication is the process of
sending data one bit at a time, sequentially, over a communication channel or computer bus. This
is in contrast to parallel communication, where several bits are sent as a whole, on a link with
several parallel channels. Serial communication is used for all long-haul communication and
most computer networks, where the cost of cable and synchronization difficulties makes parallel
communication impractical. Serial computer buses are becoming more common even at shorte
distances, as improved signal integrity and transmission speeds in newer serial technologies have
begun to outweigh the parallel bus's advantage of simplicity (no need for serialize and de
serialize, or Serves) and to outstrip its disadvantages (clock skew, interconnect density). The
migration from PCI to PCI Express is an example.
Serial transmission technology is increasingly used for the transmission of digital data. A
large number of up-to-date communications networks apply serial transmission. The numerous
applications include computer networks for office communications, field bus systems in process,
building and manufacturing automation, Internet and, finally, ISDN.Serial data transmission
implies that one bit is sent after another (bit-serial)on a single transmission line. Since the
microprocessors in the devices process data in bit-parallel mode, the transmitted performs
parallel-to-serial conversion, while the receiver performs serial-to-parallel conversion (Fig
1).This is done by special transmitter and receiver modules which are commercially available for
different types of networks. Extremely high data rates are possible today so that the increased
time consumption required by this technology is accepted in most cases. The reductions in costs
and installation effort as well as user-friendliness, on the other hand, are points.
1.4 Baud, Baud rate:-
The baud rate of a data communications system is the number of symbols per second
transferred. A symbol may have more than two states, so it may represent more than one binary
bit (a binary bit always represents exactly two states). Therefore the baud rate may not equal the
bit rate, especially in the case of recent modems, which can have (for example) up to nine bits
per symbol.
The baud unit is named after Jean Maurice Emile Bardot, who was an officer in the
French Telegraph Service. He is credited with devising the first uniform-length 5-bit code for
characters of the alphabet in the late 19th century. What baud really refers to is modulation rate
or the number of times per second that a line changes state? This is not always the same as bits
per second (BPS). If you connect two serial devices together using direct cables then baud and
BPS are in fact the same. Thus, if you are running at 19200 BPS, then the line is also changing
states 19200 times per second. But when considering modems, this is not the case.
[3]
Because modems transfer signals over a telephone line, the baud rate is actually limited
to a maximum of 2400 baud. This is a physical restriction of the lines provided by the phone
company. The increased data throughput achieved with 9600 or higher baud modems is
accomplished by using sophisticated phase modulation, and data compression techniques.
1.5 Importance of FIFO in UART:-
A UART (Universal Asynchronous Receiver/Transmitter) is the device which ultimately
controls the receive and transmit (read and write) operations performed by a given serial port. In
particular, UARTs have dedicated memory in the form of a FIFO structure (first in first out; a
queue structure) for each the receive and transmit operations.The purpose of the FIFO structures
is to hold data either received from the serial port or to be written to the serial port. Moreover
most UARTs allow the size of the FIFO used to be specified in software (in the Device Manager
for Windows OS's; directions for changing these FIFO sizes are contained in the KB linked
below entitled: Why Do I Get Buffer Overflows with My Serial Port When Using VISA with
Flow Control?). That is, there is a maximum size which is limited by the total amount of memory
on the UART, but you can specifically define the size to be used.
Figure 1.2: FIFO structure.
[4]
1.5.1 How do the FIFO effect performance:-
The size of the FIFO buffers determines when the UART interrupts the CPU in order to
transfer data between the FIFO and CPU memory (RAM, where applications running on the
CPU have access to the data). Therefore, the size of the FIFOs can affect latencies in writing to
and read from the serial port, usually on the order of milliseconds, as well as overall performance
of a given application. For example, if you set the receive buffer to 1, the UART will interrupt
the processor to transfer a single byte to CPU memory whenever a byte is received. While this
will make a given byte available in RAM as soon as possible after arriving at the port, if data is
continuously being received at the port, this will cause many interrupts. As a result, more CPU
processing is dedicated to those interrupts which can decrease overall performance if other
programs are running. Thus, if latencies on the order of a few milliseconds are tolerable for serial
operations, it is often beneficial for overall performance to use a larger receive FIFO size.
1.6 UART protocol flow control:-
Flow control refers to the control of data flow between modems, or between the modem
and computer. It handles the data in the FIFO buffer and starts and stops data flow between the
modems. Often, one modem may be sending data much faster than the other is able to receive.
Flow control allows the slower device to tell the faster device to pause and resume data
transmission. There are two ways to handle flow control: hardware (RTS/CTS or DTR/DSR) and
software (X ON /X OFF or DC1/DC3):
● Hardware flow control is performed using the RTS and CTS signals. These signals
maybe software controlled.
● Software flow control means sending an XOFF character to stop transmission, and
another character to start transmission. The flow of data bytes in the cable between 2 serial ports
is bi-directional so there are 2different flows (and wires) to consider:
● Byte flow from the computer to the modem.
● Byte flow from the modem to the computer.
[5]
HARDWARE FLOW CONTROL:-
Uses two dedicated ‘modem control’ wires to send the ‘stop’ and ‘start’ signals.
Hardware flow control at the serial port works like this: The two pins, RTS (Request to send) and
CTS (Clear to send) are used. When the computer is ready to receive data it asserts RTS by
putting a positive voltage on the RTS pin(meaning-Request To Send to me). When the computer
is not able to receive any more bytes, it negates RTS by asserting negative voltage on the pin
saying: ‘stop sending to me’. The RTS pin is connected by the serial cable to another pin on the
modem, printer, terminal, etc. This other pin's only function is to receive this signal. For a
printer, another PC, or anon-modem device, this ‘other’ pin is usually a CTS pin so a ‘crossover’
or ‘null modem’ cable is required. This cable connects the CTS pin at one end with the RTS pin
at the other end (two wires since each end of the cable has a CTS pin).For the opposite direction
of flow a similar scheme is used. For a non-modem, the RTS pin sends the signal. Some non-
modems may use other pins for flow control such as the DTR pin instead of RTS.
SOFTWARE FLOW CONTROL:-
Uses the main receive and transmit data wires to send the start and stop signals. It inserts
the ASCII control characters DC1 (start) and DC3 (stop) into the stream of data. Software flow
control is slower than hardware flow control and it does not allow the sending of binary data
unless special precautions are taken. For example, you need to be able to distinguish between an
occurrence of a control code like DC3 when it means a flow control stop and a DC3 that is part
of the binary data payload.
[6]
Figure 1.3: Protocol flow control diagram.
Character framing:
Each character is sent as a logic low start bit, a configurable number of data bits
(usually 7 or 8, sometimes 5), an optional parity bit, and one or more logic high stop bits.
The start bit signals the receiver that a new character is coming. The next five to eight bits,
depending on the code set employed, represent the character. Following the data bits may
be a parity bit. The next one or two bits are always in the mark (logic high, i.e., '1')
condition and called the stop bit(s). They signal the receiver that the character is
completed. Since the start bit is logic low (0) and the stop bit is logic high (1) then there is
always a clear demarcation between the previous character and the next one.
[7]
1.7 Principle of UART:-
Figure 1.4: Principle of UART.
Host Actions:
1. Set master enable; set control flags; load 8-bit data word for transmit sequence (LSB is
parity bit).
2. Load 'transmit data' register; buffer with start, stop and parity bits; set 'ready to send' flag.
3. Reset counter; shift each of 10-bits onto serial bus; increment transfer counter.
4. Check and clear status flags; setup for next transmit
Remote Actions:
1. Clear flags on Reset; drop 'clear to send' flag; poll for 'ready to send'.
2. Read 'ready to send' and acknowledge with 'clear to send' flag; set up the 'receive data
counter'.
3. Shift in each of 10-bits from serial bus into buffer; check parity; strip off start and stop bits.
4. Check and clear status flags; transfer data to buffer.
[8]
1.8 Basic Error Conditions:-
Over run error:-
An "over run error" occurs when the receiver cannot process the character that just came
in before the next one arrives. Various devices have different amounts of buffer space to hold
received characters. The CPU must service the UART in order to remove characters from the
input buffer. If the CPU does not service the UART quickly enough and the buffer becomes
full, an Overrun Error will occur, and incoming characters will be lost.
Under run error:-
An "under run error" occurs when the UART transmitter has completed sending a
character and the transmit buffer is empty. In asynchronous modes this is treated as an indication
that no data remains to be transmitted, rather than an error, since additional stop bits can be
appended. This error indication is commonly found in USARTs, since an underrun is more
serious in synchronous systems.
Framing error:-
A "framing error" occurs when the designated "start" and "stop" bits are not valid. As the
"start" bit is used to identify the beginning of an incoming character, it acts as a reference for the
remaining bits. If the data line is not in the expected idle state when the "stop" bit is expected, the
Framing Error will occur.
Parity error:-
A "parity error" occurs when the number of "active" bits does not agree with the
specified parity configuration of the USART, producing a Parity Error. Because the "parity" bit
is optional, this error will not occur if parity has been disabled. Parity error is set when the parity
of an incoming data character does not match the expected value.
[9]
Break condition:-
A "break condition" occurs when the receiver input is at the "space" level for longer
than some duration of time, typically, for more than a character time. This is not necessarily an
error, but appears to the receiver as a character of all zero bits with a framing error.
Some equipment will deliberately transmit the "break" level for longer than a character
as an out-of-band signal. When signaling rates are mismatched, no meaningful characters can be
sent, but a long "break" signal can be a useful way to get the attention of a mismatched receiver
to do something (such as resetting itself). Unix-like systems can use the long "break" level as a
request to change the signaling rate, to support dial-in access at multiple signaling rates.
Applications:-
Transmitting and receiving UARTs must be set for the same bit speed, character length,
parity, and stop bits for proper operation. The receiving UART may detect some mismatched
settings and set a "framing error" flag bit for the host system; in exceptional cases the receiving
UART will produce an erratic stream of mutilated characters and transfer them to the host
system.
Typical serial ports used with personal computers connected to modems use eight data
bits, no parity, and one stop bit; for this configuration the number of ASCII characters per second
equals the bit rate divided by 10.
Some very low-cost home computers or embedded systems dispensed with a UART
and used the CPU to sample the state of an input port or directly manipulate an output port for
data transmission. While very CPU-intensive, since the CPU timing was critical, these schemes
avoided the purchase of a costly UART chip. The technique was known as a bit -banging serial
port.
[10]
CHAPTER-2
ARCHITECTURE OF UART
2. ARCHITECTURE OF UNIVERSAL ASYNCHRONOUS
RICEIVER AND TRANSMITTER
2.1 Block diagram of UART:-
Figure 2.1: Block diagram of UART.
See text for the UART main module that instantiates the entities discussed above. Note
text uses a FIFO buffer so the diagram above is different. The text also includes a loop-back
circuit that instantiates the UART and connects the outputs of the receiver with the inputs of the
transmitter on the FPGA.It also adds ’1’ to the incoming data before looping it back to the
computer. Windows HyperTerminal is discussed as a mechanism to communicate directly to the
serial ports on your computer.
[11]
Receiving system:-
Figure 2.2: Receiving sub system.
The oversampling scheme replaces the function of the clock. Instead of using the rising
edge to sample, the sampling ticks are used to estimate the center position of each bit. Note that
the system clock must be much faster than the baud rate for oversampling to be possible. The
receiver block diagram consists of three components.
The baud rate generator generates a sampling signal whose frequency is exactly 16times
the UART’s designated baud rate. To avoid creating a new clock domain, the output of the baud
rate generator will serve to enable ticks within the UART rather than serve as the clock signal. The
whole system will use one elk as we will see. For a 19,200 baud rate, the sampling rate has to be
307,200 (19,200*16) ticks per second. With a system clock at 50 MHz, the baud rate generator
needs a mod-163 counter (50MHz/307,200).Therefore, the tick output will assert for one clock
cycle every 163 clock cycles of the system clk.
2.2 UART modem operation:-
The UART can support both data terminal equipment (DTE) and data communication
equipment (DCE) modes of operation. Table 1 gives a description of the signals in each mode.
[12]
Table 2.1: Modem input/output signals in DTE and DCE modes.
Two dedicated "modem control" wires are used in hardware flow control to send the
"stop” and "start" signals. When the computer is ready to receive data it asserts RTS by putting
appositive voltage on the RTS pin. When the computer is not able to receive any more bytes, it
negates RTS by asserting a negative voltage on the pin. The RTS pin is connected by the serial
cable to another pin on the modem. This other pin's only function is to receive this signal. This
"other" pin will be the modem's RTS pin. For a modem, a straight-thru cable is used. For the
opposite direction of flow a similar scheme is used. The CTS pin is used to send the flow control
signal to the CTS pin on the PC.Thus modems and non-modems have the roles of their RTS and
CTS pins interchanged.RS-232 hardware handshaking has been specified in terms of
communication between Most RS-232 connections use 9-pin DSUB connectors. A DTE uses a
male connector and a DCE uses female connector.
[13]
Figure 2.3: DTE to DCE connection.
Fig 5 :DTE to DTE connection
Figure 2.4: DTE to DTE connection.
[14]
2.3 Connection diagram:-
Figure 2.5: Connection diagrams.
Table 2.2: UART Reset Configuration.
[15]
CHAPTER-3
UART REGISTERS
3. UART REGISTERS
3.1 Register block diagram:-
Figure 3.1: Block diagram of UART Register.
[16]
3.2 Register Description :-
The registers control UART operations including transmission and reception of data.
Each register bit in Table II has its name and reset state shown.
3.2.1 Line Control Register :-
The system programmer specifies the format of the asynchronous data communications
exchange and set the Divisor latch Access bit via the Line Control Register (LCR).The
programmer can also read the contents of the Line Control Register. The read capability
simplifies system programming and eliminates the need for separate storage in system memory
3.2.2 Typical Clock Circuits:-
Fig 7: clock circuits
[17]
3.2.3 Programmable baud generator:-
The UART contains a programmable Baud Generator that I capable of taking any clock
input from DC to 24 MHz and dividing it by any divisor from 2 to 216b1. Two 8-bit latches
store the divisor in a 16-bit binary format. These Divisor Latches must be loaded during
initialization to ensure proper operation of the Baud Generator. Upon loading either of the
Divisor Latches, a 16-bit Baud counter is immediately loaded.
3.2.4 Line status register:-
This register provides status information to the CPU concerning the data transfer. Table II
shows the contents of the Line Status Register. The system programmer controls the format of
the asynchronous data communication exchange by using the line control register (LCR). In
addition, the programmer can retrieve, inspect, and modify the content of the LCR. This
eliminates the need for separate storage of the line characteristics in system memory.
3.2.5 FIFO control register:-
This is a write only register at the same location as the IIR(the IIR is a read only register).
This register is used to enable the FIFOs, clear the FIFOs, set the RCVR FIFO trigger level, and
select the type of DMA signaling. The FIFO control register (FCR) is a write-only register at the
same address as the interrupt identification register (IIR), which is a read-only register. Use the
FCR to enable and clear the FIFOs and to select the receiver FIFO trigger level. The FIFO EN
bit must be set to 1 before other FCR bits are written to or the FCR bits are not programmed.
3.2.6 Interrupt identification register:-
In order to provide minimum software overhead during data character transfers, the
UART prioritizes interrupts into four levels and records these in the interrupt Identification
Register. The four levels of interrupt conditions in order of priority are Receiver Line Status;
Received Data Ready; Transmitter Holding Register Empty; and MODEM Status. When the
CPU accesses the IIR, the UART freezes all interrupt and indicates the highest priority pending
interrupt to the CPU. While this CPU access is occurring, the UART records new interrupts, but
does not change its current indication until the access is complete
[18]
3.2.7 Interrupt enables register:-
This register enables the five types of UART interrupts. Each interrupt can individually
activate the interrupt (INTR)output signal. It is possible to totally disable the interrupt system by
resetting bits 0 through 3 of the Interrupt Enable Register (IER). Similarly, setting bits of the IER
register to a logic 1, enables the selected interrupt(s). Disabling an interrupt prevents it from
being indicated as active in the IIR and from activating the INTR output signal. All other system
functions operate in their normal manner, including the setting of the Line Status and MODEM
Status Registers.
3.2.8 Modem control register:-
This register controls the interface with the MODEM or dataset (or a peripheral device
emulating a MODEM). The modem control register (MCR) provides the ability to enable/disable
the auto flow functions, and enable/disable the loopback function for diagnostic purposes.
3.2.9 Modem status register:-
This register provides the current state of the control lines from the MODEM (or
peripheral device) to the CPU. In addition to this current-state information, four bits of the
MODE Status Register provide change information. These bits are set to a logic 1 whenever a
control input from the MODEM changes state. They are reset to logic 0 whenever the CPU reads
the MODEM Status Register.
3.2.10 sScratch pad registers:-
This 8-bit Read/Write Register does not control the UART in anyway. It is intended as a
scratchpad register to be used by the programmer to hold data temporarily.
[19]
3.2.11 FIFO interrupts mode operation:-
When the RCVR FIFO and receiver interrupts are enabled (FCR0e1, IER0e1) RCVR
interrupts will occur as follows:
A.The receive data available interrupt will be issued to teacup when the FIFO has reached its
programmed trigger level; it will be cleared as soon as the FIFO drops below its programmed
trigger level.
B. The IIR receive data available indication also occurs when the FIFO trigger level is reached,
and like the interrupt it is cleared when the FIFO drops below the trigger level.
C. The receiver line status interrupt (IIRe06), as before, has higher priority than the received data
available (IIRe04) interrupt.
D. The data ready bit (LSR0) is set as soon as a character is transferred from the shift register to
the RCVR FIFO. It is reset when the FIFO is empty.
3.2.12 FIFO polled mode operation:-
With FCR0e1 resetting IER0, IER1, IER2, IER3 or all to zero puts the UART in the
FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately either
one or both can be in the polled mode of operation. In this mode the user's program will check
RCVR and XMITTER status via the LSR. As stated previously:
LSR0 will be set as long as there is one byte in the RCVRFIFO.
LSR1 to LSR4 will specify which error(s) has occurred. Character error status is handled the
same way as when in the interrupt mode, the IIR is not affected sinceIER2=0.
LSR5 will indicate when the XMIT FIFO is empty.
LSR6 will indicate that both the XMIT FIFO and shift register are empty.
LSR7 will indicate whether there are any errors in the RCVR FIFO.There is no trigger level
reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT
FIFOs are still fully capable of holding characters.
[20]
CHAPTER-4
INTRODUCTION TO VHDL
4. INTRODUCTION TO VHDL
4.1. Use of VHDL tools in VLSI design:-
IC designers are always looking for a ways to increase their productivity without
degrading the quality of their designs. Therefore, it is no wonder that they have embraced logic
synthesis tools. In the last few years, these tools have grown to be capable for producing designs
as good as a human designer. Now logic synthesis is helping to bring about a switch to design
using a hardware description language (HDL) to describe the structure and behavior of circuits,
as evidenced by the recent availability of logic synthesis tools using the very high speed
integrated circuit hardware description language (VHDL).
Now logic synthesis tools can automatically produce a gate level net list, allowing
designers to formulate their design in a high level description such as VHDL.Logic synthesis
provided two fundamental capabilities. Automatic translation of high-level descriptions into
logic designs, and optimization to decrease the circuit’s area and increase its speed. Many
designs created manually, in terms of chip area occupied and IC signal speed, but are much faster
to do.
4.2. Scope of VHDL:-
VHDL satisfies all the requirements for the hierarchical description of electronic circuits
from system level down to switch level. It can support all levels of timing specification and
constraints and is capable of detecting and signaling timing violations. The language models the
reality of concurrency present in digital system and supports the recursively of finite state
machines. The concept of packages and configurations allow the creation of design libraries for
the reuse of previously designed parts.
[21]
4.3. WHY VHDL?
A design engineer in electronic industry used hardware description language to keep pace
with the productivity of the competitors. With VHDL we can quickly describe the capability
described as follows:
4.3.1. Power and flexibility:-
VHDL has powerful language constructs with which to write succinct code descriptions
of complex control logic. It also has multiple levels of design description for controlling design
implementation. It supports design libraries and creation of reusable language for design and
simulation.
4.3.2. Devices- independent design:-
VHDL permits to create a design with out to first choose a device implementation. With
one design description, we can target many device architectures. Without being familiar with it,
we can optimize our design for resource utilization performance. It permits multiple style of
design description.
4.3.3. Portability:-
VHDL portability permits to simulate the same design description that we have
synthesized. Simulating a large description before synthesizing can save considerable time
4.3.4. Benchmarking capability:-
Device independent design and portability allows benchmarking a design using different
device architectures and different synthesis tools. We can evaluate the results and finally choose
the device-a CLD or an FPGA that best fits our design requirements.
4.3.5. ASIC Migration:-
The efficiency that VHDL generated, allows our product to hit the market quickly if it
has been synthesized on a CPLD or FPGA. When production volume reaches appropriate levels,
[22]
VHDL facilitates the development of application specific integrated circuit (ASIC). Sometimes,
the exact code used with the PLD can be used with the ASIC and because VHDL is a well –
defined language, we can be assured that out ASIC vendor will deliver a device with expected
functionality.
4.3.6. Quick Time-to-Market and low cost:-
VHDL and programmable logic pair will together facilitate a speedy design process.
VHDL permits to be described quickly. Programmable logic eliminates NRE expenses and
facilitates quick design iterations. Synthesis makes it all possible. VHDL and programmable
logic as powerful vehicle to bring the products in market record time.
4.4 Design synthesis:-
The design process can be explained in six steps:
1. Define the design requirements.
2. Describe the design in VHDL (formulate and code the design).
3. Simulate the source code.
4. Synthesis, optimize and fit the design on to a suitable device.
5. Simulate the post-layout design model.
6. Progress the device.
4.4.1 Define the design requirements:-
Before launching into writing code for our design, we must have a clear idea of design
objective and requirements. That is, the function of the design required setup and clock-to-output
times, maximum frequency of operation and critical paths.
4.4.2 Describe the design in VHDL:-
Formulate the design: having and idea of design requirements, we have to write an
efficient code that is realized, through synthesis, to the logic implementation we intended. Code
the design: after deciding upon a design methodology, we should code the design referring to the
block, dataflow, and state diagrams such that the code is syntactically and semantically correct.
[23]
4.4.3 Stimulate the source code:-
With source code simulation, flaws can be detected early in the design cycle, allowing us
to make corrections with the least possible impact o the schedule. This is more efficient for
larger designs, for which synthesis and lace and route can take a couple of hour
4.5 Synthesis, Optimize, and Fit the design:-
4.5.1 Synthesis:-
It is a process by which net lists or equations are created from design descriptions, which
many be abstracted. VHDL synthesis software tools convert VHDL descriptions to technology
specific net lists or set of equations.
4.5.2 Optimization:-
The optimization process depends on three things: the form of the Boolean expression, the
type of resources available and automatic or used applied synthesis directives (sometimes called
constraints). Optimization for CPLDs involves reducing the logic to minimal sum-of- products,
which is then further optimized for a minimal literal count. This reduces the product-term
utilization and number of logic block inputs required for any given expression.
4.5.3 Fitting:-
Fitting is process of taking the logic produced by the synthesis and optimization process,
and placing it into a logic device, transforming the logic (if necessary) to obtain the best fit. It is
a term typically used to describe the process of allocating resources for CPLD-type architectures.
4.6 Simulate the Post-layout design model:-
A post layout simulation will enable us to verify, not only the functionality of our design,
but also timing, such as setup, clock-to-output, and register-to-register times. If we are unable to
meet our design objectives, then we need to either re synthesize, and/or fit our design to a new
logic device.
[24]
CHAPTER-5
XILINX
5. XILINX
5.1. Introduction:-
Xilinx leads one of the fastest growing segments of the semiconductor industry -
programmable logic devices.
Xilinx FPGAs:-
The Xilinx FPGA Spartan3e series has redefined programmable logic by expanding the
traditional capabilities of field programmable gate arrays (FPGAs) with new levels of integration
and features that address high performance system design issues. In a single, off-the-shelf
programmable Xilinx device, systems architects can take advantage of microprocessors, the
highest density of on-chip memory, multi-gigabit serial transceivers, digital clock managers, on-
chip termination and more. The result is that Xilinx FPGAs helps designers to simplify board
layout, reduce bill of materials, and get products to market faster than ever before.
5.2. Overview of ISE and Synthesis Tools:-
Overview of ISE:-
ISE controls all aspects of the design flow. Through the Project Navigator interface, you
can access all of the various design entry and design implementation tools. You can also access
the files and documents associated with your project. Project Navigator maintains a flat directory
structure; therefore, you can maintain revision control through the use of snapshots.
Project Navigator Interface:-
The Project Navigator Interface is divided into four main sub windows, as seen in Figure
5.1. On the top left is the Sources in Project window which hierarchically displays the elements
included in the project. Beneath the Sources in Project window is the Processes for Current
Source window which displays available processes. The third window at the bottom of the
Project Navigator is the Console window which displays status messages, errors, and warnings,
and which is updated during all project actions. The fourth window to the right is known a mult –
[25]
document Interface (MDI) window for viewing ASCII text files and HDL Bencher™
Waveforms. Each window may be resized, undocked from Project Navigator or moved to a new
location within the main Project Navigator window. Selecting View Restore. Default Layout can
always restore the default layout. These windows are discussed in more detail in the following
sections.
Figure 5.1: Project Navigator.
Synthesizing the Design:-
So far you have used XST for verifying syntax. Next, you will synthesize the design.
The synthesis tool uses the design’s HDL code and generates a supported net list type (EDIF or
[26]
NGC for the Xilinx® implementation tools). The synthesis tools perform three general steps
(although all synthesis tools further breakdown these general steps) to create the nettles
5.3 The RTL Viewer:-
XST can generate a schematic representation of the HDL code that you have entered. A
schematic view of the code is helpful for analyzing your design to see a graphical connection
between the various components that XST has inferred. To view a schematic representation of
your RTL code:
In Project Navigator, click + next to Synthesize to expand the process hierarchy.
Double-click View RTL Schematic.
Figure 5.2: RTL schematic.
[27]
Entering Synthesis Options through ISE:-
Synthesis options enable you to modify the behavior of the synthesis tool to optimize
according to the needs of the design. One option is to control synthesis by optimizing based on
area or speed. Other options include controlling the maximum fan out of a signal from a flip-flop
or setting the desired frequency of the design.
For this tutorial, set the global synthesis options:
Select stopwatch.vhd (or stopwatches).
Right-click the Synthesis process.
From the menu, select Properties. Click the Synthesis Options tab, and set the Default Frequency
to 50MHz.
Click the Net list Options tab, and ensure that the Do Not Write NCF box is unchecked
Click the Constraint File Options tab, and select the stopwatch.ctr file created in Leonardo
Spectrum, in the “Modifying Constraints” section above.
Click OK to accept these values.
Select stopwatch.vhd (or stopwatch’s) and double-click the Synthesize process in the Processes
for Source window.
The RTL/Technology Viewer:-
Leonardo Spectrum can generate a schematic representation of the HDL code that you
have entered. A schematic view of the code is helpful for analyzing your design to see a
graphical connection between the various components that Leonardo Spectrum has inferred.
[28]
Figure 5.3: Process source.
To launch the design in Leonardo Spectrum’s RTL viewer, double-click the View RTL
Schematic process. The following figure displays the design in an RTL view. Leonardo
Spectrum Synthesis Processes
Overview of Behavioral Simulation Flow:-
Behavioral simulation is done before the design is synthesized to verify that the logic
you have created is correct. This allows a designer to find and fix any bugs in the design before
spending time with Synthesis or Implementation. Xilinx® ISE provides an integrated flow with
the ModelTech Models simulator that allows simulations to be run from the Xilinx Project
Navigator graphical user interface (GUI). The examples in this tutorial show how to use this
integrated flow. For additional information about simulation and for a list of the other supported
simulators, refer to Chapter 6 of Synthesis and Verification Guide.
[29]
CHAPTER-6
UART SOURCE CODE
UART SOURCE CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity uart1 is
port ( reset :in std_logic;
clk :in std_logic;
ld_tx_data :in std_logic;
tx_data :in std_logic_vector (7 downto 0);
tx_enable :in std_logic;
tx_out :out std_logic;
tx_empty :out std_logic;
uld_rx_data :in std_logic;
rx_data :out std_logic_vector (7 downto 0);
rx_enable :in std_logic;
[30]
rx_in:in std_logic;
rx_empty :out std_logic);
end uart1;
architecture Behavioral of uart1 is
Internal Variables
signal tx_reg :std_logic_vector (7 downto 0);
signal tx_over_run:std_logic;
signal tx_cnt :std_logic_vector (3 downto 0);
signal rx_reg :std_logic_vector (7 downto 0);
signal rx_sample_cnt :std_logic_vector (3 down to signal rx_cnt :std_logic_vector (3 downto 0);
signal rx_frame_err :std_logic;
signal rx_over_run :std_logic;
signal rx_d1:std_logic;
signal rx_d2 :std_logic;
signal rx_busy :std_logic;
signal rx_is_empty:std_logic;
signal tx_is_empty:std_logic;
[31]
begin
proocess (clk, reset) begin
if (reset = '1') then
tx_reg <= (others=>'0');
tx_is_empty <= '1';
tx_over_run <= '0';
tx_out <= '1';
tx_cnt <= (others=>'0');
elsif (rising_edge(clk)) then
if (ld_tx_data = '1') then
if (tx_is_empty = '0') then
tx_over_run <= '0';
else
tx_reg <= tx_data;
tx_is_empty <= '0';
end if;
end if;
if (tx_enable = '1' and tx_is_empty = '0') then
[32]
tx_cnt <= tx_cnt + 1;
if (tx_cnt = 0) then
tx_out <= '0';
end if;
if (tx_cnt > 0 and tx_cnt < 9) then
tx_out <= tx_reg(conv_integer(tx_cnt) -1);
end if;
if (tx_cnt = 9) then
tx_out <= '1';
tx_cnt <= X"0";
tx_is_empty <= '1';
end if;
end if;
if (tx_enable = '0') then
tx_cnt <= X"0";
end if;
end if;
end process;
[33]
tx_empty <= tx_is_empty;
end Behavioral;
process (clk, reset)
begin
if (reset = '1') then
rx_reg <= (others=>'0');
rx_data <= (others=>'0');
rx_sample_cnt <= (others=>'0');
rx_cnt <= (others=>'0');
rx_frame_err <= '0';
rx_over_run <= '0';
rx_is_empty <= '1';
rx_d1<= '1';
rx_d2 <= '1';
rx_busy <= '0';
elsif (rising_edge(clk)) then
-- Synchronize the asynch signal
rx_d1<= rx_in;
[34]
rx_d2 <= rx_d1;
-- Uload the rx data
if (uld_rx_data = '1') then
rx_data <= rx_reg;
rx_is_empty <= '1';
end if;
-- Receive data only when rx is enabled
if (rx_enable = '1') then
-- Check if just received start of frame
if (rx_busy = '0' and rx_d2 = '0') then
rx_busy <= '1';
rx_sample_cnt <= X"1";
rx_cnt <= X"0";
end if;
-- Start of frame detected, Proceed with rest of data
if (rx_busy = '1') then
rx_sample_cnt <= rx_sample_cnt + 1;
-- Logic to sample at middle of data
[35]
if (rx_sample_cnt = 7) then
if ((rx_d2 = '1') and (rx_cnt = 0)) then
rx_busy <= '0';
else
rx_cnt <= rx_cnt + 1;
-- Start storing the rx data
if (rx_cnt > 0 and rx_cnt < 9) then
rx_reg(conv_integer(rx_cnt) - 1) <= rx_d2;
end if;
if (rx_cnt = 9) then
rx_busy <= '0';
-- Check if End of frame received correctly
if (rx_d2 = '0') then
rx_frame_err <= '1';
else
rx_is_empty <= '0';
rx_frame_err <= '0';
-- Check if last rx data was not unloaded,
[36]
if (rx_is_empty = '1') then
rx_over_run <= '0';
else
rx_over_run <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
if (rx_enable = '0') then
rx_busy <= '0';
end if;
end if;
end process;
rx_empty <= rx_is_empty;
[37]
RESULT
RESULTS
Figure 6.1: Result window.
From the Figure 6.1, Here parallel 1’s are given as input to the UART. These parallel 1’s
are converted into serial bits at the transmitter side UART and at the receiver side then
transmitted serial bits are converted into parallel bits. It is the output. All these results are
observed are observed by simulation process by using XILINX Software.
[38]
CONCLUSION
CONCLUSION
The Project mainly deals with the chip level modeling, taking designing of UART
as example. During the course of the project it is realized and experienced the definite
advantages that a hardware description language offers over the conventional method of
designing.
VHDL coupled with simulation tools provides the designers with option of
modeling in parts and the advantages of checking the correctness of the design as it evolves.
There is a great scope for developments in the project. This project is successful in bringing up
some of the properties of UART in our design implementation using VHDL. This project is
about the UART’s that are in market today. And also given the advancements made over in it
over the past few years.
[39]
FUTURE SCOPE
FUTURE SCOPE
VHDL can be used to model even more complex chips like80386,80486 and Pentium
microprocessors. Thus there is scope for both quantitative and qualitative improvement of this
project.UART emulator card patent #: 5604870 the computers and the fast general purpose
computers which will be manufactured in the future it is therefore to be understood that, within
the scope of the claims.The future technology device intel-FT2232 as well as a UART interfaces,
FIFO interface and big-bang of 10 modes.The UM232R is a development module which uses
FTDI’S, FT232RL, one of the FTDI’S range of USB to UART.
[40]
REFERENCES
REFERENCES
BOOKS:
1. David A. Hodges, Jackson,”Analysis & Design of Integrated Circuits”, 3rd Edition, Mc-
GrawHill Publications, 2004.
2. Neil H.E.Weste, David Harris,” Principles of CMOS &VLSI Design”, 3rd Edition, 2004.
3. Mark Zwolinski,”Digital System Design with VHDL”, 1st Edition, Prentice Hall Publications,
2000.
4. Ben Cohen,”VHDL Coding Styles & Methodoligies”, 2nd Edition, Kluwer Academic
Publishers, 2002.
5. Douglas Perry,”VHDL”, 3rd Edition, Mc-Graw Hill Publications, 2000.
6. Peter J.Ashenden,”The Designers guide to VHDL”, 2nd Edition, Morgan Kaufmann
Publications, 2001
7. Sumit Ghosi,”Hardware Description Languages: Concepts &Principles”, IEEE Press, 2nd
Edition.
8. William Kafig,”VHDL 101”, Prentice Hall Publications, 2005.
9. Robert P.Colwell.”The Pentium Chronicles”, John Wiley& Sons Publishers, 2006.
10. Jan M. Rabaey, Anantha P. Chandrakasan, and Borivoje Nikolic, “Digital Integrated Circuits”, Second
Edition, Prentice-Hall Publications, 2002.
11. Neil H. E. Weste and Kamran Eshraghian, Addison Wesley, “Principles of CMOS VLSI Design”,
Second Edition, 1993.
12. Neil H. E. Weste and David Harris, Addison Wesley, “Principles of CMOS VLSI Design”, Third
Edition, 2004.
13. Sung-Mo (Steve) Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits Analysis and
Design”, Third Edition, McGraw-Hill, 2002.
14. John P. Uyemura, Brooks/Cole, “Physical Design of CMOS Integrated Circuits Using L-Edit”, 1995.
[41]
15. Dan Clein, “CMOS IC Layout”, Newnes, 2000.
16. Ben Streetman, Sanyay Banerjee, “Solid State Electronic Devices”, Fifth Edition, Prentice Hall,
2000.
17. James D. Plummer, Michael D. Deal, Peter B. Griffin, “Silicon VLSI Technology”, Prentice Hall,
2000.
18. Ron Kielkowski, Inside SPICE: Overcoming the Obstacles of Circuit Simulation, Second Edition,
McGraw-Hill, Inc., 1998.
19. Daniel Foty, “MOSFET Modeling with SPICE”, Prentice Hall, 1997.
20. Yannis P. Tsividis, “Operation and Modeling of the MOS Transistor”, McGraw-Hill, 1987.
21. R. Jacob Baker, , “CMOS: Circuit Design, Layout, and Simulation”, Third Edition, Wiley-IEEE Press,
2010.
22. R. Jacob Baker, “CMOS Mixed-Signal Circuit Design, Second Edition”, Wiley-IEEE Press, 2009.
23. Adel S. Sedra, Kenneth C. Smith, “Microelectronic Circuits”, Fifth Edition, , Oxford University
Press, 2003.
24. R. L. Geiger, P. E. Allen, and N. R. Strader, “VLSI Design Techniques for Analog and Digital
Circuits”, McGraw-Hill, 1990.
[42]
WEBSITES
1. HTTP://SUPPORT.XILINX.COM/SUPPORT/SW_MANUALS/XILINX6/.
2. WWW.FREEBSD.ORG /.. /SERIAL-UART /-
3. WWW.WEBOPEDIA .COM /TERM/U/UART.HTML
4. WWW.LAMMERTHIES.NL/../SERIAL-UART.HTML
5. WWW.UARTS.EDU
[43]