UARTIntroduction:UART is the most widely used serial asynchronous communication protocol. Typically uart is connected between a processor and a peripheral.

To the processor, the uart appears as an 8-bit read-write parallel port that performs serial to parallel conversions for the processor andVice- versa for the peripheral.

The UART core consists of a transmitter, a receiver, a modem interface, a baud generator, an interrupt controller, and various controls and status registers.

The transmitter and receiver perform parallel-to serial and serial-to-parallel conversions, respectively. Each has a 256-byte FIFO to buffer data flow.

The use of FIFO buffers increases the overall transmission rate by allowing slower processors to respond, and reducing the amount of time wasted on context switching.

Besides data transfer, they also facilitate start/stop framing bits, check various parity options, as well as detect transmission errors.

UART HAS THREE MAIN BLOCKS:1. TRANSMITTER2. RECEIVER3. REGISTER SET

TRANSMITTER:

Read

WriteTX ControlStateMachineMem

ShiftReg

Data frameBaud clock Generator Parity generator

The main function of transmitter is to convert the parallel data into serial data.

TRANSMITTER block has 5 sub-modules:

TX FIFO. TX control state machine. Shift register. Parity generator. Baud clock generator. Data frame.

TX FIFO:

SclkWriteTx_RDY_n

rst_nReadProcessorMem

P_validFIFO_Full

Tx_control state machineFIFO_readProcessorP_data [7:0]

rd_valid_data

Fifo_rd_data[7:0]

The main function of transmit FIFO is to store the processor data based on the processor data valid signal.1. System_clock: This is used to generate the baud clk. This is used only to operate the write-logic of tx_FIFO.

2. System_reset_n: It is an active low signal, when it is low, initialises all outputs to 0.

Sometimes it is operated on the system_clk and some other modules it is operated on the baud_clk.

3. Processor_valid:

When this signal is high the valid data(8-bit) is written into FIFO.

4. Processor data [7:0]:

When the processor valid signal is high then the processor valid data (8-bit) is written into tx_FIFO.

5. Tx_RDY_n:

It is an acknowledge to the processor that the FIFO is ready to accept the data.

Based on the FIFO-Full signal, Tx_RDY_n signal is generated.

If FIFO_Full is low then the Tx_RDY_n signal is low and it acknowledges to the processor that it is ready to take the data.

6. FIFO_Full: Based on the address lines of write logic and read logic, this signal is generated.

When the LSB bits of wr_addr and wr_addr are same and the MSB bit of wr_addr and rd_addr are not equal, then this signal goes high.

7. FIFO_Empty: This signal is generated, when the wr_addr and rd_addr are same then this signal will go high.Key points: Processor-valid (single bit) and processor data (8-bit) are the inputs to the transmit-FIFO from the processor.

The processor-data (8-bit) is valid only when the processor-valid is high.

System-clock and system reset-n are the user defined inputs to the transmit-FIFO.

Transmit-FIFO generates acknowledgements to the processor. These are Tx_RDY_n and Rx_RDY_n. They are active low signals.

FIFO_Full and FIFO_Empty specify the status of the transmit-FIFO.SHIFT-REGISTER:

Tx_control state machineSr_en

Data frameShiftReg

Sr_outSr_data [7:0]

1. Shift_reg_en: when this signal is high then the data is loaded into shift register from the tx_FIFO.2. Shift_reg_data [7:0]: This is the processor data [7:0] to the peripheral.3. Shift_reg_out: It is a 1-bit signal, shifts data serially Bit by bit. Shift register shifts the processor data serially if operated in single transfer mode.

Shift register reads the data from tx_FIFO and shifts serially if operated in multi transfer mode.

Shift register sends the data to the data frame after the start bit is asserted.

Parity generator:

Baud clk Gen

Baud_clk

Parity_enTx_control SM

Parity bitData frame Parity generator

Stick parityRegister set

Even parity

Parity bit is generated and sends to the data frame. To generate the parity bit the parity enable should be high.

If parity enable is high and based on stick parity conditions the required parity bit is generated.

If stick parity is low then based on the even parity, parity bit is generated.

If stick parity is high and even parity is low then parity bit is forced to 1 irrespective of even parity conditions.

If stick parity is high and even parity is high then parity bit is forced to 0 irrespective of even parity conditions.

Parity enableStick parityEven parityParity bit

0XX-

100~^(data)

101^(data)

1101

1110

Baud clock generator:

Tx_control SM

Parity_GEN

Baud_clkBaud clock GeneratorSclk

Data frame

Rd_logic of tx_FIFO

It generates baud clock based on the system clock and this clock is used to operate every sub-module in the transmitter module.

Data frame:

Baud_clkBaud clk gen

Parity_GENParity bit

Shift registerShift reg outData frame

Send startS_out

Send data

TX control state machine

Send stop

Send parity

UART frame:

Start bitD0D1D2D3D4D5D6D7Parity bitStopbit1Stop bit2

When there is nothing to be sent, the serial line is high. The first low bit is the start bit, which indicates the beginning of a new frame.

The next five to eight bits are data bits, which convey the actual information to be sent, least significant bit first.

The number of data bits per frame is configurable. If enabled, a parity bit will be sent on the serial line after the data bits.

Finally, the serial line is held high again for at least one bit to indicate the end of a frame. This is called the stop bit, which also returns the serial line to the idle state.

START BIT: it indicates to the peripheral that my valid data starts after this bit.

D0-D7: the data to be send to the peripheral.

Parity bit: It is generated by parity generator. (Optional).

STOP_BIT1 and STOP_BIT2: Based on the number of bits of data...the stop bits are determined. These are the bits which indicate end of the frame.

Data bits Required parity bit(s)

5-bit 1-bit

6-bit1.5 bits

7-bit/8-bit2-bits

Transmitter Control State Machine: The other modules of the UART transmitter are controlled by this module.

1. TRANSMITTER IDLE4h0000

2.SEND BREAK4h0001

3.Transmit error4h0010

4.Single_mode_transfer4h0011

5.Multi_mode_transfer4h0100

6.FIFO_read4h0101

7.Send start4h0110

8.Send_data_bits4h0111

9.Send_parity_bit4h1000

10.Send_stop_bit14h1001

11.Send_stop_bit24h1010

TX control state machine:

Baud clk genBaud_clkSr_en

Shift registerSr_data [7:0]

FIFO_readTX ControlStateMachine

Send start

RD control logic of tx_FIFOFIFO_read data valid

Fifo_rd data[7:0]Data frameSend data

Send stop

Parity GENParity_en

STATE DIAGRAM

Parity_enMulti transfer modeChar length == 2b11! Break_cond! Stop_bitStop_bitBreak_condChar length != 2b11Transmit Error! Parity_en DMA_signalling mode & processor valid & !FIFO_EmptySingle transfer modeSend_parity_bitSend_stop_bit2Send_stop_bit1Send breakTransmitter IDLE H

FIFO_rd_data_validFIFO_dataFIFO_readSend startSend data! DMA_signalling mode & processor valid