uart synopsys carried out by gowrav

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Digital System Design - Verilog

Project Report

on

UniversalAsynchronousReceiverTransmitter

Under the guidance of

Mrs. Anandi .V

Associate professor

Dept. of Electronics and Communication

MSRIT, Bangalore

Submitted By:

Gowrav L (1MS13LVS03)

Department of Electronics & Communication Engineering

M S Ramaiah institute of technology, Bangalore


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DSD-Verilog Mini Project - Report

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Contents

1. Aim of the project ....................................................................................................................... 2

2. Introduction ................................................................................................................................ 2

3. Working of UART ......................................................................................................................... 2

4. Flow Chart of RX and TX .............................................................................................................. 3

5. Implementation Pseudo Code .................................................................................................... 4

6. Simulation Outputs ..................................................................................................................... 5

7. Merits and De-Merits of UART .................................................................................................... 7

8. Applications of UART .................................................................................................................. 7

9. CONCLUSION ............................................................................................................................... 7

10. REFERENCES ................................................................................................................................ 8


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1.Aim of the projectTo carry out the implementation of a simple UART (Universal Asynchronous

Transmitter Receiver) on an FPGA using VERILOG.

2. IntroductionA Universal Asynchronous Receiver/Transmitter, abbreviated UART is a piece

of computer hardware that translates data between parallel and serial forms. UARTs are

commonly used in conjunction with communication standards such as EIA, RS-232

(Recommended Standards - Serial Port), RS-422 or RS-485.

The universal designation indicates that the data format and transmission speeds are

configurable. The electric signalling levels and methods (such as differential signalling

etc.) are handled by a driver circuit external to the UART.

3. Working of UARTWhen a word is given to the UART for Asynchronous transmissions, a bit called the

"Start Bit" is added to the beginning of each word that is to be transmitted. The Start

Bit is used to alert the receiver that a word of data is about to be sent, and to force the

clock in the receiver into synchronization with the clock in the transmitter. These two

clocks must be accurate enough to not have the frequency drift by more than 10%during the transmission of the remaining bits in the word

Bit

Number1 2 3 4 5 6 7 8 9 10 11

Start Bit 5 8 Data Bits Stop Bits

StartData

0

Data

1Data 2 Data 3 Data 4 Data 5 Data 6

Data

7Stop

After the Start Bit, the individual bits of the word of data are sent, with the LeastSignificant Bit (LSB) being sent first. Each bit in the transmission is transmitted for

exactly the same amount of time as all of the other bits, and the receiver looks at the

wire at approximately halfway through the period assigned to each bit to determine if

the bit is a 1 or a 0. For example, if it takes two seconds to send each bit, the receiver

will examine the signal to determine if it is a 1 or a 0 after one second has passed, then

it will wait two seconds and then examine the value of the next bit, and so on.

When the entire data word has been sent, the transmitter may add a Parity Bit that the

transmitter generates. The Parity Bit may be used by the receiver to perform simple

error checking. Then at least one Stop Bit is sent by the transmitter.


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When the receiver has received all of the bits in the data word, it may check for the

Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be used),

and then the receiver looks for a Stop Bit. If the Stop Bit does not appear when it is

supposed to, the UART considers the entire word to be garbled and will report a

Framing Error to the host processor when the data word is read.The usual cause of a Framing Error is that the sender and receiver clocks were not

running at the same speed, or that the signal was interrupted.

4. Flow Chart of RX and TX

Figure to left depicts receiver flowchart and one on right indicates transmitter

flowchart


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6. Simulation OutputsFigures below represents the Test Bench Simulation for UART TX


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7. Merits and De-Merits of UARTThe follow list describes merits and de-merits of using UARTs

Merits:

1. No clock synchronisation signal is required between transmitter andreceiver.2. Easy to implement.3. Parity bit in the frame provides a simplest error detection algorithm. 4. Cheaper since no external components are necessary.5. Universally accepted standards can be interfaced.6. Since the data is transmitted serially only 1 transmission line and 1

reception line is used.

De-Merits:

1. Too many control bits result in inefficient bandwidth usage2. No error correction codes are provided3. Slower speeds of transmission (typically < 1Mbps)

8.Applications of UARTThe UART takes bytes of data and transmits the individual bits in a sequential

fashion. At the destination, a second UART re-assembles the bits into complete bytes

as shown in figure below

9. CONCLUSIONThis design uses VERILOG as design language to achieve the modules of

UART. Using XILINX software, Saptron 3E FPGA to complete simulation and

test . The results are stable and reliable data transmission with some reference

value and great flexibility, high integration.

UART 1 UART 2Device

1 Device 21b te 1byte


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10. REFERENCES[1]. Zou,Jie Yang,Jianning Design and Realization of UART Controller

Based on FPGA

[2]. Liakot Ali , Roslina Sidek , Ishak Aris , Alauddin Mohd. Ali,

Bambang Sunaryo Suparjo. Design of a micro - UART for SoC

application [J].In: Computers and Electrical Engineering 30 (2004) 257

268 .

[3]. HU Hua, BAI Feng-e. Design and Simulation of UART Serial

Communication Module Based on Verilog -HDL[J]. J Isuanj I Yu

Xianda Ihua 2008 Vol. 8

[4]. Bhaskar, J. A Verilog HDL Primer -Pearson Education. 2001

[5] Palnitkar, Samir. Verilog HDL - A Guide to Digital Design and

Synthesis-

[6] Smith, J. Douglas. HDL design

uart synopsys carried out by gowrav

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