Types of Instruction

ADD RADD M (ADD REGISTER TO

ACCUMULATOR)

A REG F lag REG

B REG C REG

D REG E REG

H REG L REG

STACK POINTER(16)

PROGRAM COUNTER(16)

INCREMENTER/DECREMENTER(16)2LAKSHMI B.E.

A 47 XX F

B 51 XX C

ADD B

98

BEFORE EXECUTIONAFTER EXECUTION

ADD M

A REG F REG

B REG C REG

D REG E REG

H REG L REG

STACK POINTER(16)

PROGRAM COUNTER(16)

INCREMENTER/DECREMENTER(16)3LAKSHMI B.E.

2048

2049

2050

2051 XX55

65

20 50

BA

ADC RADC M (ADD REGISTER TO

ACCUMULATOR WITH CARRY)

A REG F lag REG[S Z – AC– P – C ]

B REG C REG

D REG E REG

H REG L REG

STACK POINTER(16)

PROGRAM COUNTER(16)

INCREMENTER/DECREMENTER(16) 4LAKSHMI B.E.

A 47 XX F

B 51 XX C

ADD B

98

1

99

BEFORE EXECUTIONAFTER EXECUTION

ADC M

A REG F REG[S Z – AC– P – C ]

B REG C REG

D REG E REG

H REG L REG

STACK POINTER(16)

PROGRAM COUNTER(16)

INCREMENTER/DECREMENTER(16) 5LAKSHMI B.E.

2048

2049

2050

2051 XX55

65

20 50

BA

1

BB

BEFORE EXECUTION

AFTER EXECUTION

ADI 8BITDATA [A A + 8BITDATA]ACI 8 BIT DATA[AA + C +8 BIT

DATAA REG F REG

B REG C REG

D REG E REG

H REG L REG

STACK POINTER(16)

PROGRAM COUNTER(16)

INCREMENTER/DECREMENTER(16) 6LAKSHMI B.E.

DAD REG PAIR

A REG F REG

B REG C REG

D REG E REG

H REG L REG

STACK POINTER(16)

PROGRAM COUNTER(16)

INCREMENTER/DECREMENTER(16)7LAKSHMI B.E.

20 50

DAD H

20 5020 50 +40 A040 A0

BEFORE EXECUTION

AFTER EXECUTION

SUBTRACTION

8LAKSHMI B.E.

• SUB R ; SUB R; REGISTER A A-C ;SUB REG• SUB M ; SUB H ;AA-H ;SUB MEMORY• SUI DATA; AA-DATA ;SUB IMMEDIATE DATA• SBB R;SBB C ;AA-C-CARRY;SUB REG WITH

BORROW• SBB M ;SBB H ;AA-(H)(L)-CY ;SUB MEM

WITH BORROW• SBI DATA ; AA-DATA-CY;SUB IMMEDIATE • WITH BORROW

• INR R • INR B

LAKSHMI B.E. 9

A XX

F XX

B 35 C XX36

• INR M • INR H

LAKSHMI B.E. 10

A XX

F XX

H 35 L 40

3540 A8

3541

INX REG PAIR

• INX D

LAKSHMI B.E. 11

A XX

F XX

D 35 E 40

A XX F XX

D 35 E 41

SIMILARLY……

• DCR R• DCR M• DCX REG PAIR

LAKSHMI B.E. 12

LOGIC OPERATIONS

• ANI DATA ;[AA DATA]• ANA M ;[AA (H)(L)]• ANA R; [ A A R]

LAKSHMI B.E. 13

LOGIC OPERATIONS

• ORI DATA ;[AA DATA]• ORA M ;[AA (H)(L)]• ORA R; [ A A R]

LAKSHMI B.E. 14

LOGIC OPERATIONS

• XRI DATA ;[AA DATA]• XRA M ;[AA (H)(L)]• XRA R; [ A A R]

LAKSHMI B.E. 15

• CMP B; COMPARE REGISTER A (A-B)• CMP M; COMPARE MEMORY A(A-(H)(L))• CPI DATA; COMPARE IMMEDIATE A(A-

DATA)

• CMA (COMPLEMENT ACC) • CMC (COMPLEMENT CARRY)• STC (SET CARRY)

LAKSHMI B.E. 16

RAL(ROTATE ACC LEFT THROUGH CARRY) A88H(1000 1000B)

LAKSHMI B.E. 17

• CY1 at start• AFTER EXECUTION A

D0D1,D7CARRY ,CARRYD0)

000100011

RAR (ROTATE ACC RIGHT THROUGH CARRY)similarlyD7D6,D0CARRY ,CARRYD7)

RLC(ROT ACC LEFT TO CARRY)A88H(1000 1000B)

LAKSHMI B.E. 18

• CY0 AT START• AFTER EXECUTION A11H

(D7D0,D0D1,D7CARRY )

000100010

RRC(ROTATE ACCUMULATOR RIGHT)SIMILARLY(D7D6,D0D7,D0CARRY

DATA SERIALISATION

1 0 0 0 1 1 0 0 0

P1.0

J CONDITION

LAKSHMI B.E. 20

C CONDITION

LAKSHMI B.E. 21

CONTROL AND STATUS SIGNAL

LAKSHMI B.E. 22

MACHINE CYCLE• A particular microprocessor requires a definite

time to performing a specific task. This time is called machine cycle.

• Instruction cycle(PROCESSOR CYCLE)is defined as the time required to fetch and execute an instruction.

• The function of the microprocessor is divided into fetch and execute cycle of any instruction

of a program.• The program is nothing but number of

instructions stored in the memory in sequence.LAKSHMI B.E. 23

MACHINE CYCLE

• Instruction Cycle (IC) = Fetch cycle (FC) + Execute Cycle (EC)

LAKSHMI B.E. 24

MACHINE CYCLE

• It is well known that an instruction cycle consists of many machine cycles.

• Each machine cycle consists of many clock periods or cycles, called T-states.

LAKSHMI B.E. 25

OPCODE FETCH(M1)

• The 1st machine cycle (M1) of every instruction cycle is the opcode fetch cycle.

• during (M1 cycle) – puts the program counter contents on the address

bus – reads the opcode of the instruction through read process

LAKSHMI B.E. 26

OPCODE FETCH

LAKSHMI B.E. 27

LAKSHMI B.E. 28

R CONDITION

LAKSHMI B.E. 29

In T2, the RD control signal becomes low to enable the memory for read operation.

• A low IO/M means microprocessor wants to communicate with memory.

• The μP sends a high on status signal S1 and S0 indicating fetch operation.

• The μP sends 16-bit address. AD bus has address in 1st clock of the 1st machine cycle,T1.

• AD7 to AD0 address is latched in the external latch when ALE = 1.

• AD bus now can carry data.

LAKSHMI B.E. 30

• • The memory places opcode on the AD bus• • The data is placed in the data register (DR) and

then it is transferred to IR.• • During T3 the RD signal becomes high and

memory is disabled.• • During T4 the opcode is sent for decoding and

decoded in T4.• • The execution is also completed in T4 if the

instruction is single byte.

LAKSHMI B.E. 31

Memory read machine cycle

LAKSHMI B.E. 32

Memory write machine cycle

LAKSHMI B.E. 33

IO READ MACHINE CYCLE

LAKSHMI B.E. 34

IO WRITE MACHINE CYCLE

LAKSHMI B.E. 35

MOV B,C

LAKSHMI B.E. 36