type1lv application note - murata manufacturing · *1: ieee 802.11ac full-compliance requires...

Type1LV Application note HW

©2019 Murata Manufacturing Co., Ltd.

Document No. E2B-87-1029

Introduction

This Application Note targets HW developers.

It provides how to design the Schematic and Layout, and reference RF performance

For Module specification refer to “type1lv_datasheet-*”

Document Number: E2B-87-1029

Version: 2.0

Release Date: 2019/11/21

Murata Manufacturing Co., Ltd.

Type1LV Application Note




Revision History

Revision

Number

Release Date Comments

- 2019.3.26 1st issue

2.0 2019.11.21 1.3 Reference Circuit : Updated module Pin layout based

on module datasheet.RevL




TABLE OF CONTENTS

1 Module introduction ................................................................................................................ 4

1.1 Type1LV Introduction ......................................................................................................... 4

1.2 Block Diagram ..................................................................................................................... 4

1.3 Reference Circuit ................................................................................................................. 5

2 HW Design Guideline ............................................................................................................. 7

2.1 Underneath of module ........................................................................................................ 7

2.2 Antenna ................................................................................................................................ 8

3. RF Measurement Result ....................................................................................................... 9

3.1 Tx output power level (at module antenna port) .............................................................. 9

3.1.1. WiFi ...........................................................................................................................9

3.1.2. Bluetooth ................................................................................................................. 11

3.2 Rx minimum sensitivity level (at module antenna port) ............................................... 11

3.2.1. WiFi ......................................................................................................................... 11

3.2.2. Bluetooth .................................................................................................................12

4. Current consumption ............................................................................................................ 13

4.1 WiFi .................................................................................................................................... 13

4.1.1. Tx/Rx current consumption .....................................................................................13

4.1.2. Sleep current consumption .....................................................................................14

4.2 Bluetooth ............................................................................................................................ 14

4.2.1. BLE current consumption .......................................................................................14

5. Throughput performance ...................................................................................................... 15




1 Module introduction

1.1 Type1LV Introduction

WLAN(11a/b/g/n/ac-friendly*1)+BT/BLE(BT5.0) combo SIP module with Cypress CYW43012

The package type is LGA(SM type)

This module is covered with resin molding and fully shielded with metal

MAC and BD address are embedded in OTP

*1: IEEE 802.11ac full-compliance requires support for 40 MHz and 80 MHz channel bandwidths. CYW43012 only

supports 20 MHz channel bandwidth however it supports 802.11ac’s 256-QAM for the 20 MHz channels in the 5GHz

band enabling it to offer higher throughput and lower energy per bit than 802.11n only products.

1.2 Block Diagram

Figure-1 shows module internal block diagram.

Figure-1, Block diagram

Sleep Clock

BPF

VBAT

VDDIO

SDIO

UART

Ref Clock

37.4MHz

CYW43012

5G Tx

5G Rx

2.4G Tx(WLAN)

2.4G Rx(WLAN)

LC network

For DCDC

DIPLEX




1.3 Reference Circuit

Figure-2 shows the reference circuit of Type1LV module.

1) Antenna condition for Murata Radio certification

Please add attenuator circuit between Type1LV and antenna matching if you use Murata Radio

certification. If your antenna peak gain is higher than Murata application one, please reduce

antenna gain by this pi-type attenuator.

Please refer to “Type1LV_Antenna_performance.pdf” about more detail.

1

2

3

4

5

6

A B C D E F G H

1

2

3

4

5

6

A B C D E F G H

LBEE59B1LV

GND

GND GND

GND

BT_G

PIO

_3

BT_G

PIO

_4

BT_G

PIO

_5

BT_G

PIO

_2

RF_SW

_CTRL_5

RF_SW

_CTRL_10

RF_SW

_CTRL_6

AN

T0

GND

BT_D

EV_W

AKE

SD

IO_D

ATA_2

SD

IO_D

ATA_1

SD

IO_D

ATA_0

SD

IO_D

ATA_3

SD

IO_CM

D

SD

IO_CLK

VD

DO

UT_VD

DIO

RF_SW_CTRL_8

RF_SW_CTRL_12

RF_SW_CTRL_11

BT_I2S_DO

BT_I2S_DI

BT_I2S_CLK

BT_I2S_WS

BT_PCM_CLK

BT_PCM_IN

BT_PCM_SYNC

BT_PCM_OUT

CLK_REQ

BT_UART_RTS

BT_UART_CTS

BT_UART_RXD

BT_UART_TXD

VDDIO

GND

0.1uF

GND

32.768kHz

BT_RF_O

UT

BT_RF_IN

GND

0.1uF

BT_HOST_WAKE

WL_HOST_WAKE

BT_REG_ON

WL_REG_ON

GND

4.7uF

GND

0.1uF

VBAT

VDDOUT_VDDIO

VDDIO_SFL connect to VDDOUT_VDDIO

RF line : Module certification condition

BT_RF_IN

BT_RF_OUT

ANT0

ANT :WLAN/BT

ANT0

BT_RF_IN

BT_RF_OUT

ANT :WLAN/BT

Single antennaRF line :

ANT0

ANT :WLAN

ANT :BT

BT_RF_OUT

BT_RF_IN

GND

Separate antennaRF line :

GND(1)1

GND(2)2

GND(3)3

VDDIO_SFL4

BT_HOST_WAKE5

GND(6)6

WL_HOST_WAKE7

BT_REG_ON9

WL_REG_ON10

GND(11)11

VOUT_3P312

VBAT(13)13

VBAT(14)14

GND(15)15

RF_SW_CTRL_816

RF_SW_CTRL_1217

RF_SW_CTRL_1118

GND(19)19

GND(59)59

GND(60)60

WL_GPIO_1561

GND(103)103

BT_RF_O

UT

49

GN

D(5

0)

50

BT_RF_IN

51

GN

D(5

2)

52

GN

D(5

3)

53

RF_SW

_CTRL_6

54

RF_SW

_CTRL_10

55

RF_SW

_CTRL_5

56

GN

D(5

7)

57

AN

T0

58

BT_G

PIO

_2

90

BT_G

PIO

_5

91

BT_G

PIO

_4

92

BT_G

PIO

_3

93

GN

D(9

4)

94

GN

D(1

04)

104

GN

D(1

05)

105

GN

D(1

06)

106

GND(102)102

GND(101)101

BT_I2S_DO89

BT_I2S_DI88

BT_I2S_CLK87

BT_I2S_WS86

BT_PCM_CLK85

BT_PCM_IN84

BT_PCM_SYNC83

BT_PCM_OUT82

CLK_REQ81

EXT_LPO80

SFL_CS79

SFL_IO178

SFL_CLK77

GND(48)48

GND(47)47

P146

P045

P1244

P743

P842

P641

P540

P1339

P1138

P937

GND(36)36

VDDIO35

BT_UART_CTS34

BT_UART_RTS33

BT_UART_RXD32

BT_UART_TXD31

GND(30)30

GN

D(1

00)

100

GN

D(9

9)

99

GN

D(9

8)

98

SFL_IO

276

SFL_IO

375

SFL_IO

074

GN

D(7

3)

73

GN

D(7

2)

72

VD

DO

UT_VD

DIO

28

GN

D(2

7)

27

SD

IO_CM

D26

SD

IO_D

ATA_1

22

SD

IO_D

ATA_0

23

SD

IO_CLK

24

SD

IO_D

ATA_3

25

SD

IO_D

ATA_2

21

GN

D(2

0)

20

GND(97)97

GND(96)96

GND(95)95

GND(65)65

WL_GPIO_1464

WL_GPIO_18

BT_G

PIO

_0

29

WL_GPIO_1362

WL_GPIO_1263

WL_GPIO_566

WL_GPIO_467

WL_GPIO_368

WL_GPIO_269

NC70

WL_GPIO_671

(Type1LV)

WL_GPIO_15

GND

WL_GPIO_13

WL_GPIO_12

WL_GPIO_14

WL_GPIO_5

WL_GPIO_4

WL_GPIO_3

WL_GPIO_2

WL_GPIO_6

P1

P0

P12

P6

P13

P11

P9

P8

P5(BT_DEV_WAKE)

P7(WL_DEV_WAKE)

WL_GPIO_1

2)

Figure-2, Reference Circuit

3)

1)

Attenuator

Matching




2) External 32.768kHz Sleep Clock Specifications

Table-1 shows External 32.768 kHz Low-Power Oscillator characteristics for Type1LV.

An external LPO is required.

Parameter External LPO Clock Unit

Nominal input frequency 32.768 kHz

Frequency accuracy +/-250 ppm

Duty cycle 30-70 %

Input signal amplitude 500 – 1800 mVp-p

Signal type Square-wave or sine-wave -

Input impedance*a) > 100k ohm

*a) When power is applied or switch off

3) SDIO

Please arrange SDIO lines with 50ohm and put siries-R, shunt-C parts to reject the noise if needed.

10k~100k ohm pull-ups are required on the four DATA lines and the COMD line. This requirement

must be met duting all operating states by using external pull-ups. This module doesn not have

internal pull-ups on these lines. Please confirm the performance on your board.

4) Guideline for unused pins

All I/O are not needed pull up/down for termination when you don’t use below I/O.

P0~13

WL_GPIO

BT_GPIO

FLASH

BT_I2S/PCM

CLK_REQ

RF_SW_CTRL

Table-1, External 32.768kHz Sleep Clock Specifications




2 HW Design Guideline

2.1 Underneath of module

1) Please refer to Murata Datasheet regarding to Dimensions.

*Murata is preparing DXF file that is module footprint. “Type1LV_footprint.dxf”

2) Via design between outside and inside module pad

Via Hole Φ250um

Via Land Φ400um

1)

2)




2.2 Antenna

Antenna line should be 50ohm (*). There should be enough GND via along with Antenna line. Make

sure that pi matching circuit is located right before the wifi antenna on the main board.

(*) How to make 50ohm line?

http://www17.plala.or.jp/i-lab/index_e.htm

Here are the conditions of 50ohm lines of evaluation board. (One of example)

Epsilon : 4.3

RF trace width(s) : 0.35mm

GND gap(h) : 0.18mm

GND gap(w) : 0.5mm

The line impedance is Z0 = 51.8ohm.

Antenna line

Antenna Pad

GND Via

GND Plane

http://www17.plala.or.jp/i-lab/index_e.htm




3. RF Measurement Result

3.1 Tx output power level (at module antenna port)

3.1.1. WiFi

Tx output power setting is defined by Murata nvram file.

2.4GHz

Mode Data Rate Output Power[dBm]

11b 1M 17.0

2M 17.0

5.5M 17.0

11M 17.0

11g 6M 17.0

9M 17.0

12M 16.0

18M 16.0

24M 16.0

36M 15.0

48M 15.0

54M 14.0

11n MCS0 17.0

MCS1 17.0

MCS2 17.0

MCS3 16.0

MCS4 15.0

MCS5 15.0

MCS6 14.0

MCS7 13.0




5GHz

Mode Data Rate Output Power[dBm]

11a 6M 16.0

9M 16.0

12M 16.0

18M 16.0

24M 15.0

36M 15.0

48M 14.0

54M 13.0

11n

HT20

MCS0 16.0

MCS1 16.0

MCS2 16.0

MCS3 15.0

MCS4 15.0

MCS5 14.0

MCS6 13.0

MCS7 12.0

11ac

VHT20

MCS0 16.0

MCS1 16.0

MCS2 16.0

MCS3 15.0

MCS4 15.0

MCS5 14.0

MCS6 13.0

MCS7 12.0

MCS8 10.0




3.1.2. Bluetooth

<Condition>

VBAT=3.3V, VDDIO=1.8V

Hcd.file version

CYW43012C0_003.001.015.0064.0000_Generic_UART_37_4MHz_wlcsp_ref3_sLNA

Frequency[MHz] Output Power [dBm]

DH5 3DH5 BLE

2402 9.4 5.0 5.0

2440 9.4 5.5 5.2

2480 9.1 5.7 5.3

3.2 Rx minimum sensitivity level (at module antenna port)

3.2.1. WiFi

<Condition>


FW version:version 13.10.271.111

2.4GHz

Frequency[MHz]

Rx minimum sensitivity level[dBm]

11b 11g 11n

1Mbps 11Mbps 6Mbps 54Mbps MCS0 MCS7

2412 -98.8 -89.9 -94.4 -77.7 -94.3 -75.9

2442 -98.7 -89.9 -94.6 -77.8 -94.6 -76.0

2472 -99.0 -89.9 -94.6 -77.7 -94.8 -76.1

5GHz(20MHz band)

Frequency[MHz]

Rx minimum sensitivity level[dBm]

11a 11n(HT20) 11ac(VHT20)

6Mbps 54Mbps MCS0 MCS7 MCS0 MCS8

5180 -92.2 -75.1 -92.1 -73.4 -91.8 -71.0

5500 -91.2 -75.4 -91.2 -73.7 -91.1 -71.0

5825 -90.2 -75.6 -90.3 -73.7 -90.7 -71.1




3.2.2. Bluetooth

<Condition>


Hcd.file version

CYW43012C0_003.001.015.0064.0000_Generic_UART_37_4MHz_wlcsp_ref3_sLNA

Frequency[MHz] Rx minimum sensitivity level[dBm]

DH5 3DH5 BLE

2402 -92.8 -90.8 -97.3

2440 -93.0 -90.4 -97.4

2480 -93.0 -90.3 -97.3




4. Current consumption

4.1 WiFi

4.1.1. Tx/Rx current consumption

<Condition>


WL_REG_ON:ON, BT_REG_ON:ON

FW version:version 13.10.271.111

2.4GHz

Mode Rate Tx current

Rx current[mA]*b) setting power Tx current[mA]*a)

11b 1Mbps 17.0 200

20 11Mbps 17.0 200

11g 6Mbps 17.0 195

20 54Mbps 14.0 150

11n MCS0 17.0 195

20 MCS0 13.0 140

*a) Setting value: 1024byte, 20usec interval.

*b) Carrier sense when no carrier present.

5GHz

Mode Rate Tx current

Rx current[mA]*b) setting power Tx current[mA]*a)

11a 6Mbps 16.0 300

20 54Mbps 13.0 230

11n(HT20) MCS0 16.0 300

20 MCS7 12.0 210

11ac(VHT20) MCS0 16.0 300

20 MCS8 10.0 190

*a) Setting value:1024byte, 20usec interval.

*b) Carrier sense when no carrier present.




4.1.2. Sleep current consumption

<Condition>


WL_REG_ON:ON, BT_REG_ON:OFF

FW_version: 13.10.271.57

Band Mode VBAT(3.3V) VDDIO(1.8V)

mA uA

- IEEE Power save, Inter Beacon*a) 0.024 120

2.4GHz IEEE Power Save:DTIM1*b) 0.479 119

IEEE Power Save:DTIM3 0.149 119


5GHz IEEE Power Save:DTIM1 0.368 119



*a). Idle, not associated, or inter-beacon.

*b). Beacon Interval = 100ms

4.2 Bluetooth

4.2.1. BLE current consumption

<Condition>


WL_REG_ON:OFF, BT_REG_ON:ON

Hcd.file version: CYW43012C0_003.001.015.0064.0000_Generic_UART_37_4MHz_wlcsp_ref3_sLNA.hcd

Mode VBAT(3.3V) VDDIO(1.8V)

uA uA

BLE Scan *a) 121 44

BLE Adv-Uncounnectable 1.00sec 30 39

BLE connected 1sec 29 44

*a) No devices present. A 1.28 second interval with a scan window of 11.25ms.




5. Throughput performance

<Condition>


WL_REG_ON:ON, BT_REG_ON:ON

FW_version: 13.10.271.138

2.4GHz

11n_HT20_MCS7 Tx[Mbps] Rx[Mbps]

TCP 51.2 47.8

UDP 57.2 56.9

5GHz

11ac_VHT20_MCS8 Tx[Mbps] Rx[Mbps]

TCP 60.8 66.8

UDP 68.9 69.7

(END)

type1lv application note - murata manufacturing · *1: ieee 802.11ac full-compliance requires...

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