tutorial xcal feb(daq) croc
DESCRIPTION
Tutorial XCAL FEB(DAQ) CROC. Calorimeter ECS Tutorial Frédéric Machefert Thursday June 26th, 08. A FEB. A CROC. A crate... with almost no the cable. CROC (no front panel) . FEB. ECAL. 2x7 crates located on top of the calorimeter. ECAL Crates - Side A. ECAL Crates - Side C. - PowerPoint PPT PresentationTRANSCRIPT
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TutorialXCAL
FEB(DAQ)CROC
Calorimeter ECS Tutorial
Frédéric MachefertThursday June 26th, 08
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A FEB
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A CROC
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A crate... with almost no the cable
CROC (no front panel)FEB
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ECAL
ECAL Crates - Side C ECAL Crates - Side A
2x7 crates located on top of the calorimeter
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HCAL
HCAL Crates - Side C HCAL Crates - Side A
2x2 crates located on top of the calorimeter
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PVSS projects
The PC hosting the XCAL DAQ projects are : ECAL C : ECDAQHVC01w
ECAL A : ECDAQHVA01w
HCAL C : HCDAQHVC01w
HCAL A : HCDAQHVA01w
The projects directly driving the hardware areECAL C : ECDAQC1
ECAL A : ECDAQA1
HCAL C : HCDAQC1
HCAL A : HCDAQA2
start working by opening the FSM Editor NavigatorPermits to navigate in the hierarchy of the hardware controlled by the project
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Configuration of a crate : FEB + CROC (I)Usually, configuration is performed from the top of the DAQ hierarchy (main console)
If you need to configure “manually” a crate
Select the crate
Press left button
Select “view” button
This opens the crate panelIf something is wrong some/all cards are in ERROR,...
CROC
FEBHCDAQC1
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Configuration of a crate : FEB + CROC (II)
To configure an elementPress the “State” button of the element
Select “Configure”
The crate or boards should change its states to READY
Running the boards is usually done from the top (main console)
For the FEB/CROC
READY ∼ RUNNING
Only monitoring counters reset
Select “Start” from “State” button
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Configuration of a crate : FEB + CROC (III)
A crate in good shapeIf everything is all right, ECAL/HCAL will appear “RUNNING” in the main console
Open a board configuration panel
Select board
Press the left button
Select “view” option
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FEB : Sequencer configuration
Sequencer configuration
Clock polarity for DAQ
Delay chip tuning time alignment (global synchro)
BXID reset : alignment of BXID between FE-TELL1-ODIN
No Effect :obsolete, spy, ...
Most of the parameters have their normal value.If are different from board to board :
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FEB : front-end BGA configuration
FE PGA config.L0 Latency per block of 16 channels
Permits to correct for wrong cable length for pin diode
Pedestal subtraction
No subtract.
Subtract Min (evt-2,evt-1)
Subtract Min (evt-1, history±val)
pin diodes !149 maybe not the final value ?
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FEB : general state/control
Derandomizer state
FEB has two derandomizers types
in FE PGAs
In Seq PGA
which are empty after a while if no event is processed (green LED)
FEB general settings
Front panel LED should be off (induced noise)
Mode should be PHYSICS (no test pulses)
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FEB : resets and panel update
Glue reset General board reset
Only way to reset the delay chips
SeqPGA reset
FePGA resetsA single FePGA may be selected
Parameters are refreshed only when opening the panel
May force a refresh with the “update” button
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FEB : channel specific settings
Trigger configuration
Trig calibration constant
Trigger factor 4
Timing conf.ADC sampling time
Clock polarity (BGA sampling)
Test ModesShould be OFF !
RAM Pattern
Pulser Mode
Important : Time configuration will depend on channel time alignmentsClock value, Clock polarity and Calib Constant may also be different from what is showed
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FEB : Automatic polarity for BGA sampling
BGA sampling polarity
depends on the ADC sampling time
The dependence has been measured
Automatic polarity
The clock polarity is re-evaluated and changed in the panel when ADC sampling is modified
Need to apply to set the new configuration
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FEB : Masking a channel in the trigger
Fast way of masking a channel
Setting its calibration constant to 0 has the effect of masking it
Woud it be the good place to add a button to update the PHYSICS recipe for that FEB and with the masked channel(s)
Uneasy link with the geometry
Would have to be implemented...
Update PHYSICS Recipe(not yet implemented)
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FEB : fast tuning
Setting may be changed for the 32 channels altogether
Toggle buttons
Spin boxes
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CROC : crate power controlControl power failure of a board
A red LED means a power cut (SEL?) in a slot
CROC stores transitions
Status is always OK for empty slots
Switch power on a board
The grey button permits to act on the power line of a board.
Don't forget to apply
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CROC : crate configuration control
Crate Configuration
A picture shows what the CROC knows about the load of the crate
Change the CROC configuration
It is possible for a user to change the recipe setting by acting on the button
Don't forget to apply
Read/Write crate ID
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CROC : TTC input
TTC signalsClock may be feed through a NIM input
Normal situation is “LHC” (TTCrq board)
L0 and Channel B can be sent through a NIM input or through a software command. “Normal” situation is LHC (TTCrq board)
A red colour is the sign of something going wrong...
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CROC : crate timing control
The TTCrq signals may be shifted
The “global” clock of the crate may be shifted by steps of 100ps.This is the fine tuning.
L0/channelB commands may be delayed by several clock beats. This is the coarse tuning.
Control boxesShow the value read back after applying
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CROC : FEB clock/data capture control
FEB clockThe “global” clock may be shifted again before being sent to the front-end boards (FEB tuning)
The CROC may capture the data coming from the FEB with a variable sampling time. This sampling time is defined by the “CROC” synchronisation tuning.
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CROC : DAQ control
The GOL samples the data from two types of PGA
4 FePGA
1 SpyPGA
Clock polarityThe clock polarity used by these PGA to send the data to the GOL may be changed :
Direct
Inverted
polarities
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CROC : GOL control
Two operation modes for the GOL
PHYSICS : the CROC sends data from the FEBs
TEST : the GOL are configured to send a fixed pattern – BER
A single GOL may be BER activated
The RED colour for the LED means BER
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CROC : resets
Crate ResetsFull reset of
The Master
The specs Mezzanine
The glues of the FEBs
This also resets
FEPGA
GOL
Delay Chip
Specific resetCROC reset = reset of
Delay chip
FEPGA
GOL
You may also select what you want to reset
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CROC : warnings
WarningsPower failure
Excessive temperature
>2300
Calibration ?
FEB header synchronisation
L0 counters
From TTC
From Headers
TTC
Ready
Fibre Locked
Data Parity
1 bit/Fe PGA
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CROC : temperature monitoring
Temperature monitoring
Show the temperature trend since the CROC panel is open
Counter resetsAll the counters
Header sync.
L0 counters
Parity error
are reset after going in states
READY
RUNNING
!
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References
EDMS notes : FEB : EDMS 909465
https://edms.cern.ch/file/909465/1/FEB_909465.doc
CROC : EDMS 909466
https://edms.cern.ch/file/909466/1/CROC_909466.pdf
TWIKI tutorialsFEB tutorial
http://frederic.web.cern.ch/frederic/PVSS/PVSS_FEBTutorial.html
CROC
http://frederic.web.cern.ch/frederic/PVSS/PVSS_CROCTutorial.html