tuning development of distributed real-time systems with ... · ! which type of application"...
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Tuning Development of Distributed Real-Time Systems with SDL and MSC:
Current Experience and Future Issues
"Eighth SDL Forum"(SDL '97)
Evry, FranceSeptember 23 - 26, 1997
Rainer GerlichBSSE System and Software EngineeringAuf dem Ruhbuehl 181D-88090 ImmenstaadPhone: +49/7545/91.12.58Mobile: +49/171/80.20.659Fax: +49/7545/91.12.40e-mail: [email protected]
BSSE System and Software Engineering
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Foreword
!!!! Overloading of terms
" performance and tuning
1. resource utilisation
2. efficiency of system development
3. quality of a system and early system validation
!!!! Message
" SDL is helpful for such system tuning and increasing of performance
" however, use of SDL and SDL tools needs to be tuned
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
SDL and Heterogeneous Distributed (Fault-Tolerant) Systems (1)
!!!! which type of application" SDL not necessarily limited to "classical" protocol applications
e.g." embedded real-time systems (OS like VxWorks, space application)
" client-server systems (UNIX-based, Solaris/Sparc, Solarisx86, Linux)
!!!! optimised usage of SDL" behavioural part of an application (system control) in SDL
" functional part in C / Ada
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Example: Embedded On-Board Space Real-Time System
Data Bus 1
Devices 1 Devices 2
StarSensor 2
SunSensor 2 Gyro 2 Thruster2
Data Bus 2
Cross-ChannelData Link 1
Processor 1 Processor 2
FlightControl2
Heart-Beat 2
Monitoring Processor
Bus CrossCoupling
OBAC
Control1Flight Heart-
Beat 1
SunSensor 1 Gyro 1Star
Sensor 1 Thruster1
Vital Data & Cmds.
Sensor Data & Actuator Commands
Heart-Beat
Sensor Data &
Actuator Commands
Reconf. Cmds. Reconf. Cmds.
Sensor Data &
Actuator Commands
Cross-ChannelData Link 2
case study: coherent transition from specification to design
from simulation (UNIX) to target system (UNIX, VxWorks)
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Heterogeneous Distributed Fault-Tolerant System
ICIH
Tower
DAT Tape 4GB Hard Disk
ICLF (1): Call Data ProcessingDatabase Server Solaris
SCSI 1
Terminal Server
Streamer Tape
Tower
DAT Tape4GB Hard Disk
ICLF (2): Call Data Processing
Database Server Solaris
SCSI 2
LAN1
Billing System
Report Printer
Database Client Windows NT / Oracle
ICLF (3): Reporting & Database Maintenance
Streamer Tape
ICIH ICIH ICIH ICIH ICIH
ISDN1 ISDN2
LAN2
LAN3
LAN3
RS232/Terminal ServerRS232/Terminal Server
Remote Data Acquisition
UNIX / Windows
Data Processing
WindowsC / C++
MMI / Database
Oracle
UNIX/Solaris/LinuxSDL / C
SDL / C
andArchiving
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Software Architecture
ICLF (1)MMS
Monitor & MessageSubsystem
Call Receiving&
ConversionSubsystem
CRCS
Call Data StorageSubsystem
CSS
Hot BillingSubsystem
HBSMan Machine
InterfaceSubsystem
MMIS
Server Part
Man MachineInterface
Subsystem
MMIS
Client Part
Reporting & Database Maintenance
Call Receiving&
ConversionSubsystem
CRCS
Call Data StorageSubsystem
CSS
Hot BillingSubsystem
HBSMan Machine
InterfaceSubsystem
MMIS
Server Part
ICLF (2)MMS
Monitor & MessageSubsystem
ICLF (3)
Communication
ISDN
Subsystem
COMS
Communication
ISDN
Subsystem
COMS
SDLSolarisx86
Windows NT
Oracle
Database
Subsystem - SubsystemInformation Exchange
Recovery Data & ISDN Data
ICLF3 Status & Commands.
Status, Statistics & Log-Information
Hot-Billing Information
Hardware DaemonStatus Monitoring
Hardware DaemonStatus Monitoring
LAN
Solarisx86SDL
Oracle
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
SDL and Heterogeneous Distributed (Fault-Tolerant) Systems (2)
!!!! why SDL?" strong by formalisation of behaviour (FSM)
" strong by formal description of scenarios (MSC)
" strong by verification means (tool simulators, exhaustive simulation)
" efficient by capability of (automated) code generation
!!!! customisation needed for more general class of applications" coherent transition from specification down to target code generation
and final system" (early) system validation
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Experience!!!! space domain
" selected for ESA/ESTEC for a new lifecycle approachEarly System Validation: EaSyVaDe
" top-down refinement using executable SDL models
" safety-critical / fault-tolerant real-time embedded systems
" early and complete system validation
" need for behavioural, functional and performance validation
" extension of SDL and ObjectGEODE towards performance validation andcomplete system validation
!!!! enhanced SDL tool environment" experience by ESA/ESTEC studies: EaSySim
" enhancement and complete new approach: EaSySim II (BSSE)
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Lessons learned
! performance needs to be considered already during exhaustive simulation
! specification modelling may no fit with needs of target system
! rules needed for coherent transition down to target code generation
! state explosion prevents to take real benefit of SDL strongness
! specific modelling approach needs to be supported to reduce number of systemstates as supported by EaSySim II
! introduction of performance (timing) reduces number of system states
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Impact by Logical Faults and Performance Aspects
without performance
performance impact
+ SDL subset
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Dependence of System States on Number of SDL Processes
from this limitationhelps to escapes
reentrant approach:EaSySim II
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Problems with Correct System Validation
!!!! Representative modelling" verification / validation methods / tools only respond to a given model
" performance aspects (timing, resource usage) significantly impact results
" validation of a high level model does not mean anything
" response is needed from the system in the real environment
" in the real environment a system tells you if you are right or wrong
!!!! if not" it is possible to succeed for an erroneous system, still believing it is correct
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
The 2-Dimensional Life Cycle
Target SystemHost System
Target CodeSimulation
Specification
Design
Final System
Platform
PhasesLife Cycle
Hardware-SoftwareIntegration
Status Cross-Check
Refinement
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Validation Example System Architecture
Processor(Master)
from_proc to_proc
masterrequest
slaveresponse
slave - slavecommunicationcontroled by
masterA / IR B / RS
Device n(Slave)
Device 1(Slave)
Device 2
(Slave)
Source Sink
Interrogation (IR)
Response (RS)
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Processor Device X(Master) (Slave)
Source
Device Y(Slave)SinkInitiator
poll sink
poll source
sink ready
source ready
condition source
condition sink
request data
transmit datatransmit data
transmit datatransmit data
request data
transmit datatransmit data
request data
check sourcecheck sink
source ok
sink ok
more requests
Problem:Due to varying propagation times in a network the inital sequence of signals may not be the final sequence!
Requirements for transmission:
- data must arrive in requested order- any sequence of request/transmit signals is
allowed which matches this requirement
variation of sequencesallowed for eqivalentsignals !!!ok signals may arrivein any order
variation of sequencesallowed for eqivalentsignals !!!ready signals may arrive in any order
Commissioning Phase
Transfer Phase
Termination Phase
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
A
Dev. 1
chck2poll 2 poll 1
proc
Dev. 2 proc
condition 2 condition 1
poll devicesProcessor wait for rdy condition devices
proc
B 2 rdy 1 rdy
datarqu
datatrns
datarqu
datarqu
proc proc
datatrns
datatrns
datarec data
rec
datarec
chck1
proc
fault
procchck
Illegal data !
chck
1 ok2 ok
data requestdata reception
check dev.rec. checks
cond.
cond.Source
Sink
Transfer has already been terminated!
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Principal System Structure
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Modelling Approach (1)
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Functional Bus with Two Uni-Directional Bus LinesSimple Functional Bi-Directional Buswith Broadcasting
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Modelling Approach (2)
FSM of Uni-Directional Bus Line with Clock (Device-to-Processor Line)
Fully Representative Architectural Bus
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Results (1)
!!!! question: is the set of SDL states (not considering performance) asuperset of system states (when considering performance)?" answer: it is not" as verified by the "simple" example" consequence: results of simulation may give the wrong answer
!!!! modelling task" 9 models at different degree of refinement and representativity
3 functional and 6 architectural models
architectural model = refinement towards real system architectureconsideration of timing
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Results (2)
!!!! evaluation
" models yielding low performance on the target system lead to correct results,4 out of 9, amongst which the 3 functional modelslow performance = 33% of optimum performance
" verification of 3 out of 6 of the architectural models did not give thecorrect result(predicted "no problems", although there are problems)
" for one architectural model it was correctly predicted that it will not workin the target environment
" for the architectural model yielding optimum performancethe result was correct
" when running this correct and optimised architectural model in afunctional representation (zero timing) it was rejected as erroneous
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Results (3)
!!!! evaluation (c'td)
" 2 out of 3 erroneous (exhaustive) simulation runs did not terminate
" the optimum architectural model terminated with lower system states andtransitions than one of the functional modelsit was close to the states and transitions of the (simple) functional modelsthis proves that a more refined system does not necessarily cause stateexplosion due to performance enhancement
" filtering of system states / transitions may hide (serious) problems
!!!! conclusion
" performance optimisation for the target system is a critical source of bugs(which may not be detected by SDL / SDL tools in the current shape)
" limiting verification to a (simple) functional model only andextending / modifying this model later towards the real functionalityinvalidates the previous results
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Consequences!!!! consequence 1:
" behavioural, functional and performance aspects need to be consideredalready during simulation
" for comparison and cross-checking, the response from the real systemshould always be available
!!!! consequence 2:
" the final system needs to be subject of validation / exhaustive simulation
" it is not sufficient and dissatisfying to "play" with simplified models
" system states need to be sufficiently low to succeed withexhaustive simulation
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Performance and SDL!!!! What is meant by "performance extension of SDL" ?
" representative performance modelling" not meant: stochastic modelling of arrival times, queuing times, latencies, ...
!!!! Why?" phases between signals will impact the verification result" performance may change the order of signals in a correlated manner
not possible by pure functional or stochastic performance modelling" on different physical channels different propagation times may occur" such systematic impact may only randomly hit by stochastic performance
modelling
!!!! What for which purpose?" stochastic performance modelling for estimation of throughput" accurate performance modelling for correct system validation and
for minimisation of system states and transitions, and for calculationof throughput
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
The EaSySim II ∆∆∆∆-Approach
CommunicationNetwork
Resource,
&Interface Mgt.
Scenario
EaSySim IIModellingApproach
ComponentsFunctional
Application Data
Resource Access,&
Scenarios
Access of External Tools,Resource Access,
&Scenarios
Access of External Tools,
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
EaSySim II (1)
!!!! History
" EaSySim II is based on the experience obtained by the previousESA/ESTEC studies OMBSIM and DDV
!!!! Status
" implementation of an on-board space data management system(case study)from specification to design and target environment
" implementation of the generic approach for a distributed system(air traffic control)re-entrant SDL processes
" realisation of a fault-tolerant commercial data acquisition systemcoupling of system components via Ethernet/ISDN, andcoupling with Oracle DBheterogenous, distributed environment
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
EaSySim II (2)
!!!! Features
" extends SDL and ObjectGEODE tool towards performance validation" is based on extensions written in SDL and C" allows for communication between SDL and "foreign", self-standing software" allows to deal with on-line (re)configuration of fault-tolerant systems" allows to reconfigure a system without recompilation" provides a modelling philosophy which optimises system validation" provides the corresponding environment" provides templates for building SDL processes" provides error detection mechanisms and related software" provides software to evaluate performance loads" allows for generic modelling: one SDL process + n data sets" enforces reuse
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Conclusions (1)
!!!! risk reduction and higher quality due to
" powerful verification and code generation capabilities ofSDL and ObjectGEODE
" enhancement by performance matters towards complete andearly system validation
" continuous verification and cross-checking capabilities over the life cycle
" automated transition: 15 min for installation, verification and execution:simulation (UNIX),code generation (UNIX,VxWorks),execution (UNIX,VxWorks)
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering
Conclusions (2)
!!!! higher efficiency at higher quality
" EaSySim II: ~300 operators, 5.000 SDL LOC (net), 25.000 C LOC (net)
" ATC study (simulation only)
~4.500 SDL LOC (net), 250 man hours, 40 C LOC per man hour
" commercial fault-tolerant data acquisition system
~ 10.000 SDL LOC (net, application)(34.000 LOC in pr-file incl. EaSySim II)yielding ~20.000 C LOC
~ 20.000 C LOC (net) in addition (without EaSySim II and database)~ 40.000 C LOC (net) in total, existing now~ 2500 man hours for completion (estimation)~ 16 C LOC per man hournot visible by the figures: degree of reuse in SDL and C by EaSySim II organisation principles
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(C) Copyright Rainer Gerlich, BSSE 1997
BSSE System and Software Engineering