trends in integrated circuits technology - stanford · pdf fileworld ic market by technology...

1

EE311/ Trends1 tanford Universityaraswat

Prof. Krishna Saraswat

Department of Electrical EngineeringStanford UniversityStanford, CA 94305

[email protected]

Trends in Integrated CircuitsTechnology


Courtesy Prof. Tsu-Jae King

(Sources: VLSI Research Inc.; UnitedNation yearbook; World BankDatabase; IMF)

Miniaturization => Market growthMiniaturization => Market growth

Technology Scaling

Investment

Market Growth

Better Performance/Cost

Semiconductors havebecome increasingly moreimportant part of worldeconomy

2


World IC Market by Technology

Silicon CMOS has become the pervasive technology

Ref: Chang and Sze, ULSI Technology, 1996


Moore’s Law

108

107

106

105

104

103

102

101

100

109

1010

’60 ’65 ’70 ’75 ’80 ’85 ’90 ’95 ’00 ’05 ’10

Transistors Per DieTransistors Per Die

1011

1K1K4K4K 16K16K

64K64K256K256K256K

1M1M1M

16M16M4M4M

64M64M64M

40044004

80808080808080868086

8028680286i386™i386™

i486™i486i486™™PentiumPentium®®

MemoryMemoryMicroprocessorMicroprocessor

PentiumPentiumPentium®® IIIIPentiumPentium®® IIIIII

256M256M512M512M512M

PentiumPentium®® 4ItaniumItanium®®

1G1G2G2G 4G4G

128M128M

IC Performance to Gordon Moore’s Prediction

Source: Intel

3


Feature Size Trend

0.001

0.01

0.1

1

1980 1990 2000 2010 2020

micron

Generation

LGATE

Gate length is not true measure of transistor size


Generation:

Intel386™ DXProcessor

Intel486™ DXProcessor

Pentium® Processor

Pentium® II Processor

1.5µ 1.0µ 0.8µ 0.6µ 0.35µ 0.25µ

Example: Microprocessor Evolution

4


MOS Device Scaling

Why do we scale MOS transistors?1. Increase device packing density ~ α2

2. Improve frequency response (speed) ~ a3. Power/ckt: ~1/α2, power density constant4. Improve current drive (transconductance gm)

!

gm ="ID

"VG VD = const

#W

Lµn

Ko x

to xVD for VD <VDSAT

, linear region

#W

Lµn

Ko x

to xVG $ VT( ) for V

D>VDSAT

, saturation region

Constant E Field ScalingAll device parameters are scaled bythe same factor α.

• Gate oxide thickness tox ↓• Channel length L ↓• Source/drain junction depth Xj ↓• Channel doping ↑• Supply voltage VD ↓


Intel’s Transistor Research down to 10nm

65nm process65nm process2005 production2005 production

30nm30nm

45nm process45nm process2007 production2007 production 32nm process32nm process

2009 production2009 production

15nm15nm

22nm process22nm process2011 production2011 production

Source: Intel

10nm10nm

DNA is 15 nm wideDNA is 15 nm wide

20nm20nm

Electronics is NanotechnologyElectronics is Nanotechnology

5


Speed increases as a result of scaling

Source: Mark Bohr, Intel

0.01

0.1

1

10

100

0.001 0.01 0.1 1LGATE (um)

Gate

Delay

(ps)

Limit


Physical Limits in Scaling Si MOSFET

Substrate

Gate

Source Drain

Gate stack• Tunneling current ⇒ Increased Ioff• Gate depletion ⇒ Increased EOT

Source/Drain• Contact resistance • Doping level, abruptness

Channel• Surface scattering - the “universal mobility” tyranny• DIBL ⇒ drain to source leakage• Subthreshold slope limited to 60mV/decade (kT/q) ⇒ Increased Ioff• VG - VT decrease ⇒ reduced ION

Net result: Bulk-Si CMOS device performance increase commensurate withsize scaling is unlikely beyond the 70 nm node

High E-Field• Mobility degradation• Reliability

te

6


MOSFET Scaling Limit: Leakage

Lo et al.,IEEE EDL, May 1997.

Gate Leakage S/D Leakage

Source: Marcyk, Intel

Total Leakage Trend

Total Power Trends

Ability to control Ioff will limit gate-length scaling– Thermionic emission over barrier– QM tunneling through barrier– Band-to-band tunneling from body to drain

To suppress D/S leakage, need to use:– Higher body doping to reduce DIBL

⇒ lower mobility, higher junction capacitance, increased junction leakage– Thinner gate dielectric to improve gate control ⇒ higher gate leakage– Ultra-shallow S/D junctions to reduce DIBL ⇒ higher Rseries


45

MOSFET Scaling Problem: Saturation of Saturation of IIDsatDsat

200

400

600

800

0.1 0.2

0.25

0.3 0.4 0.6 0.8 1.0

NMOS

PMOS

IDsat (A/m) (drive current)

Channel Length (µm)

• Data from IBM, TI, Intel, AMD, Motorola andLucent

• Low OFF current desirable

0

0.4

0.8

1.2

1990 1995 2000 2005

1

10

Supply

Voltage (

V)

Drive C

urr

ent (m

A/µ

m)

Changhoon Choi, PhD Thesis, Stanford Univ., 2002

Constant OFF current Limit Relaxed OFF current Limit

Source: Intel

Low Vt

High Vt

IOFF,high Vt

IOFF,low Vt

Vg

log Id

0

7


!

Eeff =q

"Si(Ndep +# $ NChannel ) Ndep= depletion charge density

NChannel = charge induced in the channel

Increases in substrate doping ⇒ Ndep ⇑ Gate oxide thickness decrease ⇒ NChannel ⇑ Eeff increases with scaling ⇒ µ ⇓ Reduced gate oxide thickness increases remote charge scattering ⇒ µ ⇓ High k dielectrics have higher coulombic scattering due to surface states

and phonon scattering ⇒ µ ⇓

Coul

ombi

c Phonon

SurfaceRoughness

µ

Eeff

Effects of Scaling Bulk MOSFET on Mobility

S. Takagi et al., IEEE TED, 41 (1994) 2357. srphCeff µµµµ

1111++=


New Structures and Materials forNanoscale MOSFETs

1. Electrostatics - Double Gate - Retain gate control over channel - Minimize OFF-state drain-source leakage2. Transport - High Mobility Channel - High mobility/injection velocity - High drive current for low intrinsic delay3. Parasitics - Schottky S/D - Reduced extrinsic resistance4. Gate leakage - High-K dielectrics - Reduced power consumption5. Gate depletion - Metal gate

1

23

GG

Si

S D Si

SiO2

C

BULK SOI Double gate

Bottom Gate

Top Gate

Source Drain

High µchannel High-K

45

8


Combining New Device Structures withCombining New Device Structures withNew MaterialsNew Materials

We will be here withthese innovations

We arehere today

• With better injection and transport we may be able toimprove MOSFET ION

• With better electrostatics we may be able to minimize Ioff


0.001

0.01

0.1

2000 2010 2020

micron

1

10

100

nm

45 nm

65 nm

32 nm

22 nm

16 nm

11 nm

8 nm

Generation

LGATE

Evolutionary

CMOS Exotic Revolutionary

CMOS

Nanotechnology Eras

ReasonablyFamiliar

NanotubesNanowires

ReallyDifferent

Source: Mark Bohr, Intel

9


Scaling of MOS Gate Dielectric

(Ref: S. Asai,Microelectronics Engg., Sept. 1996)

Gate SiO2 thickness is approaching < 10 Å to improve device performance• How far can we push MOS gate dielectric thickness?• How will we grow such a thin layer uniformly?• How long will such a thin dielectric live under electrical stress?• How can we improve the endurance of the dielectric?

ID ! gm !K

thickness


•Below 20 Å problems with SiO2– Gate leakage => circuit instability, power dissipation– Degradation and breakdown– Dopant penetration through gate oxide– Defects

Problems in Scaling of Gate Oxide

Defects and

nonuniformity of film

Dielectric breakdown

Reliability due to

charge injection

Si substrate

Polysilicon gate electrode

Dopant

penetration

gate oxide

Leakage current

10


Dielectric Degradation

What are the mechanisms for damage and breakdown?How can we engineer the gate dielectric to minimize the damage?

• Degradation during device operation due to high E field causing current injection• Degradation during fabrication due to charging in plasma processing

cathode

e

Anode

oxide

Eox

N(E)

E


0.00001

0.001

0.1

10

1000

1801301007050

Technology Generation (nm)

Cur

rent

(µA

/µm

)

Igate

Ioff

Ion

Source G. Bersuker, et al. Sematech

Gate Oxide Scaling Issues: Leakage

• Ion is not increasing with scaling • Igate ⇑, power dissipation ⇑• Circuit instability

11


High-k MOS Gate Dielectrics

K ≈ 20

Historically Cox has been increased by decreasing gate oxidethickness. It can also be increased by using a higher K dielectric

Si3N4 K ≈ 8

40 ÅToday Near future

Long term

20 Å SiO2 K ≈ 4!

ID"C

ox"

K

thickness

100 Å high K

Si

Higher thickness -> reduced gate leakage

Ichannel ∝ charge x source injection velocity∝ (gate oxide cap x gate overdrive) vinj∝ CCoxox (VGS - VT) Esource µµinjinj


Perkins, Saraswat and McIntyre,Perkins, Saraswat and McIntyre,StanfordStanford Univ Univ. 2002. 2002

Capacitance and Leakage for High-k GateDielectric Films Grown Using ALCVD

Gat

e Le

akag

e (A

/cm

2 )

10-10

10-8

10-6

10-4

10-2

100

0 0.05 0.1 0.15 0.2

Leakage (A/cm

2) @ V

FB

± 1 V

1/C'

ox (µm

2/fF)

SiO2

4 nm

2.5 nm

ALCVD ZrO2

Gat

e C

urre

nt@

VFB

+1V

(A/c

m2 )

Equivalent SiO2 Thickness (nm)

Silicon Germanium

Chui, Kim, Saraswat and McIntyre,Chui, Kim, Saraswat and McIntyre,StanfordStanford Univ Univ. 2004. 2004

12


!s = f VG( ) =1

"VG

!

ID"QI " eqVG /# kT

!

QI " eq#s /kT

!

" =1+1

2 # C ox

q$sNa

|%p |Where

Subthreshold Behavior

source

VG

• Diffusion of carriers over thebarriers to the channel.

• Fermi-dirac distribution ofcarriers: e-E/kT

• Gate reduces the barrier tocurrent flow.

Fermi Diracdistribution

draine

VT

VDD

ID

(log scale)

VG

ILEAK

or

IOFF

VDD- V

T

60 mV/decade60 mV/decade

ION

ON

OFF

(ln )

G

D

VS

I

!=!


In devices with long channel lengths, the gate is completely responsible fordepleting the semiconductor (QB). In very short channel devices, part of thedepletion is accomplished by the drain and source bias

Since less gate voltage is required to deplete QB, VT↓ as L↓. Similarly, as VD

↑, more QB is depleted by the drain bias, and hence VT↓. These effects areparticularly pronounced in lightly doped substrates.

Effect of Reducing Channel Length

junctiondepletion

region

poly gate

n+ n+

p-substrate

poly gate

n+ n+

p-substrate

depleted by gate charge

VT

Drawn Channel Length, L

VT

Supply Voltage, VD

13


p-well

poly gate

n+ n+

VDD

Drain-Induced Barrier Lowering (DIBL)• Exacerbates subthreshold leakage in short-channel devices• Soft punchthrough induced by drain-to-substrate depletion region

• |VT | ↓ as VD ↑ [drain-induced short channel effects (SCE)]• VD ↑ drain-to-substrate depletion region grows with more reverse bias• Lateral electric fields in drain-induced depletion region lowers source-to-

channel barrier, allowing more carriers to diffuse from source to channel

reduction of electron barrierheight in conduction band (CB)

at edge of source

CB

VDD

source drain

p-well

poly gate

n+n+


Q depletedby source

Q depletedby drain

B B

N+ source N+ drain

Gate

P-Si

Depletion region

L!

L

rj

VT = VFB ! 2 "#F !QB

Cox" 1 ! 1+

2 "W

rj!1

$

% &

'

( ) "rj

L

*

+ ,

-

. /

•Roll-off in threshold voltage as the channel length is reduced•VT roll-off is reduced as junction depth(rj) is decreased•Sheet resistance increases as junction depth is reduced

L. Yau, Solid-State Electronics, vol. 17, pp. 1059, 1974

Why do we need to scale junction depth?

14


Source: Jasonn Woo, UCLA

30 nm 50 nm 70 nm 100 nm0

20

40

60

80

100

120

140NMOSScaled by ITRS Roadmap

Rc

Rdp

Rext

Rov

Physical Gate Length

Serie

s R

esis

tanc

e (o

hms)

Rc RdpRext

Rov

x

y = 0

GateSiO2

Metal

Next(x)

Nov(y)

Source/Drain Resistance

Problem in junction scaling:• Sheet resistance of a junction is a strong function of doping density• Maximum doping density is limited by solid solubility and it does not scale• Silicidation can minimize the impact of junction sheet resistance (Rs,Rd)• Contact resistance Rc is one of the dominant components for future technology


Contact Resistance

Specific contact resistivity

Doping density

(Ref: S. Swirhun, PhD Thesis, Stanford Univ. 1987)

!c = !co exp2"Bqh

#sm*

N

$

% & &

'

( ) ) ohm * cm2

• Contact resistance is a strong function ofdoping density at the metal/silicon interface

• Solid sulubility of dopants does not scale !

PROBLEMS

15


Solutions to Shallow JunctionResistance Problem

Extension implants Elevated source/ drain

Silicidation Schottky Source/Drain


Problems with Poly-Si Gate.This occurs because of high E - field due to a combination of highersupply voltage and thinner gate oxide.

• Effect of depletion is to increase effective tox and thus reduce Cox• A reduced Cox implies reduction in gm and thus ID(on)• Ionized impurities in the gate electrode cause “remote charge scattering”

⇒ Reduced mobility

tox(electrical)

tox(physical)

Gate depletion

Oxide

Substrate

Poly-Si gate

Need metal gate electrode with proper workfunction

16


Ultra-Thin Body Single Gate SOI

Ultra-Thin Body DoubleGate SOI

Evolution of MOSFET Structures

GateGate

Silicon Substrate

Source Drain

TBOX

Si

SiO2

SOI

Source Drain

Gate 1Gate 1 Vg

Tox

SOI

Gate 2Gate 2

Si

Ref: Philip Wong, IEDM Short Course, 1999

BULK

Advantages of Ultra-Thin Body SOI• Depleted channel ⇒ no conduction path

is far from the gate• Short channel effects controlled by

geometry• Steeper subthreshold slope• Lower or no channel doping• Higher mobility• Reduced dopant fluctuation


Non PlanarNon Planar MOSFETs

UC Berkeley

Gate

Source Drain

Intel

Tri Gate FET

SourceSource DrainDrain

GateGate

SiO2

Channel

Double Gate FinFETVertical FET

Stanford, AT&T

17


Transport: Effects of Biaxial Tensile Strain on Si Energy BandsHoyt, 2002

Conduction BandAdditional splitting:Band repopulation

- reduced intervalley scattering- smaller in-plane effective transport mass

Δ2

Δ4

[001]

[010]

[100]

Δ Es ~ 67 meV/ 10% Ge

Δ4

Δ2

Δ6Ec

Bulk Si Strained Si

µ = q!

m*c

Strained Si grown on Relaxed Si1-xGex

biaxial tension

HH

LH

Spin-Orbit

E EValence Band

HH/LH degeneracy lifted at Γ

- reduced interband scattering- smaller in-plane transport mass due to band deformation

Γ

Bulk Si Strained Si

in-planeout-of-plane

kk

Δ Es ~ 40meV/10% Ge

ml

mtmt

mt < ml

Single ellipsoid


Strained Si gate oxide

Si Substrate

Relaxed Si1-xGex

n+ poly LTOspacer

n+ n+

Si1-xGex Graded layer

0.80

1.0

1.2

1.4

1.6

1.8

2.0

0.0 0.10 0.20 0.30 0.40

Mobility enhancement ratio

Substrate Ge fraction, x

VDS

= 10 mV

300 K

Measured, J. Welser, et al.,

IEDM 1994.

Calculated for strained Si

MOS inversion layer

S. Takagi, et al., J. Appl. Phys. 80, 1996.Mob

ility

Enh

ance

men

t Fac

tor

NMOS

Mobility Enhancements in Strained-Si MOSFETs

Intel

PMOS

Gibbons Group, Stanford

18


Nanowire and Nanowire and Nanotube FETsNanotube FETsALD HfO2 Coated of Ge NW FET

sourcegate

drain

dielectric

semiconductor

~20nmmetal

~10nm

Channel

Au

Nanoparticle

GeContaining

Vapor

Ge Nanowire

Ge NW Growth

Key Challenge: Controlled growthCatalyst Support

CnHmCnHm Fe

Gate

HfO2

10 nm SiO2

p++ Si

SD

Carbob Nanotube MOSFETCarbob Nanotube Growth


B

+ =

Spintronics

Seemingly Useful Devices

Limited Current DriveCryogenic operation

Limited Fan-OutCritical dimension control

Need high spin injectionand long spin coherence time Limited thermal stability

New architectures needed

~ 2 nm

Challenging fabricationand process integration

CarbonNanotubes

Controlled growth

19


• In general this device scaling methodologydoes not take into account many other chipperformance and reliability issues, e.g.,interconnects, contacts, isolation, etc.

• These factors are now becoming an obstaclein the evolution of integrated circuits.


Device Isolation pitch as a function ofminimum dimension

With decreasing feature size the requirement onallowed isolation area becomes stringent.

0.0 0.2 0.4 0.6 0.8 1.0Minimum dimension [µm]

0.0

0.5

1.0

1.5

2.0

2.5

16M

64M

1G

P. Fazan, Micron, IEDM-93

Activ

e Ar

ea p

itch

(µm

)

20


Scaling of Device Isolation

NitridePad oxide

Fully recessed LOCOS

Nitride Pad oxide

Semi-recessed LOCOSNitride

Field oxide

After field oxidation

After field oxidation

LOCOS based isolation technologies have serious problemsin loss of area due to bird’s beak.

Deep trench isolation

N-wellP-substrate

Shallow trench isolation

Trench isolation can minimize area loss


Scaling of interconnections

OldNew (scaled)

• Bigger chip => longer interconnects• Scaling to smaller dimensions => reduced cross section• Larger R, L and C

21


Interconnect Delay Is Increasing

• Chip size is continuallyincreasing due toincreasing complexity– Increase in R, L and C

• Device performance isimproving but interconnectdelay is increasing

• Need better materials– Metal with lower resistivity– Dielectrics with lower K– Other solutions, e.g., 3D,

optical interconnects

60 80 100 120 140 160 18010-2

10-1

100

101

Technology Node (nm)D

elay

Tim

e (n

s) Longest Interconnect Delay

Typical Gate Delay

scaling


1970’s Poly-Si gateAluminum

1980’s Aluminum alloysSilicide contactsPolycide gatesLocal planarization

1990’s Layerd aluminum/titanium SalicidesCVD tungsten plugsShallow trench isolationGlobal planarization

Advances in Backend Technology

22


Current Interconnect Technologies

Copper 6

Copper 1

TungstenLocal Interconnect

Copper 3

Copper 5

Copper 4

Copper 2

Current Al technology(Courtesy of Motorola)

Current Cu technology(Courtesy of IBM)


1

2

3

4

5

6

7

8

9

10

11

12

13

14

Al & SiO2 (! = 4)

Cu & SiO2 (! = 4)

Al & low-! (! = 2)

Cu & lo w-! ( ! = 2)

0.092007

0.132004

0.182001

0.251998

0.351995

Tec hnology Generation

µmYear

Why Cu and Low-k Dielectrics?

Reduced resistivity and dielectric constant results in reduction in number ofmetal layers as more wires can by placed in lower levels of metal layers.

global

semiglobal

local

Source: Y.Nishi

23


Cu Resistivity: Effect of Line Width Scaling• Effect of Cu diffusion Barrier

• Barriers have higher resistivity• Barriers can’t be scaled below a minimum thickness

• Effect of Electron Scattering• Reduced mobility as dimensions decrease

• Effect of Higher Frequencies• Carriers confined to outer skin increasing resistivity

Problem is worse than anticipated in the ITRS 1999 roadmap


Problems in Scaling of Interconnections

Pure Metal Interconnect

Layered Interconnect

Surrounded Interconnect

Al

Al

Cu

ρav

Minimum Feature Size (λ)

• Resistivity increases asgrain size decreases

• Resistivity increases asmain conductor sizedecreases but not thesurroundingbarrier size

AS λ DECREASESBarrier

Barrier

Cu

24


3-D Integration: Motivation

• Integration of heterogeneous technologiespossible, e.g., memory & logic, optical I/O

• Reduce Chip footprint• Replace long horizontal wires by short

vertical wires• Interconnect length ⇓ and therefore R, L, C ⇓

– Power reduction– Delay reduction

2-D System 3-D System

Wire-length

Num

ber o

f Int

erco

nnec

ts

(Log-Log Plot)2-D IC3-D IC

Area = A

Very Long Wire

Shorter Wire

2D

3D

A/2

A/2


3-D Motivation: Integration Density

Time

No.

Tra

nsis

tors

/chi

p //

Perf/

Func

tiona

lity

No.

Tra

nsis

tors

per

cm

3 in

sys

tem

12-15 years

The Best Integrators of Electronic Devices Will Own theHeart of Every System – We have <15 Years to Figure it out

2-D Batch

3-D Packaging

3D batch

End-of-Moore’sLaw!

Source: D. Radack, DARPA

Logicn+/p+

n+/p+ n+/p+

Gate

Gate

T1

T2

M1

M2

M3

M4

n+/p+n+/p+

GateRepeaters oroptical I/O devices

n+/p+

M’1

M’2

MemoryorAnalog

25


Can Optical Interconnects help?40Tb/s Optical I/O1024 x OC-768100Tb/s On-ChipBisection BWPMM64 Tiles64b Processor+ 4MB DRAMOn-Chip Optical Interconnects

Chip-to-chip Optical Interconnects

Can potentially address many problems ofCu/low-k wires

On-Chip LinksReduce delay

Clocking and SynchronizationReduce jitter and skew

High Bandwidth off-chip Links Reduce power


Result: scaling of power components

Power increasingly becoming the performance bottleneck for high-endmicroprocessors

• Dynamic Power: CV2f• Leakage power: devices• Short circuit power during switching• Static power, e.g., analog components (sense amps etc.)

ITRS projections for totalpower dissipation on chip

Chandra, Kapur and Saraswat,IEEE IITC, June 2002

26


• Thermal conductivity of low-k insulators is poor

• Thermal impedance increases

• Energy dissipated (CV2f) is increasing as performance improves• Average chip temperature is rising

Thermal Behavior in ICs

Source: ITRS

3550 70 130 180100

0

1

2

3

4

0

0.2

0.4

0.6

0.8

1

1.2

Technology Node [nm]

Die

lect

ric C

onst

ant Therm

al Conductivity [

W / m

K ]

35 50 70 100 130 180

0

5

10

15

20

25

30

0

1

2

3

4

5

Pow

er D

ensi

ty [

W /

cm2

]

Technology Node [nm]

Jm

ax [ MA

/ cm2 ]


>100A will flow on these wires

The problems Caused by Increased Power

As T ⇑ R ⇑, RC delay ⇑10°C ⇑ , Speed ⇓ 5%

PERFORMANCE

RELIABILITY

10°C ⇑ , MTF ⇓ 50%

!

MTF =A

rmJnexp

Ea

kT

"

# $

%

& '

Mean time to failure

Electromigration induced hillocks and voids

Hillock VoidMetal

MetalDielectric

27


Source Drain

Gate

Time

Conclusion: Technology ProgressionBulk CMOS

Si0.8Ge0.2

Si

Si

(tensile)

Si1-xGex

Strained Si

High k gate dielectric

Metal gate

3D ICs

2 nm

Cu interconnect

Low-k ILD

FD SOI CMOS

Optical interconnect

Molecular device

Detectors, lasers,modulators, waveguides

Spin device

B

+ =

Ge on Si hetroepitaxy

Ge on Insulator

Wafer bondingCrystallization

Nanowires

Ge/Si Heterostrcture

Double-Gate CMOS

Nanowire

Single etransistor

Nanotube

Feature Size


MOS Transistor in 2010 A Circuit in 2010 A Factory in 2010

Gate oxide thickness < 1nm Channel Length < 2nmJunction depth < 1-2nmSize of an atom ~ 5 Å

1010 components Integrated digital, analog, sensors

Approaching $10 billion

Summary

Questions we are trying to answer• How can we continue the Moore’s law• What will be new materials, devices, circuits, sensors,

equipment, simulators, etc.• How will we design them?• How will we manufacture them?

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