transistors and logic gates - memory & storage...
TRANSCRIPT
Chapter 3Digital LogicStructures
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-2
Basics
Switch open:• No current through circuit• Light is off• Vout is +2.9V
Switch closed:• Short circuit across switch• Current flows• Light is on• Vout is 0V
Switch-based circuits can easily represent two states:on/off, open/closed, voltage/no voltage.
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-3
Digital symbols:• recall that we assign a range of analog voltages to each
digital (logic) symbol
• assignment of voltage ranges depends on electrical properties of transistors being used
typical values for "1": +5V, +3.3V, +2.9V, …from now on we'll use +2.9V
What is semiconductor ( 반도체 )?
• 도체 (conductor), 부도체 (insulator), 반도체 (semiconductor)
• Dr. Walter Brattain on Semiconductor Physicshttps://www.youtube.com/watch?v=EWZsnLvL400
Semiconductor: Silicon
Conceptually…. In Reality….
n-type and p-type Semiconductor
n-type semiconductor p-type semiconductor
P-N Junction Diode
depletion region
Reverse biased Forward biased
Source: http://www.electronics-tutorials.ws/diode/diode_2.htmlhttp://www.electronics-tutorials.ws/diode/diode_3.html
BJT(Bipolar Junction Transistor)
N-P-N Transistor
Emitter (E) Base (B) Collector (C)
Source: https://qph.ec.quoracdn.net/main-qimg-9b58be1f7188ec19810ca02284ee111c
MOS(Metal-Oxide-Silicon) Transistor: n-type
P P
G=0 G=1
n-type transistor as a switch
Keep it simple"Perfection is achieved not when there is nothing
more to add, but when there is nothing left to take away"
Antoine de Saint-Exupery
BJT
MOS Transistor
Source http://gumho.img3.kr/radio/52sanyosf-78green/sanyosf-78green-3.jpghttp://techreport.com/r.x/core-i7/die-callout.jpg
노벨상도 실수를 한다 ?• 1956 년 Nobel Prize in Physics
• William Bradford Shockley, John Bardeen, and Walter Houser Brattain
• “for their researches on semiconductors and their discovery of the transistor effect”
• The field-effect transistor (a predecessor of the MOS transistor) was first patented by Julius Edgar Lilienfeld in 1926
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-12
n-type MOS Transistor• when Gate has positive voltage,
short circuit between #1 and #2(switch closed)
• when Gate has zero voltage,open circuit between #1 and #2(switch open)
Gate = 1
Gate = 0
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-13
p-type MOS Transistorp-type is complementary to n-type
• when Gate has positive voltage,open circuit between #1 and #2(switch open)
• when Gate has zero voltage,short circuit between #1 and #2(switch closed)
Gate = 1
Gate = 0
Primitive (CMOS) Gate: Inverter (NOT) gate
In Out
0 1
01
In Out +V
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-15
CMOS CircuitComplementary MOSUses both n-type and p-type MOS transistors
• p-typeAttached to + voltagePulls output voltage UP when output is one
• n-typeAttached to GNDPulls output voltage DOWN when output is
zero
For all inputs, make sure that output is either connected to GND or to +,but not both!
(GND)
(+V)
Source: https://3.bp.blogspot.com/-Yfr5bIYOGJc/VtMoo9Y8BoI/AAAAAAAAAF8/POvHrRll9RM/s1600/CMOSBD.png
Primitive Gate: NAND gate
A B
0 0
10
01
11
Out
Primitive Gate: AND gate
A B
0 0
10
01
11
Out
Composition!!
Primitive Gate: NOR gate
C D
0 0
10
01
11
Out
Duality!!
Primitive Gate: OR gate
C D
0 0
10
01
11
Out
Analogy!!
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-20
Basic Logic Gates
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-21
DeMorgan's LawConverting AND to OR (with some help from NOT)Consider the following gate:
A B0 0 1 1 1 00 1 1 0 0 1
1 0 0 1 0 1
1 1 0 0 0 1
BA BA BA
Same as A+B, thus A+B =
Alternatively,
Source http://www.learnabout-electronics.org/Digital/dig23.php
3-22
Additional Laws
•Operations with 0 and 1• A ∙ 1 = A• A + 0 = A
• A ∙ 0 = 0• A + 1 = 1
•Idempotent theorem• A ∙ A = A• A + A = A
Source http://www.learnabout-electronics.org/Digital/dig23.php
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-23
More than 2 Inputs?AND/OR can take any number of inputs.
• AND = 1 if all inputs are 1.• OR = 1 if any input is 1.• Similar for NAND/NOR.
Can implement with multiple two-input gates,or with single CMOS circuit.
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-24
Building Functions from Logic GatesCombinational Logic Circuit
• output depends only on the current inputs• stateless
Sequential Logic Circuit• output depends on the sequence of inputs (past and present)• stores information (state) from past inputs
We'll first look at some useful combinational circuits,then show how to use sequential circuits to store information.
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-25
Decodern inputs, 2n outputs
• exactly one output is 1 for each possible input pattern
2-bitdecoder
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-26
Multiplexer (MUX)n-bit selector and 2n inputs, one output
• output equals one of the inputs, depending on selector
4-to-1 MUX
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-27
Full AdderAdd two bits and carry-in,produce one-bit sum and carry-out. A B Cin S Cout
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-28
Four-bit Adder
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-29
Logical CompletenessCan implement ANY truth table with AND, OR, NOT.
A B C D0 0 0 00 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
1. AND combinations that yield a "1" in the truth table.
2. OR the resultsof the AND gates.
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-30
Combinational vs. SequentialCombinational Circuit
• always gives the same output for a given set of inputsex: adder always generates sum and carry,
regardless of previous inputsSequential Circuit
• stores information• output depends on stored information (state) plus input
so a given input might produce different outputs,depending on the stored information
• example: ticket counteradvances when you push the buttonoutput depends on previous state
• useful for building “memory” elements and “state machines”
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-31
R-S Latch: Simple Storage Element
To reset, R = 0, S = 1 (“Active Low” logic – “0” means active)
Output changes to zero.
1
0
1
0
0
0
1
1
R changes to zero
1
0
1
0
?
?
?
?
R is used to “reset” or “clear” the elementS is used to “set” the element
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-32
R-S Latch: Simple Storage Element
Output changes to one.0
1
1
1
0
0
S changes to zero0
1
?
?
?
?
To set, R = 1, S = 0 (Again, “Active Low” logic)
R is used to “reset” or “clear” the elementS is used to “set” the element
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-33
R-S Latch: Simple Storage Element
If R = S = 1, • “quiescent” state -- holds its previous value• note: if a is 1, b is 0, and vice versa
1
0
1
1
1
1
0
0
1
1
0
0
1
1
R is used to “reset” or “clear” the elementS is used to “set” the element
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-34
R-S Latch (active low) SummaryR = 0, S = 1
• set value to 0S = 0, R=1
• set value to 1R = S = 1
• hold the current value in latch
R = S = 0• both outputs equal one• final state determined by electrical properties of gates• Don’t do it!
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-35
Gated D-LatchTwo inputs: D (data) and WE (write enable)
• when WE = 1, latch is set to value of DS = NOT(D), R = D
• when WE = 0, latch holds the previous valueS = R = 1
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-36
RegisterA register stores a multi-bit value.
• We use a collection of D-latches, all controlled by a common WE.
• When WE=1, n-bit value D is written to register.
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-37
Representing Multi-bit ValuesNumber bits from right (0) to left (n-1)
• just a convention -- could be left to right, but must be consistentUse brackets to denote range:D[l:r] denotes bit l to bit r, from left to right
May also see A<14:9>, especially in hardware block diagrams.
A = 0101001101010101
A[2:0] = 101A[14:9] = 101001
015
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-38
MemoryNow that we know how to store bits,we can build a memory – a logical k × m array of stored bits.
•••
k = 2n
locations
m bits
Address Space:number of locations(usually a power of 2)
Addressability:number of bits per location(e.g., byte-addressable)
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-39
22 x 3 Memory
addressdecoder
word select word WEaddress
writeenable
input bits
output bits
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-40
More Memory DetailsThis is a not the way actual memory is implemented.
• fewer transistors, much more dense, relies on electrical properties
But the logical structure is very similar.• address decoder• word select line• word write enable
Two basic kinds of RAM (Random Access Memory)Static RAM (SRAM)
• fast, maintains data as long as power appliedDynamic RAM (DRAM)
• slower but denser, bit storage decays – must be periodically refreshed
Also, non-volatile memories: ROM, PROM, flash, …
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-41
State MachineAnother type of sequential circuit
• Combines combinational logic with storage• “Remembers” state, and changes output (and state)
based on inputs and current state
State Machine
CombinationalLogic Circuit
StorageElements
Inputs Outputs
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-42
Combinational vs. SequentialTwo types of “combination” locks
4 1 8 4
30
15
5
1020
25
CombinationalSuccess depends only onthe values, not the order in which they are set.
SequentialSuccess depends onthe sequence of values(e.g, R-13, L-22, R-3).
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-43
StateThe state of a system is a snapshot ofall the relevant elements of the systemat the moment the snapshot is taken.
Examples:• The state of a basketball game can be represented by
the scoreboard.Number of points, time remaining, possession, etc.
• The state of a go game ( 바둑 ) can be represented bythe placement of ’s and ’s on the board.
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-44
State of Sequential LockOur lock example has four different states,labelled A-D:
A: The lock is not open,and no relevant operations have been performed.
B: The lock is not open,and the user has completed the R-13 operation.
C: The lock is not open,and the user has completed R-13, followed by L-22.
D: The lock is open.
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-45
State DiagramShows states and actions that cause a transition between states.
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-46
Finite State MachineA description of a system with the following components:
1. A finite number of states2. A finite number of external inputs3. A finite number of external outputs4. An explicit specification of all state transitions5. An explicit specification of what determines each
external output value
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-47
The ClockFrequently, a clock circuit triggers transition fromone state to the next.
At the beginning of each clock cycle,state machine makes a transition,based on the current state and the external inputs.
“1”“0”
timeOneCycle
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-48
Implementing a Finite State MachineCombinational logic
• Determine outputs and next state.Sequential logic: Storage elements
• Maintain state representation.
State Machine
CombinationalLogic Circuit
StorageElements
Inputs Outputs
Clock
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-49
Storage: Master-Slave FlipflopA pair of gated D-latches, to isolate next state from current state.
During 1st phase (clock=1),previously-computed statebecomes current state and issent to the logic circuit.
During 2nd phase (clock=0),next state, computed bylogic circuit, is stored inLatch A.
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-50
StorageEach master-slave flipflop stores one state bit.
The number of storage elements (flipflops) neededis determined by log (number of states)
Examples:• Sequential lock
Four states – two bits • Basketball scoreboard
7 bits for each score, 5 bits for minutes, 6 bits for seconds,1 bit for possession arrow, 1 bit for half, …
2
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-51
Complete ExampleA blinking traffic sign
• No lights on• 1 & 2 on• 1, 2, 3, & 4 on• 1, 2, 3, 4, & 5 on• (repeat as long as switch
is turned on)
DANGERMOVERIGHT
1
2
34
5
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-52
Traffic Sign State Diagram
State bit S1 State bit S0
Switch onSwitch off
Outputs
Transition on each clock cycle.
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-53
Traffic Sign Truth Tables
Outputs(depend only on state: S1S0)
S1 S0 Z Y X
0 0 0 0 0
0 1 1 0 0
1 0 1 1 0
1 1 1 1 1
Lights 1 and 2
Lights 3 and 4
Light 5
Next State: S1’S0’(depend on state and input)
In S1 S0 S1’ S0’
0 X X 0 01 0 0 0 11 0 1 1 01 1 0 1 11 1 1 0 0
Switch
Whenever In=0, next state is 00.
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-54
Traffic Sign Logic
Master-slaveflipflop
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
3-55
LC-3 Data Path
CombinationalLogic
State Machine
Storage
GateMDR
꼭 기억해야 할 것• Levels of abstraction• MOS Transistor / CMOS circuits• Importance of simplicity
• CMOS gates• Inverter• NAND, AND• NOR, OR
• Circuits• Combinational circuits• Sequential circuits• Finite State Machine