transformational iii-v electronics thesis

8/10/2019 Transformational III-V Electronics Thesis

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Transformational III-V Electronics

Thesis by

Maha Nour

In Partial Fulfillment of the Requirements

For the Degree of

Master of Science

King Abdullah University of Science and Technology

Thuwal, Kingdom of Saudi Arabia

April 30, 2014


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EXAMINATION COMMITTEE APPROVALS FORM

The thesis of Maha Nour is approved by the examination committee.

Committee Chairperson [Muhammad Mustafa Hussain]

Committee Co-Chair [Mohamed-Slim Alouini ]

Committee Member [Zhiping Lai]


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Approval Date

Maha Nour

All Rights Reserved


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ABSTRACT

Transformational III-V Electronics

Maha Nour

Flexible electronics using III-V materials for nano-electronics with high electron mobility

and optoelectronics with direct band gap are attractive for many applications. This thesis

describes a complementary metal oxide semiconductor (CMOS) compatible process for

transforming traditional III-V materials based electronics into flexible one. The thesis

reports releasing 200 nm of Gallium Arsenide (GaAs) from 200 nm GaAs / 300 nm

Aluminum Arsenide (AlAs) stack on GaAs substrate using diluted hydrofluoric acid (HF).

This process enables releasing a single top layer compared to peeling off all layers with

small sizes at the same time. This is done utilizing a network of release holes that

contributes to the better transparency (45 % at 724 nm wavelengths) observed.

Fabrication of metal oxide semiconductor capacitor (MOSCAPs) on GaAs is followed by

releasing it to have devices on flexible 200 nm GaAs. Similarly, flexible GaSb and InP

fabrication process is also reported to transform traditional electronics into large-area

flexible electronics.


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ACKNOWLEDGMENT

There are many people to whom I feel significantly grateful for their unlimited support

and without their help this thesis would not have been possible. In first place, I owe my

sincere appreciativeness to Dr. Muhammad M. Hussain, for giving me the opportunity to

work under his supervision and for his constant guide.

I would like also to thank my group members for their continuous support. This work

could not have been completed without their truthful recommends and assist. Also, I

would like to thank Mr. Ahad Syed form the nanofabrication lab for his guide.

I would like to expand my thanks to the committee members Dr. Mohamed-Slim Alouini

and Dr. Zhiping Lai for taking out the time to attend my defense and to review my thesis.

Finally, I would like to thank my parents, family and my husband and friends for their

support and motivation throughout my masters.


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TABLE OF CONTENTS

ABSTRACT ........................................................................................................................ 4

ACKNOWLEDGMENT..................................................................................................... 5TABLE OF CONTENTS .................................................................................................... 6

LIST OF ABBREVIATIONS ............................................................................................. 7

LIST OF ILLUSTRATIONS .............................................................................................. 8

LIST OF TABLES ............................................................................................................ 10

1 CHAPTER 1: Introduction ......................................................................................... 11

1.1 Flexible electronics ............................................................................................... 12

2 CHAPTER 2: Experimental Setup For Transformational III-V Electronics .............. 15

2.1 Flexible GaAs Electronics .................................................................................... 15

2.1.1 Design GaAs flexible Substrate ..................................................................... 15

2.1.2 Flexible process for GaAs Substrate .............................................................. 18

2.1.3 Design MOSCAP on Flexible GaAs .............................................................. 27

2.1.4 Fabrication for flexible GaAs MOSCAP ....................................................... 32

2.2 Flexible InP and GaSb .......................................................................................... 39

2.2.1 Design Flexible Inp Substrate and Gasb Substrate ........................................ 39

2.2.2 InP Flexible Substrate Fabrication Process .................................................... 44

2.2.3 GaSb Flexible Substrate Fabrication Process ................................................. 50

3 CHAPTER 3:Discussion and Results ........................................................................ 543.1 GaAs Flexible Substrate ....................................................................................... 54

3.2 MOSCAP on Flexible GaAs ................................................................................. 56

3.3 InP and GaSb Substrates ....................................................................................... 59

3.4 Future Work .......................................................................................................... 59

4 CHAPTER 4: Conclusion ........................................................................................... 60


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LIST OF ABBREVIATIONS

AFM Atomic Force MicroscopyAl Aluminum

Al2O3 Aluminum oxide

AlAs Aluminum Arsenide

ALD Atomic layer Deposition

AlInGaP Aluminum Indium Gallium Phosphide

DI water Deionized water

DRIE Deep Reactive Ion Etching

EPI Epitaxial

GaAs Gallium Arsenide

GaN Gallium NitrideGaSb Gallium antimonite

HCl Hydrochloric acid

HF Hydrofluoric acid

InAs Indium Arsenide

InP Indium phosphide

LEDs Light emitting diodes

MOSCAP Metaloxidesemiconductor capacitor

MOSFET Metaloxidesemiconductor field-effect transistor

PDMS Polydimethylsiloxane

PR Photoresist

RIE Reactive ion etching

SEM Scanning Electron Microscopy

Si Silicon

TaN Tantalum Nitride

Te Tellurium

XeF2 Xenon difluoride

XRD X-Ray Diffraction


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LIST OF ILLUSTRATIONS

FIGURE 1.1:RELEASE MULTILAYERS OF GAAS [9] .......................................................... 13FIGURE 1.2:FABRICATION PROCESS FLOW FOR RELEASING SILICON PIECES FROM MONO-CRYSTALLINE SILICON WAFER [13]. ............................................................................ 14

FIGURE 2.1:HOLES SEPARATIONS AND DIAMETERS........................................................... 16FIGURE 2.2:ETCHING RATE FOR ALXGA1-XAS WITH DIFFERENT HFCONCENTRATIONS

[14]............................................................................................................................. 16FIGURE 2.3:SEVEN REPETITIONS OF 200NM GAAS /300NM ALAS ON GAAS SUBSTRATE18

FIGURE 2.4:DEPOSIT 4!"PHOTORESIST.......................................................................... 19FIGURE 2.5:DEVELOP PHOTORESIST FOR 60SECONDS....................................................... 19

FIGURE 2.6:SEMIMAGE FOR RIEFIRST TRAIL SHOWS 500NM ETCH AND NO PRANYMORE................................................................................................................................... 20

FIGURE

2.7:

SEMIMAGE FOR

RIESECOND TRAIL SHOWS BARLEY ETCHED

GA

AS

............. 21FIGURE 2.8: SEMIMAGE FOR RIETHIRD TRAIL:ETCH 2600NM IN 1MIN AND 45SECONDS

(1486NM/MIN) ........................................................................................................... 22FIGURE 2.9:SEMIMAGE FOR RIEFOURTH TRAIL:ETCH 570NM IN 1MIN......................... 22

FIGURE 2.10:SEMIMAGE FOR THE FIRST LAYER OF GAAS IS ETCHED............................... 23FIGURE 2.11:ZOOM IN TO FIND 290NM ETCHED................................................................ 24

FIGURE 2.12:HFETCHES ALAS TO PEEL OFF THE FIRST LAYER OF GAAS.......................... 24FIGURE 2.13:SEMIMAGE FOR 4%HFDILUTED ATTACKING ALAS AFTER 52SECOND..... 25

FIGURE 2.14:RELEASING THE FIRST LAYER BY USING PDMS ............................................ 26FIGURE 2.15:PEELED OFF GAAS ON PHOTORESISTS ON PDMS ......................................... 26

FIGURE 2.16:SIGE MOSCAPON SI WAFER [15] ............................................................... 27FIGURE 2.17:SUBSTRATE CONTACT FOR MOSCAPON TOP INSTEAD OF BACKCONTACT [10]

................................................................................................................................... 29FIGURE 2.18:(A)MASK DESIGN FOR THE GATE HOLES.(B)MASK DESIGN FOR RELEASING

HOLES. ........................................................................................................................ 30

FIGURE 2.19:THE TOP CONTACT HAS 100!M WIDTH SEPARATED BY 5!M FROM THE GATE.

THE RED CIRCLES REPRESENTS THE RELEASING MASK ITS CENTERED IN THE MIDDLE OF

GATE HOLES AND SEPARATED BY 2.5!M. ................................................................... 30

FIGURE 2.20:1CM X1CM MASK........................................................................................ 31

FIGURE 2.21:DEPOSIT 10NM AL2O3USING ALD .............................................................. 32FIGURE 2.22: DEPOSIT 20NM TANUSING ALD ............................................................... 33

FIGURE 2.23:DEPOSIT 200NM AL FOR GATE CONTACT USING SPUTTERING...................... 33FIGURE 2.24:PHOTORESISTS.............................................................................................. 34

FIGURE 2.25:DEVELOP PRAND ETCH GATE STACK USING RIE. ........................................ 34FIGURE 2.26:STRIP PR. ..................................................................................................... 34

FIGURE 2.27:LIFT-OFF TI/AU............................................................................................ 35FIGURE 2.28:DEVELOP PHOTORESIST................................................................................ 36

FIGURE 2.29: ETCH 200NM OF GAAS AND 90NM OF ALAS USING RIE .......................... 36FIGURE 2.30: HFTO ETCH ALAS TO RELEASE 200NM OF GAAS..................................... 37

FIGURE 2.31:STRIP PR ...................................................................................................... 37


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FIGURE 2.32:FIRST TRANSFER USING PDMS ..................................................................... 38

FIGURE 2.33:USING ALUMINUM TAPE FOR THE SECOND TRANSFER.................................. 38FIGURE 2.34:COMPLETE DOUBLE TRANSFER USING ALUMINUM TAPE............................... 38

FIGURE 2.35: 200NM OF GAAS TRANSFERRED FROM PDMSTO ALUMINUM TAPE........... 38

FIGURE 2.36: III-VSUBSTRATE WAFER............................................................................. 39FIGURE 2.37: GROW AN OXIDE AS A PROTECTION LAYER SELECTIVE TO ISOTROPICETCHANT. ................................................................................................................... 40

FIGURE 2.38: SPIN PR ....................................................................................................... 40FIGURE 2.39: EXPOSE AND DEVELOP PRUSING HOLES MASK............................................ 40

FIGURE 2.40: ETCH THE OXIDE USING RIE ........................................................................ 40

FIGURE 2.41:ETCH THE III-VMATERIAL USING RIETO 10!"OR MORE.......................... 40

FIGURE 2.42: STRIP THE RESIST......................................................................................... 41FIGURE 2.43: PROTECT THE SIDE WALLS WITH A SELECTIVE MATERIAL TO ISOTROPIC

ETCHANT.................................................................................................................... 41FIGURE 2.44: RIEETCHING FOR BOTTOM CLEANING......................................................... 41

FIGURE

2.45:

ISOTROPIC ETCHING

..................................................................................... 41FIGURE 2.46: PEAL-OFF FLEXIBLE III-VSUBSTRATE......................................................... 41

FIGURE 2.47: RELEASED III-VMATERIALS WITHOUT EPIPROCESS................................... 43FIGURE 2.48: FIRST INPRIETRAIL:NO ETCHING............................................................. 45

FIGURE 2.49: SECOND INPRIETRAIL :100NM /MIN........................................................ 45

FIGURE 2.50: THIRD INPRIETRAIL:1.5!"ETCH OF INPAND 450NM OF SINMASK...... 46

FIGURE 2.51: FOURTH INPRIETRAIL:12!"ETCH OF INPAND USING 4!"PRMASK AND

1!"SIO2MASK......................................................................................................... 47FIGURE 2.52:ANISOTROPIC WET ETCHING USING HCL:H2O(2:1)FOR 2MINUTES USING 1

!"SIO2MASK............................................................................................................ 47FIGURE 2.53:ISOTROPIC INPETCHING USING 25%HCLFOR 9MINUTES AT 60

OC ........... 49

FIGURE 2.54:FIRST GASB RIETRAIL :2.9!"ETCH OF GASB IN 2MINUTES. ................... 51FIGURE 2.55:SECOND GASB RIETRAIL :12!"ETCH OF GASB IN 11MINUTES. .............. 51

FIGURE 2.56:FIRST ISOTROPIC TRIAL:PROFILE FOR GASB ETCHED USING 1HCL:1H2O2:2

H2OFOR A MINUTE..................................................................................................... 53FIGURE 2.57:SECOND ISOTROPIC TRIAL: PROFILE FOR GASB ETCHED USING1HCL:1H2O2:

2H2OFOR TWO MINUTES........................................................................................... 53FIGURE 3.1:2CM X1CM GAAS WITH 200NM THICKNESS ON PDMS ............................... 54

FIGURE 3.3:AFMOF RELEASED GAAS ON PDMS ............................................................. 55FIGURE 3.4:TRANSPARENCY OF RELEASED 200NM GAAS ON PRON PDMSREACHED TO

45%AT 724NM WAVELENGTH. ................................................................................. 55FIGURE 3.5:XRDOF 200NM OF GAAS ON PHOTORESIST ON PDMS. ................................ 56

FIGURE 3.6:C-VGAAS MOSCAPS BEFORE RELEASING................................................... 57FIGURE 3.7:C-VAFTER RELEASING SHOWS BREAKDOWN EFFECT OF AL2O3. .................... 58

FIGURE 3.8:CHARACTERIZING RELEASED MOSCAPS ON ALUMINUM TAPE USING PROBE-STATION...................................................................................................................... 58


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LIST OF TABLES

TABLE 1.1:PROPERTIES OF III-VS VS SILICON................................................................. 12

TABLE 2.1:HFETCHING RATE........................................................................................... 17TABLE 2.2:GAAS RIERECIPIE.......................................................................................... 20

TABLE 2.3:GAAS RIETRIAL AND ERROR......................................................................... 23

TABLE 2.4:INPISOTROPIC ETCHING RATE USING HCL....................................................... 48


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1 CHAPTER 1: Introduction

III-V compound semiconductors have unique characteristics such as direct band gap and

high electron mobility. In contrast to Silicon (Si), that has indirect band gap and much

lower electron mobility. These characteristics make III-V compound semiconductors

mostly have better performance devices over Silicon and make it an attractive material

for many devices such light-emitting diodes (LEDs), lasers, solar cells and MOSFETs.

However, III-V compounds are quite expensive compared to Silicon. This is the main

reason why Silicon is the most used material in electronics although III-V materials

perform better. For some applications such as optoelectronics the direct band gap is

critically important feature for effective devices such as detectors, LEDs and lasers that

cant be replaced with Silicon. Other devices such as MOSFETs that mostly fabricated on

Silicon compromise in performance versus price. Although MOSFETs with III-V

material channels can switch faster than Silicon channels since electrons with higher

mobility cause higher velocities at lower electric fields. For example Gallium Arsenide

(GaAs ) has electron mobility almost six times higher than Silicon that contributes for

faster devices. The wider band gap allows the devices to operate in higher temperature.

The direct band gap, higher mobility, velocity, and conductivity of III-Vs developed

interest in these materials to replace Silicon.


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Lift-off thin film of III-Vs can be a solution for low cost, high performance devices. Lift-

off process allows to separate thin layer of IIIVs from their substrates to avoid the high

cost of IIIV materials by reusing the substrates several times. Releasing a thin layer of

III-V material is not only to minimize the cost but it also has a major advantage of

making flexible substrate due to the thin released layer.

1.1 Flexible electronics

Flexible electronics is one of the hottest topics nowadays. There are several studies done

on flexible electronics using different technics to release III-V materials such as Gallium

Nitride (GaN) [7, 8], GaAs [9, 10], Indium Arsenide (InAs) [11], Aluminum Indium

Gallium Phosphide ( AlInGaP) [12] and others. The main use technic is growing

epitaxial layers. One layer acts as a sacrificial material and one act as a thin film substrate

that is required to peel off. After the device fabrication, a selective etchant is used to etch

Electron Mobility Electron density Band gap

Material Cm /V.s Mass of theelectron(me)

eV

Si 1400 [1] 1.09 [2] 1.12[3]

GaAs 8500 [4] 0.067 [4] 1.42 [4]

GaSb 4000 [5] ---- 0.73 [6]

InP 4600 [4] 0.078 [4] 1.34 [4]

InSb 80000 [4] 0.0136 [4] 0.17 [4]

Table 1.1: Properties of III-Vs Vs Silicon


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the sacrificial layer and release the thin film. However, epitaxial growth use is the main

drawback for this technic since it is a costly method.

John A. Rogers were capable to released seven layers of GaAs by having epitaxial stack

of 200nm GaAs / 20 nm Aluminum Arsenide (AlAs) on GaAs substrate [9]. By placing

the stack in Hydrofluoric acid (HF) etchant, AlAs acts as a sacrificial layer due to etching

selectivity, where GaAs has lower etching rate by 106. The released GaAs layers were

transferred on another substrates and devices such as solar cells and MOSFETs, where

fabricated on them.

Flexible electronic studies where not restricted only in III-V materials but also on others

and mainly Silicon. There are several accomplishments were done on flexible Silicon.

However, our group has a unique methods for peeling off a porous thin layer of silicon

from the original Silicon substrate [13]. This technic is based on anisotropic and isotropic

Figure 1.1 : Release Multilayers of GaAs [9]


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etching as shown in Figure 1.2. It starts with oxide deposition on Si. Followed by

photoresist (PR) mask and reactive ion etching (RIE) to etch through the oxide and create

porous. After that the Silicon was etched using deep RIE process. Then an oxide was

grown to protect the silicon walls before starting the lateral etching. Using RIE the oxide

on the bottom trenches is etched keeping the sidewalls protected. Finally, using Xenon

difluoride(XeF2) as isotropic etchant for silicon where capable to create connected caves

and peel off Silicon porous thin layer.

Figure 1.2: Fabrication process flow for releasing silicon pieces from mono-

crystalline silicon wafer [13].


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2 CHAPTER 2: Experimental Setup For Transformational III-V Electronics

2.1 Flexible GaAs Electronics

2.1.1 Design GaAs flexible Substrate

The design was inspired from released GaAs stack for John A. Rogers [9] and the peeling

off a porous thin layer of silicon from the original Si for J.P. Rojas [13] to release layer

by layer of GaAs instead of peeling off all layers at a time. Which make it easer to

fabricate devices on rigid substrate rather than released substrate and speed up the

releasing process.

Epitaxial multilayers stack consists of seven repetitions of 200 nm of GaAs and 300 nm

of AlAs grown on GaAs substrate. The process starts by deposit a thick layer of

photoresists as a mask for GaAs etching and a supportive layer for 200 nm GaAs after the

release. Then lithography process takes a place to create holes in the photoresist. The

holes mask was designed to have 10 !m holes diameter and 5 !"constant separation

between holes as shown in Figure 2.1. Then, the first layer of GaAs was etched using

RIE. After that the wafer was placed in HF to release thin layer of GaAs and peel it off on

PDMS that acts as support layer.

A holes mask is required to peel off the GaAs layer. The maximum distance between two

holes is 11.2 !m. Thus to release the first layer, its required to etch 5.6 !m maximum.

However, when holes are connected horizontally and vertically the middle area has very

high etching rate since the etching occur from all around. However, based on Figure 2.2,


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shows HF etching rate for AlxGa1-xAs with different HF concentrations[14] where able to

calculate the required time for the lift-off process.

Figure 2.1: Holes separations and diameters

Figure 2.2: Etching rate for AlxGa1-xAs with different HF concentrations [14].


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Table 2.1, shows the required time for lift off process. 10% diluted HF is rejected since it

has very high etching rate. Therefore, either 4% or 2% diluted HF can be use.

HF ConcentrationEtching rate

(mm/h)

Etching rate

(!m /min)

lift-off Time

(to Etch 5 !m)

10 % 2.3 38 9 seconds

4 % 0.34 5.67 52 seconds

2 % 0.2 3.33 90 seconds

Table 2.1: HF etching rate


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2.1.2 Flexible process for GaAs Substrate

A fabrication process has been developed to release layer by layer of 200 nm GaAs using

a combination process of peeling of seven layers of GaAs at a time for John A. Rogers

[9] and peeling off a porous thin layer of silicon from the original Si for J.P. Rojas [13].

2.1.2.1 Substrate

Epitaxial multilayers stack consists of seven repetition of 200 nm n-type GaAs with

Silicon doped ( 5 X 10

17

cm

-3

) and 300 nm of AlAs grown on 2 inch Silicon doped

GaAs substrate wafer. The wafer was diced into 1 cm X 1 cm square pieces.

2.1.2.2 Lithography process

Deposit 4 !"photoresist using ECI 3027 at 1750 rpm spinspeed for 30 seconds. Then

the sample was baked for 60 seconds at 100OC. Then the sample was exposed to 200

mJ/cm2using holes mask. Then developed for 60 seconds using AZ 726. Finally rinsed

with deionized water (DI) and dried using N2.

Figure 2.3: seven repetitions of 200 nm GaAs / 300 nm AlAs on GaAs substrate


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Figure 2.4: Deposit 4 !"photoresist

Figure 2.5: Develop photoresist for 60 seconds

2.1.2.3 Reactive Ion Etching (RIE)

Oxford instruments were used to develop an RIE recipe to etch 200 nm of GaAs.

However, trail and error method was used to find the required recipe. The first trail was

done based on Stanford recipe to etch III-V [16]. The recipe starts by cleaning the

chamber but it was modified a little to match the tool capability.


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After the cleaning process the Stanford etching recipe run for 1 minutes and 34 seconds

to etch 200 nm GaAs based on the given etching rate, 130 nm/ minutes that includes 5

sccm BCl3, 5 sccm Cl2, 20 sccm Ar, 2 mTorr, 30W RF power and 250 W ICP power. The

first trail run and the sample was inside the chamber during the cleaning process. The O 2

in the cleaning process attacks all the photoresist and etched 500 nm from the stack.

Figure 2.6: SEM image for RIE first trail shows 500 nm etch and no PR anymore

Chamber cleaning recipe

Trail recipe Stanford recipe [16]

RF power (W) 70 70

ICP power (W) 2000 2000

Pressure (mTorr) 20 20

O2(sccm) 20 100

SF6(sccm) 20 100

Time (minutes) 10 10

Table 2.2: GaAs RIE recipie


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Therefore, in the second trail the cleaning chamber where done then the sample was

placed for 1 minutes and 45 seconds. In this trail the sample was not etched or barley

etched.

Figure 2.7: SEM image for RIE second trail shows barley etched GaAs

It was noticed that this tool was not capable to have 30 W DC power and during the first

minutes the DC power was zero then it starts to increase. Thus, in the third trail the DC

power was raised to 75 W, the ICP power to 1000 W and pressure to 10 mTorr. This

recipe was capable to etch but in very high etching rate, 1486 nm/min that mean 8

seconds are needed to etch 200 nm.


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Figure 2.8: SEM image for RIE third trail: Etch 2600 nm in 1min and 45 seconds

(1486 nm/min)

It is not possible to stabilize the tool for 8 seconds. Therefore, in the fourth trailer the

recipe was modified to decrease the etching rate. The recipe includes 15 sccm Cl2, 3 sccm

Ar, 5 mTorr, 50 W RF power and 300 W ICP power. The BCl3was removed since it is a

strong etchant. In this trail were capable to etch 570 nm/min.

Figure 2.9: SEM image for RIE fourth trail: Etch 570 nm in 1min


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In the fifth trail the same recipe was used but run for 22 seconds and it was capable to

etch 200 nm GaAs and a 90 nm AlAs. This was a suitable recipe since it attacks the first

GaAs without affecting the second layer of AlAs.

Figure 2.10: SEM image for the first layer of GaAs is etched

Trail Temperature PressureRF

DCICP Cl2 BCl3 Ar Time

Etching

depth

OC mTorr W W Sccm Sccm Sccm min sec nm

1 25 2 30 250 5 5 20 1 34 500

2 25 2 30 250 5 5 20 1 45 0

3 25 10 75 1000 10 10 10 1 45 2600

4 30 5 50 300 15 0 3 1 0 570

5 30 5 50 300 15 0 3 0 22 290

Table 2.3: GaAs RIE trial and Error


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Figure 2.11: Zoom in to find 290 nm etched

2.1.2.4 HF etchant

4% diluted HF was prepared using HF : H2O with 1:24 and the exact etching rate was

found by placing a dummy sample for 52 seconds. Using SEM the exact etching rate was

found to be 2.5 !m/min. Therefore the sample was placed in 4% HF etchant for 2

minutes. Then the sample was rinsed with DI water and dried using N2.

Figure 2.12: HF etches AlAs to peel off the first layer of GaAs


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Figure 2.13: SEM image for 4% HF diluted attacking AlAs after 52 second

2.1.2.5 PDMS

The Polydimethylsiloxane (PDMS) was used to peel off the GaAs since its an excellent

adhesion to many surfaces that help in lifting-off thin films. PDMS is prepared by curing

agent ratio 0.5: 5. Then it was mixed using steel stick. The mixture was poured onto a flat

wafer piece embedded in aluminum boat. Then the sample was placed in vacuum oven at

115OC and pump down. Leave it pumped to lowest pressure for few seconds until most

bubbles are gone. The oven was vented and this was repeated twice until no bubbles

anymore. Then the mixture was cured for 20 minutes. After that the PDMS was placed on

top of the sample and pressed on it. Then, it was removed to peel-off 200 nm GaAs toped

with 4 !m photoresist on top of it.


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Figure 2.14: Releasing the first layer by using PDMS

Figure 2.15: Peeled off GaAs on photoresists on PDMS


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2.1.3 Design MOSCAP on Flexible GaAs

The MOSCAP design was inherited from a design done by our group of metal gate

devices on flexible SiGe on bulk of silicon (100) by using trench-protect-release-reuse

based generic batch process to demonstrate mechanically flexible and optically semi-

transparent [15]. The same MOSCAP design that consists of 10 nm Al2O3as a high-k

gate dielectric and 20 nm TaN metal gate using atomic layer deposition (ALD) with 200

nm Al as a contact layer. Using the same MOSCAP but build it on GaAs layer on top of

AlAs allows us to have MOSCAP on flexible GaAs using the same concept of releasing

GaAs substrate in section 2.1.1.

To design MOSCAP on flexible GaAs there are several challenges should be taking into

consideration to design the process flow. First of all, while releasing the GaAs substrate

its required to have holes and use HF etchant but Aluminum (Al) and Aluminum oxide

Figure 2.16: SiGe MOSCAP on Si wafer [15]


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(Al2O3) are not selective to HF. Another challenge, is how to design the back contact

since there are 14 layer of epitaxial layers ( 200 nm GaAs /300 nm AlAs ). If the back

contact is going to be after the releasing then how to overcome the short circuit because

of the holes and how to have readings before and after releasing?

To solve the selectivity challenge a design was created to have a hole with 15 !m

diameter in the MOSCAP gate and smaller hole with 10 !m diameter for releasing that

centered in the middle of the larger hole. In this way the photoresist can protect the gate

metal and oxide from the HF since the PR is selective to HF. Therefore, its possible to

release the GaAs and etch the AlAs without compromising the high-k gate dielectric that

help to increase the gate capacitance and thus reduce current leakage which means better

performance.

To overcome the back contact issue, a solution was found in Epitaxial lift-off process for

Gallium Arsenide substrate reuse and flexible electronics [10]. Where in this paper the

GaAs layer was released first then the devices were created on top and top contact instead

of back contact for the substrate contact was used by having the metal contact as a frame

layer around the device as shown in Figure 2.17.


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(a) (b)

Figure 2.18: (a) Mask design for the gate holes. (b) Mask design for releasing holes.

Figure 2.19: The top contact has 100 !m width separated by 5 !m from the gate. The

red circles represents the releasing mask its centered in the middle of gate holes and

separated by 2.5 !m.


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Figure 2.20: 1cm X 1 cm mask


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2.1.4 Fabrication for flexible GaAs MOSCAP

2.1.4.1 Gate Stack deposition

This step consists of depositing Aluminum Oxide layer as the dielectric material with 10

nm thickness using Atomic Layer Deposition (ALD). ALD was chosen because its

extreme thickness controllability since it deposited layer by layer. The ALD deposition

was done in 100 cycles at 300OC and 15 mTorr. Each cycle consist of several steps.

Starting by exposure of the first precursor. Then purge to remove the non-reacted

precursors and the gaseous reaction by-products. After that, expose of the second

precursor. Finally, purge or evacuate of the reaction chamber.

After that, 20 nm of Tantalum Nitride (TaN) layer was deposited also using ALD on top

of Al2O3as gate metal using 200 cycles at 300OC and 15 mTorr.

Figure 2.21: Deposit 10 nm Al2O3 using ALD


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Figure 2.22: Deposit 20 nm TaN using ALD

2.1.4.2 Gate Contact Deposition

Aluminum (Al) layer with 200 nm thicknesses was deposited using sputtering tool as a

gate contact. It took 700 seconds to deposit 200 nm using 300 W DC bias at 5 mTorr.

Figure 2.23: Deposit 200 nm Al for gate contact using sputtering

2.1.4.3 Gate Pattern

ECI 3027 was used as a positive photoresists 1750 rpm to have 4 !m thickness. Then

baked for 1 minute at 100oC. A light field mask was used to pattern the gate starting by

Al layer. The photoresist is exposed to 200 mj/cm2and developed using AZ 726 for 60

seconds. 200 nm of Al was etched using Metal-RIE Oxford instruments with 40 sccm

Cl2, 10 sccm BCl3, 10 sccm Ar, 20 mTorr, 150 W DC power, 1500 W ICP power at 80oC


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for 60 seconds.After that, 20 nm of TaN and 10 nm of Al2O3were etched using 20 sccm

CHF3, 5 sccm Ar, 100 W DC , 1000 W ICP, 4 mTorr for 45 seconds, where the etching

rate is 40 nm/min for both Al2O3and the TaN. Then the resist was striped using acetone.

Finally the resist was striped using acetone.

Figure 2.24: Photoresists

Figure 2.25: Develop PR and etch gate stack using RIE.

Figure 2.26: Strip PR.


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2.1.4.4 Top Substrate Contact

Instead of having back contact for the substrate, top contact was used to be able to have

all contacts in one side since we are not able to use the back contact. Using Lift off

process the top substrate contact was placed. The process started by using ECI 3027 as a

positive photoresists 1750 rpm to have 4 !m thickness. Then baked for 1 minute at

100oC. A dark field mask was used and the photoresist was exposed to 200 mj/cm

2and

developed using AZ 726 for 60 seconds. Then, Titanium (Ti) and Gold (Au) were

deposited for the top contact using the sputtering tool. 20 nm of Ti was deposited first in

110 second using 400 W, 5 mTorr and 25 sccm of Ar. Then, 200 nm of Au was deposited

using the same conditions but for 250 seconds. After that, the sample was placed in

acetone to complete the lift-off process by removing the photoresist and all the metals

that on top of it.

Figure 2.27: Lift-off Ti/Au


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2.1.4.5 Releasing GaAs Substrate

A positive photoresist was used (ECI 3027) using 1750 rpm to have 4 !m thickness.

Then baked for 1 minute at 100oC. A dark field mask was used to pattern holes with 10

!m diameter inside the larger holes that has 15 !m diameter to act as a protection

material for Al and Al2O3from HF in the next step. The photoresist is exposed to 200

mj/cm2and developed using AZ 726 for 60 seconds. Then using Metal-RIE Oxford

instruments to etch 200 nm of GaAs and 90 nm of AlAs in 30 oC, 5mTorr, 50 W DC RF,

300 W ICP , 15 sccm Cl2and 3 sccm Ar. After that, the sample was placed in diluted HF.

Using HF: H2O with ratio 1:24 for 6 minutes since it has 2.5 !m/min etching rate and the

separation between holes is 15 !m. Finally the photoresist was striped using acetone.

Figure 2.28: Develop Photoresist

Figure 2.29: Etch 200 nm of GaAs and 90 nm of AlAs using RIE


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Figure 2.30: HF to etch AlAs to release 200 nm of GaAs

Figure 2.31: Strip PR

2.1.4.6 Double Transfer

The first transfer is done using the same PDMS recipe used in section 2.1.2.5. The second

transfer is done using Aluminum tape. This process was done on dummy sample first by

placing released 200 nm GaAs with no devices on PDMS and pressed gently. Then

remove from the PDMS to transfer the complete substrate to the tape. This method

worked smoothly and perfectly on 200 nm GaAs substrate. Therefore, it was repeated

with MOSCAPs on released on 200 nm GaAs.


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2.2 Flexible InP and GaSb

2.2.1 Design Flexible Inp Substrate and Gasb Substrate

Peeling of III-Vs were possible using sacrificial layer Epitaxial (EPI) deposition process.

However, EPI is an expensive process thus peeling of III-V material using a sacrificial

layer is not the best solution. Based on peeling off a porous thin layer of silicon from the

original Si [13] , a design was created to peel off thin layer of III-V material without the

need of EPI process specifically Indium phosphide (InP) and gallium antimonite (GaSb).

This design process for releasing a thing film of III-V without EPI process is simply

divided into two main steps. First step is having anisotropic etching using RIE with holes

mask. Second step is isotropic etching to peel off thin layer of III-V. This step requires a

sidewalls protection layer that is selective to the isotropic etchant mainly an oxide.

However, the main difference between peeling off Silicon or III-Vs is the RIE recipe for

isotropic, chosen etchants and the sidewalls protection materials based on the selectivity

between the materials. The process design flow for fabricating flexible III-Vs without

EPI process is shown from Figure 2.36 to Figure 2.46.

Figure 2.36: III-V substrate wafer


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Figure 2.37: Grow an oxide as a protection layer selective to isotropic etchant.

Figure 2.38: Spin PR

Figure 2.39: Expose and develop PR using holes mask

Figure 2.40: Etch the oxide using RIE

Figure 2.41: Etch the III-V material using RIE to 10 !"or more


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Figure 2.42: Strip the resist

Figure 2.43: Protect the side walls with a selective material to isotropic etchant

Figure 2.44: RIE etching for bottom cleaning

Figure 2.45: Isotropic etching

Figure 2.46: Peal-off flexible III-V substrate


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One mask is required to peel of a thin layer of III-Vs that consists of holes as shown in

Figure 2.1.Therefore, to peel off thin layer of III-Vs its required to create connected

caves using isotropic etching after the RIE and sidewalls protection. To design the

peeling of thickness layer with thickness its necessary to study the etching rate for depth

and lateral depth in isotropic etchant to know to calculate required anisotropic etching

depth using RIE. The required time to peel off a think later:

Peel-off Time =!

!"#$%"&!"#$%&'!"#$!! (1)

Where L is half the distance between holes (see Figure 2.47). However, during the

peeling-off time the etchant attack the material in the upward direction as well as the

downward direction.

H = Depth etching rate X Peel-off Time (2)

Where H is the etching height during releasing process. If it is required to peel of a layer

with thickness (T) then its necessary to etch isotropically with distance

D = T+H (3)

Where D is the etching depth using RIE, T is the releasing layer thickness and H is the

required horizontal etch to release the sample.


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Figure 2.47: Released III-V materials without EPI process


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2.2.2 InP Flexible Substrate Fabrication Process

2.2.2.1 InP Substrate

P-type two-inch InP wafer with origination (100) was ordered from Wafer Technology.

The InP wafer is Zinc doped with 1017cm-3. The wafer was diced into 5 mm X 5 mm.

2.2.2.2 InP Anisotropic

There was no recipe found for InP etching in micro-range using RIE that is capable to be

implemented in our lab using Metal-RIE Oxford instruments. Either the recipes required

gasses are not available in the tool such as CH4[17-19], N2[20, 21], H2 [18, 19] or the

recipe required temperature is not capable to reach where the tool maximum temperature

is 80oC and its required to reach 200

oC [22]. Therefore, RIE recipe was created based on

trail and error method. Since Metal-RIE Oxford instruments has only Cl2, HBr, BCl3, Ar

, O2and SF6, we are limited by our tool capability. PR was used as a mask then O2is not

recommended to be used, where O2 is not selective to PR. Therefore, the first trail was

implemented by choosing the gases that contributes to etch InP in other recipes.

Therefore, in the first trail HBr [23-25], BCl3[22, 26, 27] , Cl2[17, 21, 23, 27, 28] and Ar

[21, 22, 27, 28] were chosen with 10 , 5 , 10 , 5 sccm respectively at 25OC in 10 mTorr.


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Figure 2.48: First InP RIE trail: no etching

In the second trail, the same recipe was used in the first trail but the temperature in this

trial was increased to 80oC for 7 minutes. This recipe etched InP 700 nm with 100 nm /

min for InP and 0.36 !m /min for PR mask. Therefore to etch 10 !m it is required to etch

for 100 minutes, which mean it, is required to have 36 !m of PR. It is not possible to use

such a thick PR mask therefore another mask was used for the third trial.

Figure 2.49: Second InP RIE trail : 100 nm / min


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Figure 2.51: Fourth InP RIE trail: 12 !!etch of InP and using 4 !"PR mask and 1

!"SiO2mask

Also, wet etching using HCl base etchants are anisotropic for InP in room temperature

[10, 29, 30]. Thus, HCl: H2O (2:1) was used for anisotropic etching for 2 minutes to etch

3 !"of InP using 1 !"SiO2 mask.

Figure 2.52: Anisotropic wet etching using HCl: H2O (2:1) for 2 minutes using 1

!"SiO2 mask


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2.2.2.3 InP Isotropic Etching

InP etching usually has anisotropic profiles even using wet etching. HCl based chemicals

are well-known InP etching acid. It has anisotropic etching profile in room temperature.

However, two InP etchants were found for isotropic profiles at 60 OC, either HCl [10, 31]

or HCl : H3PO4 (1:9) etchant that has InP lateral etching up to 400 nm / minutes [31]. To

choose between these two etchant, the selectivity between materials and etchants were

studied. Al2O3 oxide was preferred to use as a protection oxide using ALD because of its

uniform deposition to PECVD based on our lab capability. A simple test was done by

growing 40 nm of Al2O3on Silicon wafer then a piece was placed in concentrated HCl

(37%) etchant at 60oC and another piece was placed in HCl : H3PO4 (1:9) at 60

oC for a

minute. It was found HCl : H3PO4 (1:9) at 60oC etched all 40 nm of Al2O3.On the other

hand the concentrated HCl has low etching rate to Al2O3reached to 0.75 nm/min at 60oC.

In concentrated HCl at 60oC the lateral etching rate is 5.9 mm/h [10]. The separation

between holes in our design is only 5 !m concentrated HCl etch it in 3 seconds and

manually this not an accurate process. Therefore, different concentration where tested at

60 oC to study the etching rate as shown in Table 2.4.

Concentration Lateral Etching rate Depth Etching rate

HCl : H2O % !m / min !m / min

1:50 2 Almost zero Almost zero3:50 5.7 Almost zero Almost zero

17:50 25 0.73 0.3

Table 2.4: InP isotropic etching rate using HCl


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25 % HCl is good enough to peel a thin layer of InP. Since the separation between holes

is 5 !m then the peeling time is 6 minutes and 50 seconds based on equation (1) in

section 2.2.1. The etching height during releasing process is 2 !m based on equation (2).

in section 2.2.1.Therefore to peel off a layer of InP using this etchant should have

anisotropic etching more than 3 !m based on equation (3) in section 2.2.1..

Figure 2.53: Isotropic InP etching using 25 % HCL for 9 minutes at 60 C


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2.2.3 GaSb Flexible Substrate Fabrication Process

2.2.3.1 GaSb substrate

Two-inch wafer of orientation of n-Type GaSb was ordered from University

Wafer. The wafer is Tellurium (Te ) doped with concentration of 1 X 1017

/ cm3. The

wafer was diced to 0.8 cm X 0.8 cm.

2.2.3.2 Protection oxide

For flexible III-V material it is required to choose the right material to act as a protection

layer from isotropic etchant. In addition to uniformity deposition. In flexible GaSb

substrate we chose Al2O3as protection oxide. 20 nm of Al2O3was deposited using ALD

to have uniformly deposition. Also, it is selective to GaSb isotropic etchant HCl:H2O2:

H2O [32, 33].

2.2.3.3

GaSb Anisotropic Etching

Looking for anisotropic etching for GaSb as one of the main steps to have flexible GaSb

substrate. GaSb first anisotropic etching trial done using Metal-RIE Oxford instruments,

Cl2and Ar [34] using 20 nm of Al2O3 toped with 4 !m of PR mask. The first trial etched

2.9 !m using 15 sccm Cl2and 5 Ar at 5 mTorr, 100 W DC, 1500 W ICP at 80OC for 2

minutes. This recipe has good anisotropic profile.


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Figure 2.54: First GaSb RIE trail : 2.9 !"etch of GaSb in 2 minutes.

In the second trial the same recipe was repeated but for 11 minutes to have above 10 !"

etch. This recipe was able to etch 12 !"but the profile is not as expected where it has

wall expansion due to the deep etching.

Figure 2.55: Second GaSb RIE trail : 12 !"etch of GaSb in 11 minutes.

!"# !%&"'' !%


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2.2.3.4 GaSb Isotropic Etching

Isotropic etchant for GaSb was chosen to be a mixture between Hydrogen Peroxide,

Hydrogen Chloride and DI (1 HCl: 1 H2O2: 2 H2O). This etchant was chosen between

other GaSb isotropic etchants since it has high etching rate (2.6 !"/ min ) [22], smooth

surface morphology with 2.35 nm RMS roughness [22] and selective to Al2O3 with low

etching rate. The exact etching rate were calculated by depositing 20 nm of Al2O3on

Silicon wafer using ALD then diced into smaller pieces. After that, the pieces were

placed in several isotropic GaSb etchant and the selectivity between the materials were

studied. And measure the thickness after etching reflectometer with Al2O3on Silicon

recipe. 1 HCl: 1 H2O2: 2 H2O has etching rate 1.3 nm/h for Al2O3.

40 nm of Al2O3was deposited on GaSb as a protection oxide layer. PR with 4 !"

(ECI3027) was used as a mask to etch the Al2O3 using RIE and create holes. After that,

the first isotropic etching trial was done using by placing the sample in 1 HCl: 1 H2O2: 2

H2O for a minute. From Figure 2.58 , shows that it has 1.7!"/min GaSb vertically

etching rate and 1.4!"/min lateral etching rate. In the second trial the same process was

repeated but for two minutes. Figure 2.59 shows 3 !"etch from both sides vertically and

laterally.


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Figure 2.56: First Isotropic trial: profile for GaSb etched using 1 HCl: 1 H2O2: 2 H2O

for a minute

Figure 2.57: Second Isotropic trial: profile for GaSb etched using1 HCl: 1 H2O2: 2

H2O for two minutes

&"( !"

) !"


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Figure 3.3: AFM of released GaAs on PDMS

Figure 3.4: Transparency of released 200 nm GaAs on PR on PDMS reached to 45 %at 724 nm wavelength.

200 400 600 800 10000

20

40

60

80

100

Transparenc

y(%)

Wavelength (nm)

PDMS

GaAs + PR


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too low compared to GaAs MOSCAP that was MBE-grown with silicon-doped GaAs

layer. Compared to HfO2high-K dielectric with an equivalent oxide thickness of 12

deposited by using a dc magnetron sputtering system and annealed to 400

O

C that has

capacitance around 2.3 !m / cm2at 100 KHz [36]. There are several differences that can

explain the difference in the results, including the dielectric material, the oxide thickness,

the back contact instead of the top contact and the annealing.

Figure 3.6: C-V GaAs MOSCAPs before releasing

After releasing the GaAs with MOSCAPs and double transfer using PDMS then tape the

same characterization were done on the MOSCAPs. However, none of the devices were

working and two devices shows breakdown effect from the dielectric [37, 38]. This can

be explained that the GaAs was not transferred. This can be from the holes separations is

not anymore 5 !m as the first released GaAs substrate but 15 !m instead and it was


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assumed that the etching rate is linearly 2.5 !m/min which mean 6 minutes. However, the

exact etching time should be calculated for 15 !m. Another challenge during the

characterization was to measure thin layer on liquid, which cause stress on the surface

due to the probes.

Figure 3.7: C-V after releasing shows breakdown effect of Al2O3.

Figure 3.8: Characterizing released MOSCAPs on Aluminum tape using probe-station


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3.3 InP and GaSb Substrates

Both InP and GaSb flexible substrate projects were not completed to have flexible

substrate. However, the basics steps and recipes were implemented including the deep

anisotropic etching ( more than 10 !") using RIE, isotropic etching using wet etching

and choosing the selective materials and the right masks. Connecting the puzzles to create

the complete process and release the substrate is not yet executed due to Metal-RIE

Oxford instrument is down in Nanofab lab. This limitation is temporary and the work will

continue on the project as soon as the tool is back.

3.4 Future Work

Stabilize the transfer process for GaAs by having working MOSCAPs. then fabricate

transistor instead of MOSCAPs on flexible 200 nm GaAs using the same process. For InP

and GaSb, linking the steps to complete InP and GaSb flexible substrate. Once this

process is rigid and reliable then create InP and GaSb MOSFETs in the same method

they were implemented on InP or GaSb wafers [39, 40] but with holes to release it later

on.


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4 CHAPTER 4:Conclusion

We demonstrate two processes to fabricate flexiable III-Vs for high mobility devices

where it allows to create devices on rigid substrate then transform it into flexible and

transparent devices. The first process based on using EPI and sacrificial layer. This

process preserving the surface smooth for high performance devices and leaving the III-

V's substrate recyclable for multiple fabrication and release cycles. This is an important

milestone in the quest for achieving high mobility flexible and transparent III-V devices.

On the otherside, EPI is expensive process. The seconds process is based on relaiable

process for flexiable Silicon and in this thesis we generalize it to III-Vs by using

anisotroipic etching, isotropic etchant and wall protection mateial that is selective to the

isotropic etchant to release the substrate. This process is cheper compared to the first one.

However, it leaves the surface rough that requires polishing before using it once again.


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