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Tracking Millions of Flows In High Speed Networks for Application Identification

Tian Pan, Xiaoyu Guo, Chenhui Zhang, Junchen Jiang, Hao Wu and Bin Liut Tsinghua National Laboratory for Information Science and Technology Department of Computer Science and Technology, Tsinghua University, Beijing 10084, China

2012 Proceedings IEEE INFOCOM

通訊所 周啓松

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Outline

Framework of systemExternal flow table managementALFE replacement policyTheoretical analysisEvaluationConclusion

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FRAMEWORK OF SYSTEM

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Emerge issues

On-chip SRAM is fast but insufficient to accommodate millions of concurrent flows which has to be stored in DDR or RLDRAM.

High hash collision rate and high cache miss rate.

It is hard to attach parallel off-chip DRAMs to gain performance improvement.

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Purpose

An on-chip/off-chip hierarchical flow table to achieve high speed packet lookup and maintain tens of millions of flows.

Adaptive Least Frequently Evicted(ALFE), which keeps the elephant flows longer in the cache thus increasing the cache hit rate.

An efficient management scheme is proposed to exploit DRAM's burst feature.

• Real trace evaluation on Altera FPGA platform indicates, with 200MHz internal clock, small sized cache with 16K entries can achieve up to 80% hit rate, enabling more than 70Mpps line rate flow tracking even at the 40-byte packets.

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Framework of the Proposed Application Identification

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Design Trade-offs and System-level Optimization

Stateless TCP Handling without Flow Reconstruction◦ 3-Way shaking

◦ FIN/RST

Fixed-allocated Hash Buckets to Exploit DRAM Bursts◦ Lower utilization of memory space

Cache Replacement Policy to Track Elephant Flows◦ Heavy-tailed distribution

lmpact of Misidentification

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EXTERNAL FLOW TABLE MANAGEMENT

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Flow Record Data Structure

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Fixed-allocated Hash Bucket How to store the flow records How to read/write the memory efficiently

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Device Independent Layer

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Memory Swapping Logic

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ALFE REPLACEMENT POLICY

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Heavy-tailedness

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Replacement Policy

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THEORETICAL ANALYSIS

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Poisson Queuing Network System

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Throughput and Queue Length

The arrival rate of packets is less than the service rate:

The overall maximum throughput is determined by the maximum arrival rate which could be afforded by each part.

According to queuing theory, the system queue length is:

𝑄=(1+𝛼+𝛼𝛽)𝜆

𝜇𝑐−(1+𝛼+𝛼𝛽)𝜆+

(𝛼+𝛼𝛽)𝜆𝜇 𝑓 −(𝛼+𝛼𝛽)𝜆

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EVALUATION

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Experiment Setup

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On-chip Flow Cache

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Off-chip Flow Table

The collision rate will be bounded less than when active flow number (AFN) is 4M.

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Bucket OverflowNE

BAW

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Memory Utilization

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Delay and Throughput

The 400MHz DRAM I/O interface transfers two data words per DRAM clock cycle.

The read latency is 6 DCs. The write latency is 7 DCs. The maximum throughput of DRAM is 44.44Mpps.

𝜇𝐷𝑅𝐴𝑀≤400𝑀𝐻𝑧

7+⌈𝑁𝐸

2⌉

(𝑝𝑝𝑠 ) ,𝑁𝐸≥ 4

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Trade-off between Utilization and Speed

When BAW is set to be 15 bits, the system reach optimal balance. In this paper, the BAW is expanded to 21 bits to provide higher

speed.

◦ NE = 8

◦ Total entry number = 16.8M

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Power

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System Overall Performance System Throughput

◦ Overall throughput under different cache entry number

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avalanche effect

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Conclusion

Detail of Matching Engine should be listed.

Setup time of flow table should be taken into account System Overall Performance.