tracker week 11th february 2004 0 cclrc, rutherford appleton laboratory, oxon, uk imperial college,...

Tracker Week 11th February 2004

http://www.te.rl.ac.uk/esdg/cms-fed 1

CCLRC, Rutherford Appleton Laboratory, Oxon, UKImperial College, London, UKBrunel University, London, UK

presented by John Coughlan RAL

FED Status & Production Plans



FED-PMC Production

Feb 2003 : Request for production of 40 (incl spares) more FED-PMC Mk3. Components on last time buy.

July 2003 : 28 delivered. Commissioning suspended.

Sept 2003 : Resistor problem reported;

11 cards repaired and returned

Dec 2003 : Commissioning restarted

Jan 2004 : 6 cards delivered (+ 3 USA repaired)

Feb 2004 : Final 6 cards just sent completes order.



9U FEDv1 Production Summary

Productions

Jan 2003 : 2 boards. Working.

June 2003 : 3 boards. Working.

Oct 2003 : 6 boards. Major problems.

Feb 2004 : 6 boards. In production. New manufacturers.

Locations of 5 working FEDs

2 at CERN in Tracker Lab. (one is to go to PISA next week).

2 at Imperial

1 at RALFEDv1 commissioning activities

Recent visits to Assembly plants

Tender Process

Future FED productions



Problem FED Batch (Oct 2003)

XRAY imageBGA 676 pins 1 mm pitch

Oct 2003: All 6 boards exhibited power shorts. BGAs.

All 6 were re-worked, replace BGAs (larger devices).

Dec 2003:006 : 2 Bscan errors007 : 1 Bscan error008 - 011 : Numerous Bscan errrors.None of these 6 boards should be sent outside UK.

Possible causes: Chemical contamination of pcbs depleting solder resist. Uncured solder resist ink leeching from vias (latter seen on similar boards).

Plans:Recover OptoRx from 008-011Send one board to National Physical Lab for analysis.Attempting recompense from pcb and/or assembler

Note: Dual supply: PCB and AssemblySame manufacturers for all 11 boards.

solder bridges x

Components



FEDv1 CommissioningMajor Activities in progress to verify FEDv1 Design:

Front-End FPGA Algorithms : Test existing logic. (RAL)

S-LINK : Test readout logic using DAQ FEDKit. (Imperial & RAL)

Power : Measure driving all 96 FED opto inputs. (Imperial)

Temperature : Test over-temperature shutdown. (RAL)

Analogue : ADC circuit change (Imperial)

FPGA in-situ reprogramming: Implementing Compact Flash interface firmware. Last major firmware block. (RAL)

Final Software: Implementing software to operate in Tracker DAQ environment. (Imperial & RAL + Trk DAQ group, centre of gravity now moved to CERN with FEDs)



FEDv1 Commissioning

ADC 1 10 10

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Serial I/O

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Config

Cluster Finding FPGA VERILOG Firmware

Full flags

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Global reset

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trig1Synch error

4x

Temp Sensor

Delay Line

Opto Rx

Clock 40 MHzD

LL

1x2x4x

per adc channel phase compensation required to bring

data into step

+ Raw Data mode, Scope mode, Test modes...

160 MHz



FEDv1 Commissioning

Working: APV Re-ordering. Pedestal registers loading/reading and subtraction.

Processed raw data mode is fully tested. Common mode median calculation and subtraction. Common mode median override. Cluster threshold registers loading/reading.

To do: Cluster finding. Disable strip function (by disabling a strip one can exclude it from the

CM calculation and the cluster finding). Testing FED error flags (disabling APVs, setting incorrect skew values,

etc).

Front-End FPGA Algorithms: Raw Data ; Processed Raw Data ; Zero Suppression



FEDv1 Commissioning

Slink Receiver

Generic PCI Card

Slink Transmitter

Transition Card (ECAL)

VM

E B

ackp

lane

FED Controller

Slink Controller

Control via VXI-MXI-2

LVDS Cable

FED

S-LINK

BE FPGA:

Pattern Generator Logic

Set-up based at Imperial with logic from RAL

Quickly Transferring Event Data successfully

Studying clock signal reflections

Need to speed up tests & understand occasional hang-ups



FEDv1 Commissioning

Power

Nr cards 1 20

5V (A) 6.5 130.0 +1.5V is derived from +5V rail.

3.3V (A) [3] 10.0 200.0 2.5V is derived from 3.3V

12V (A) 0.7 14.0 -5V is derived from +12V rail.

Typical Power (W) 80 1,603 estimate

Maximum Power (W) 96 1,926 estimate

Measured Power (W) [1] 75 1,500 No Inputs

*expect max 17 FEDs/crate

*



Multi Channel FED Tester

DACs

Fibre reels

8-way MU optical connectors

Clks provided via QPLLs

Analogue Optical Hybrids

Cross-point switches

VME interface

System control FPGA

G. Iles & Co.



FED Pulse Shaping Issues

Undershoot developed here by the

AD9218Effect not present on

scope

Un-optimised pulse shape from a FED channel emulatortest bench:NOT FROM THE FED



FEDv1 Commissioning

FED Software Enhancements

Makefile update for easy project building and release FED Shared Libraries created with minimal dependencies

available for integration into other software projects. Version 1 Fed Standalone debug software suite Assert and Exception handling upgrade for DAQ use XDAQ FED Supervisor upgraded to XDAQ version 2 Installation script to set up software to use the FED XML description integration commenced, waiting for

upgrade to HAL version with xerces

See Online Software Meeting



FEDv1 Future ProductionsProduction Plans

Feb/March 2004 : Finalise design changes for FEDv2.

Sign off against FED User Requirements Document.

April/May 2004 : Implement changes FEDv2 and review.

June/July 2004 : Manufacture 2 off FEDv2s.*

Q4/2004: Pre-production 20 off FEDv2s using company awarded tender.

Q2-Q4/2005: Production staged 500 off FEDv3s @ 50 month.

*NB: Some FPGAs now on long lead times (12+ weeks).



FEDv2 Design ChangesMajor Changes:

Power Block : Rationalises design. Changes well defined. Now being tested on sister board CALICE project.

ADC : AD9218 Device Bug. Change to 1Vpp mode. Reduce gain by half. Implemented on existing boards.

FPGA Configuration : Reprogram VME Boot device in-situ. tbd.

QDR Memory : Need to switch to next generation device. (same as CALICE)

S-LINK & TTS Signals : New Transition Card.



FEDv1 Assembly Companies

In last couple of months made visits to a number of Assembly plants (in UK)

Evaluate facilities in order to prepare tender documents.

Long term looking for a “one stop shop” solution for production:

Procurement, PCB manufacture, Assembly & Test

Advantages:

One company is responsible.

Can get guarantees.

Easier to manage.

Possibly cheaper.

Catching any problems early at company saves effort.

Disadvantages:

New procedures to learn. More effort in specification. Less control.

Minimise risk by understanding processes, equipment, test facilities.



FEDv1 Assembly Companies

Have seen 3 companies that would be capable of staged 500 off FED production.

Medium size facilities 100-200 employees.

Professional approach.

All offer one stop shop solution.

All have a similar range of facilities with slight variations.

All offer advanced Quality Control and Test Facilities.



Assembly Facilities

DD i Europe 2002 18

Manufacturing Process



Assembly Facilities

DD i Europe 2002 17

Services availableServices available

Floor 2 ServicesFloor 1 Services

Box Build Assem bly

Final Asse mbly

Front E nd Engine eringFastrack

SMT Asse mbly

TestT/H As sembly



Assembly Facilities

DD i Europe 2002 19

• Configured Line

• Dek 265 Fully Auto Printer, Highvolume (50K/hr) - S iemens I s-placeHS50/F5 + 10 Zone BTU Pyramax Oven

• Configured Line

• EKRA E5 Fully Auto Printer, Medium -high volume (20K/ hr) - Mydata MY15+ 10Zone BTU Pyramax Oven

• Configured Line

• Dek 248 + Vision, Medium volume(15K/ hr) – 2 x Tenryu + 5 Zone S iroccoOven

• Configured Cell

• Dek 248 + Vision, Low - mediumvolume (6K/hr) - 4 x Mydata TP9 2 x 6Zone Surf

PCB Assembly CapabilitiesPCB Assembly Capabilities



Assembly Facilities

DD i Europe 2002 23

• Automated Optical I nspection(AOI ) x 2

• Optical inspection

• 3D X- ray (BGA) I nspection

Quality Inspection ProcessesQuality Inspection Processes



Assembly Facilities

DD i Europe 2002 51

Takaya 9400 FICT ATE

Programming Debug ATE facility. Off-line Programming bureau facility. Fabmaster CAD file conversion software.

Customers include:

BAE, Malvern, Sun Micro, Marconi



FEDv1 Current ProductionImpressed with companies and their Quality Control and Test Facilities.

Much better than our previous prototype assembler.

Have learnt a lot by visits.

(Have also offered useful general advice on manufacturing issues, e.g. pcb metal finishes, Pb free directive).

Decided to switch and assemble existing 6 FEDv1 PCBs with one of these new companies to get experience: DDi Technologies.

(DDi also manufactured PCBs hence could offer manufacture guarantees, effectively one stop shop).

In process of setting up for assembly, exchanging design files and modification lists.Learning curve.Thermal profile in ovens using one of the bad boards from previous production.

Will Assemble, AOI, all FPGAs X-Rayed and do Flying Probe Test on assembled boards.

Delivery date for 6 boards is March 8th.



EU Tender ProcessEU Procurement Directives:

Goods & Services > £150 K

Open Procedure : Any party can tender, suitable for off the shelf items (e.g. components)

Restricted Procedure : Only N selected parties are invited to tender. N to be specified in advance. Two part process. Market survey + Tender.

Publish OJEC Notice for Expressions of Interest. Can pre-notify selected companies.

Associated Questionnaire. Rather general document. Elicit size, history of company, financial standing, standards adherence, facilities etc.

Evaluation and Selection of N companies to tender. Detailed enquiries. Visits.

Issue Tender. Detailed specification.

Still learning about these procedures. And how they fit with CERN (and CMS) procedures.

RAL is just about to issue a general pcb manufacture notice. Can benefit a lot from their experience.

Some issues to decide, eg is separate tender for FPGAs necessary?



Restricted Procedure



Testing At Assembly plant.

Do as much as possible. Discuss with companies. Positive responses. Q. Cost?

Boundary Scan. Flying probe or ATE. VME Crate single card tests. (without Opto inputs, using internal test

features). Major software effort to devise suitable tests with diagnostics. Draft document for “Reduced Test Setup at Assembly” just released.

Full System Tests at RAL/Imperial Full crate tests. Interfaces to TTC. Full optical soak system tests before shipping.

Installation and commissioning. Ship FEDs to Prevessin staging point. Repeat standalone soak tests? Install boards individually at CMS.



Spares Manufacture all in one go.

Need 440 for CMS Tracker. 60 working spares (for lifetime of CMS). Guesstimate. Assume final 500 delivered pass all commissioning tests.

Issues for later productions. Component availability. Memories. Expert availability. Design and Test. Changes in pcb and assembly processes. Standards. Markets. Pb Free Directive

Failure rates Hard to determine yet. Based on previous experiments assume normal failure rate is low after

commissioning, bath tub distribution (catastrophic crate loss?). Consider accelerated ageing tests offered by assembly companies? Assume most failures can be repaired. OptoRx can be removed.



Pb Free Directive We know it’s coming…

WEEE July 2006. In principle a good thing. Japan already claims Pb Free. Military, Automotive exempt (but small markets). We may be exempt. Contract manufacturers constrained to switch for mainstream

production. No drop in replacement to eutectic Sn/Pb solder. Alternatives require higher soldering temperatures. Manufacturing processes not fully understood. BGAs solder type? No long term experience of alternative solder e.g. failure in service. May require changing pcb base material from FR4.

Would advise to make FEDs before industry switches…



Summary FEDv1

6 more FEDv1’s in production. Commissioning tests at (CERN, Imperial & RAL) proceeding well. Target is to finalise changes for FEDv2 in next couple of months.

Design FEDv2 Implement design changes in April/May Manufacture couple of boards in summer.

Manufacture Looking a one stop shop solution. Presently evaluating possible candidates for large FED production (also

outside UK). Proposal document for test at Assembly plant. Learning fast about operation of processes and facilities.

EU Tender Investigating EU procedures. Learn from present RAL tender.



End

Intentionally left blank



First FED Prototype (Jan 2003)

Primary Side(Secondary side has 1/2 analogue)

OptoRx

CFlash

VME64x9U board

34 x FPGAs ~40K-2M gates

Analogue

TTC Power

Event Buffers

96 channels

JTAGBoundary Scan

Deliver FED “Package”:HardwareFirmwareSoftware



First Fully Assembled BoardPrimary Side Secondary Side

9U VME64x

PCB (2mm) 14 layers (incl 6 power & ground)

96 ADC channels : AD9218 Dual package 10 bit @ 40 MHz

~ 6 K components (smallest 0402) ; ~ 25 K tracks

1/2 Analogue circuitry on Secondary Side

Highest density at Front-End Units

FE Unit

BGAs 676 pins @ 1 mm pitch

Test with JTAG Boundary Scan

32http://www.te.rl.ac.uk/esdg/cms-fedTracker Week 11th February 2004

CMS Tracker FED

TrimDAC

differential op-amp ADC 9218

To readout

0v

RLoad

100

100 -> 50

33http://www.te.rl.ac.uk/esdg/cms-fedTracker Week 11th February 2004

CMS Tracker FED Firmware Status

Clocks

Data

SerialControls

VMELINK

VMEBus

VMESystemSystemACEACE

SystemACE

Clocks

EPROMEPROM

EPROM

TTCrxQDR Write QDR Read

SerialComms

Headers

TTCchanA

VME LinkRegs

S-LINKS-LINK S-LINK

Clocks

Data

SerialComms

ScopeMode

HeaderMode

FIFOs

Input

Regs

SerialControls

ScopeMode

Frame-FindngMode

Output

Input

Regs

Opto Rx DACOpto Rx DAC

DELAY FPGA x 3 x 8

FE FPGA x 8

BE FPGA

VME FPGA

ADCADC

Under Simulation

Under Test on FED

Only for FEDv2Only for FEDv2 Controls

Data Readout

Control

Throttle TCSInput

Cluster FindingCluster FindingModeMode

EdEd

SaeedSaeed

IvanIvan

EdEd

Ed, JohnEd, John

Saeed, IvanSaeed, Ivan

Chan BChan B

I2C

Temp

“Working” on FED

External Devices

TempTemp

14th July 2003

To be Implemented

QDR QDR

tracker week 11th february 2004 0 cclrc, rutherford appleton laboratory, oxon, uk imperial college,...

Documents

imperial ralpower

similar boards

ukimperial college

imperial ral trk daq

test modes

test readout logic

test existing logic

fedpmc mk3