trace32 solution for automotive platform automotive seminar able zhou . 2015/8/12 12/62 timestamps:...

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Trace32 Solution for

Automotive platform

Power Architecture

Aurix Architecture

Autosar Support

▪ Able zhou ▪[email protected]

Automotive Seminar ▪ Able Zhou . 2015/8/12 www.lauterbach.cn

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Power Architecture

Qorivva 32-bit Microcontrollers (MCUs) based on Power Architecture


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Debug Cable

LA-3736 JTAG Debugger for MPC5xxx

Support for controlling the external Watchdog with a dedicated pin

Support for calibration tools, e.g. ETAS ETK or dSPACE GSI with dedicated pins

Support for JTAG, DAP and

cJTAG interfaces


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Preprocessor & connect interface

Mictor38 Samtec50

LA-7630LA-3911

Samtec34


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Trace Port Configuration

Parallel Nexus Port

System Clock Divider:

Check processor data

sheet regarding max.

trace port frequency

(often ~80MHz)

Double Data rate

supported

only by few processors

(e.g. Leopard, Panther,

Calypso)

Do not use DDR with

PortMode 1/1, 1/3.


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Aurora Nexus Port

Aurora Configuration

must be done before

debug session starts

(i.e. SYStem.Up)

External clock only

required for automotive

processors

Use processor generated timestamps

for hi-res measurements


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On-chip trace (trace to memory)

Access class and

address range define

which buffer to use:

A: physical address

EEC: Emulation

memory in ED


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Program Trace

How dose program trace work?

Program Trace requires

Trace message

Trace start address

Branch-taken info

Instructions executed info

Indirect branch addresses

Program code


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Program Trace

Branch target

address

Instruction size (VLE)

Indirect branch

or interrupt?


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Ways to give program access to Trace32

Command: Trace.ACCESS

Analyze trace while core running:Trace.ACCESS DualPort

Analyze trace after power-down:Data.LOAD <file> /VM

Trace.ACCESS VM

Parts of code executed from temporary SRAM location (like done by MPC57XX boot assist code):Data.COPY <SRAM-range> VM:<SRAM-start>

Trace.ACCESS AutoVM


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Timestamps: Tool generated vs. Processor generated

Parallel Nexus:

One Nexus message stored per trace record= one timestamp per message

Small on-chip message FIFO (compared to Aurora)

Good precision with tool generated timestamp

BUT: Measured time must be longer than message transfer time

E.g. PT-IBM (5-bit ICNT and 16-bit U-ADDR)

MDO16: 2 MCKO cycles (4~8 core clock cycles)MDO4: 9 MCKO cycles (18~36 core clock cycles)

Hint: Some processors with par. Nexus support processorgenerated timestamps (but takes up much bandwidth!)


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Timestamps: Tool generated vs. Processor generated

Aurora Nexus:

Up to three nexus messages stored per trace record

Aurora requires big on-chip message FIFO(protocol imposed transmission gaps for synch packets)

= long message delays on chip

Tool generated timestamp only suitable for average time or long time measurements.

Use processor generated timestamps for precise measurements (and for measurements using TraceEnable)


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Data Trace Options

Data Trace Options

Read | Write | ReadWrite:

trace any loads and/or stores

ReadLimited | WriteLimitedReadWriteLimited:

trace any loads and/or storesexcluding stack accesses

(Only supported by MPC57XX and newer processors)

IFETCH:

Data trace messages contain information about instruction fetches


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Data Trace exceeds trace port bandwidth

Error message TARGET FIFO OVERFLOW

→ Filtering required


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Data Trace Filtering

Method A: Filter by target address

MPC57XX: 4 address ranges possible

Break.Set 0x40000000++0xFFFF /Write /TraceData

Break.Set my_var /ReadWrite /TraceData

Var.Break.Set my_array /Write /TraceData

Trace task switches (with loaded RTOS awareness):

Break.Set TASK.CONFIG(magic) /TraceData


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Data Trace Filtering

Method B: Message suppression

Data trace messages are suppressed based onfill level of on-chip message FIFO

NEXUS.DTM ReadWrite

NEXUS.SpenDTM ON

NEXUS.SupprTHReshold 1/4


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Event triggered tracing

Event triggered tracing of program & data

Any debug event can start or end tracing:

Instruction address

Break.Set func7 /TraceON

Data address

Break.Set my_var /Write /TraceOFF

Data address & value

Break.Set nActiveBlock /Read /Data.Word 162. /TraceON

Data address (opt. with value) within instruction address range

Break.Set sYmbol.RANGE(my_func) /MemoryWrite my_var /TraceOFF


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Tool selection

Chip search on www.lauterbach.com


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Freescale Application Note: AN4591

www.lauterbach.cn

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Trace32 Solution for Automotive

platform

• Power Architecture

• Aurix Architecture

• Autosar Support


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Aurix Name

SAK–TC275TE–64F200W AB EES


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AGBT Off chip trace

Device Feature >= 6, e.g. TC26x

Emulation Device

Package

BGA, e.g. TC2x7

Soldering device is highly recommended!

LQFP package: only Fusion Quad

Soldering device is mandatory!


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Fusion Quad Devices

Special LQFP package type

Provides AGBT off-chip trace

Provides JTAG for LQFP-Emulation Devices


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AURIX Architecture Overview

Up to 3 cores

Core types

Performance core

Efficiency core

Lockstep cores

Local RAM each core


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Multi-Core Debugging and Tracing

Multicore debugging for up to three TriCorecores, HSM core and GTM

Ready-to-use FLASH programming scripts

On-chip trace as well as serial off-chip trace

Start and stop synchronization


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Aurix Multicore Debugging

AMP

3 GUIs

Individual control

SMP

One GUI

Use with OS

AMP SMP

3 GUIs One GUI

Individual control Use with OS


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Multicore debugging SMP

Use provided scripts as a template, e.g.:

DO ~~/demo/tricore/hardware/triboard-tc2x5/tc275t-astep/*.cmm

tc275t-astep_smp_demo_multisieve.cmm

Runs from internal RAM (SPR)

tc275t-astep_smp_demo_multisieve_flash.cmm

Running from flash

tc275t-astep_smp_demo_waveform.cmm

Runs from internal RAM (SPR and LMU)

Cores are automatically synchronized


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MultiCore Debugging AMP

Use provided scripts as a template, e.g.:

DO ~~/demo/tricore/hardware/triboard-tc2x5/tc275t-astep/*.cmm

tc275t-astep_amp_demo_multisieve.cmm

Runs from internal RAM (SPR)

tc275t-astep_amp_demo_multisieve_flash.cmm

Running from flash

tc275t-astep_amp_demo_waveform.cmm

Runs from internal RAM (SPR and LMU)

SYnch your cores as you like


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Multicore debugging GTM

Generic Timer Module

Successor of the PCP (Peripheral Control Processor)

Bosch IP

TC27x-Astep is barely debuggable


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Aurix Debugging - flash program

Generic script:

DO ~~/demo/tricore/flash/tc27x.cmm

Device specific script (use as template), e.g.:

DO ~~/demo/tricore/hardware/triboard –

tc2x5/tc275tastep/tc275t-astep_demo_flash.cmm


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Aurix Debugging - flash program

Invalid data in

BMHDs (Boot Mode Header) (A-Step only)

UCB (User Configuration Block) sectors

HSM (Hardware Security Module) sectors

lock the device

Be careful!

=> Use provided cmm scripts


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Aurix trace Concept - source & message

(1) Write data only

(2) Via write data trace

(3) SRI: For up to two slaves only(System Peripheral Bus)

(4) SCR: Bus cycles generated by SCR(Shared Resource Interconnect))

(5) HSM: All trace information discarded by hardware


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Diagram of Aurix Trace MCDS/AGBT on- and off-chip trace

Message generation and triggering is dentical

Trace messages are written into EMEM

On-chip Trace: read by debugger

Off-chip Trace: read by AGBT and forwarded to trace port


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Multicore Trace - SMP


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Multicore Trace - AMP


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Mini MCDS

•Available in all TC29x devices

• Emulation Device not required

• Limited trace and trigger capabilities

• Only one TriCore core (selectable)

• 8 KB in LDRAM

• Requires MCDS-TriCore (LA-3799X)

Available in Q3/2015


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Peripheral Trace

Trace peripheral modules of AURIX Emulation Devices

e.g. CAN, DMA, Interrupts…

Display timing of signals

Evaluate different signals

e.g. DMA engine or channel number, CAN object number

Peripheral Trace is available for all peripheral modules, that can

be routed to OTGB (see Infineon documentation)


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DAP over CAN Physical Layer (DXCPL)

Single-Pin DAP (SPD) over CAN pins

CAN bus not usable any more

50 – 400 KB/s (~1 MHz debug port speed)

Analyzing field-returns

Available

LA-3888

Level adaption to CAN


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DAP over CAN Messages (DXCM)

DAP via CAN messages

No software instumentation necessary

CAN bus remains fully functional

Snail-speed debug support (~20 – 40 KB/s)

In-field tests, e.g. in a driving car

Watching parameters, variables, …

In development

Supported by TC21x, TC22x, TC23x only

LA-3888 (same as for DXCPL)

Available in Q4/2015


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Watch pin setup

Step 1:

Set breakpoint

with action

WATCH

Set breakpoint

with action

Alpha/Beta/Charly/

Delta/Echo

Step 2:

Route to output pin

Step 3 (optional):

Change

speedgrade


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WatchPins – Demo

Example / Demo:

Simple NOP loop

(0xc0000000--0xC0001000)

4 WatchPin ranges

WATCH and Beta routed to Pin0

(/BRKOUT)

Alpha and Charly routed to Pin1

(/BRKIN)


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Lauterbach Documentation

TriCore-specific documentation

Processor Architecture Manual

debugger_tricore.pdf

debugger_gtm.pdf

Application Note Debug Cable TriCore

tricore_app_ocds.pdf

AURIX Multicore Debugging

aurix_amp_smp_debugging.pdf

AURIX Training (Trace)

training_aurix_trace.pdf

www.lauterbach.cn

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Trace32 Solution for Automotive

platform

• Power Architecture

• Aurix Architecture

• Autosar Support


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Autosar ORTI support

Load symbols of application before loading ORTI file

Data.LOAD.Elf <symbolfile> /nocode

Load ORTI file in debugger

TASK.ORTI <ortifile>

Debugger then “knows” the OS and its objects


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OS specific menu

TASK.ORTI automatically creates menu entries for OS objects


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AUTOSAR tasks and objects

View objects and attributes with ORTI support

Performance analysis on tasks, functions, services and ISRs


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Task coverage


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Tool Interactions

Processor-In-the-Loop

Verify model on real HW

and detect divergences

Seamless support of the

Simulink SIL/PIL block

Support of AUTOSAR

models

http://cn.mathworks.com/products/connections/product_detail/product_73079.html

www.lauterbach.cn

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THANK YOU!

▪ Able zhou ▪[email protected]

Questions?

trace32 solution for automotive platform automotive seminar able zhou . 2015/8/12 12/62 timestamps:...

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