TOF Project OverviewMilestones, Budget

BNL

August 10, 2009

Geary Eppley

Rice University

Today’s presentations:

• The talks up until the afternoon break will cover the success of the TOF project to date. We will demonstrate that: – all deliverables are complete– all requirements have been met.

• Following the afternoon break, we will cover:– STAR’s physics plan for the new TOF system– Final installation plan; project summary.

Design goals:

• Beginning with the R&D in the late 1990s, the goal was to design an affordable TOF system for intermediate-Pt particle ID using available technology.

• The choice was multi-gap resistive plate chambers, MRPCs, developed by Bologna/ALICE. Our group participated with Bologna in this research effort.

• The electronics readout choice was the CERN HPTDC chip developed for the LHC. Our group participated in the beta testing of this chip.

Design considerations:

• The integration space available for TOF in STAR was that originally occupied by the CTB (central trigger barrel.)

• The space is about 2.2m from the beam line: this requires precision time measurement.

• The clearance between the TPC and EMC is about 10 cm.

• The space has a uniform 0.5T magnetic field parallel to the beam.

• There is limited space for “nearby” electronics outside the magnet steel.

ZCal

SiliconVertexTracker

CentralTriggerBarrel orTOF

FTPCs

TimeProjectionChamber

Barrel EMCalorimeter

VertexPositionDetectors

EndcapCalorimeter

Magnet

Coils

TPCEndcap &MWPC

ZCal

RICH

The MRPC module:

Side-View

The MRPC module, stack of 4:

International cooperation:

• Chinese groups joined early in the R&D effort.• The Chinese TOF Project contributed all of the detectors

(MRPCs) for the project.• The Chinese project developed the techniques to

successfully manufacture large numbers of the detectors with outstanding QA.

• Six Chinese institution joined STAR and Chinese students earning PhDs at BNL contributed greatly to the success of the project.

The TOF tray with MRPCs:

Tray-level electronics:

schematic by J. Schambach

Trays with TINO front-end cards installed:

TOF tray with full readout electronics:

Significant private sector partner:

• Following successful Phase I and Phase II SBIRs, Blue Sky Electronics, LLC became a significant contractor for the project.

• Blue Sky produced the TDIG read out boards and TCPU tray controller boards for the project.

• Blue Sky continues to assist with system integration.

86 fully-functioning trays installed for Run 9:

TPC support arms

Run-8 trays

TOF trays installed for Run 9:

graphic from W. Llope

Final installation:

• The 31 final trays were delivered to BNL in July• They have been re-tested on the test stand and are

ready for installation

Tray installation schedule:

• Installation schedule (presented August 2, 2007)– Run 8: 5 trays– Run 9: 65 trays– Run 10: 120 trays, project complete.

• Installation schedule (presented August 11, 2008)– Run 8: 5 trays– Run 9: 65 trays (more, depending on run schedule)– Run 10: 120 trays, project complete.

• Installation schedule, August 10, 2009 – Run 9: 86 trays

– Run 10: 120 trays, project complete

Schedule:

• The final design of the TDIG and TCPU readout electronics began almost a year later than originally anticipated and was completed one year later than the original milestones, thus delaying board production, and tray assembly and testing.

• However, the project finished tray assembly of 120 trays and 6 spares only 4 months behind the original plan.

• The project completed all deliverables only one calendar quarter behind the original plan when schedule contingency is included.

OriginalBaselineSchedule:

• Baseline milestones versus actual performance

• China project milestones in blue

• Red: >2 months late

WBS Milestone Description Baseline

completion date

Actual performance

1.1.2 Project approved FY06 Q1 Met 1.1.3 Preliminary design and safety review FY06 Q2 Met 1.1.4 Project accounts open FY06 Q2 Met 1.1.5 Final design review: Trays FY06 Q2 FY06 Q3 1.4.7 Decide viability of NINO chip FY06 Q2 Met 1.1.6 Final design review: Modules FY06 Q3 Met 1.2.2 Module production begins in China FY06 Q3 Met 1.4.8 Order HPTDC and NINO chips FY06 Q3 Met 1.4.9 TINO, TDIG R&D complete FY06 Q4 FY07 Q4 1.1.7 Final design review: Electronics FY06 Q4 FY07 Q4 1.2.3 128 modules received from China FY06 Q4 Met 1.3.7 Tray assembly begins FY06 Q4 FY07 Q3 1.4.10 TCPU, THUB R&D complete FY07 Q1 FY08 Q1 1.2.4 384 modules received from China FY07 Q1 Met 1.1.8 Final design review: Gas system, Start detector FY07 Q1 Met Final design review: Infrastructure FY07 Q1 FY09 Q2 1.3.8 4 trays complete FY07 Q2 FY07 Q4 1.2.5 768 modules received from China FY07 Q2 Met 1.1.9 Final design review: Low & High voltage systems FY07 Q1 Met 1.3.9 14 trays complete FY07 Q3 FY08 Q3 1.2.6 1312 modules received from China FY07 Q3 Met 1.3.10 24 trays complete FY07 Q4 FY08 Q3 1.2.7 1856 modules received from China FY07 Q4 Met 1.3.11 38 trays complete FY08 Q1 FY08 Q4 1.2.8 2400 modules received from China FY08 Q1 Met 1.3.12 52 trays complete FY08 Q2 FY08 Q4 1.3.13 Start detector complete FY08 Q1 Met 1.3.14 Gas system complete FY08 Q1 Met 1.2.9 2944 modules received from China FY08 Q2 Met 1.3.15 68 trays complete FY08 Q3 FY08 Q4 1.2.10 3488 modules received from China FY08 Q3 Met 1.3.16 86 trays complete FY08 Q4 FY09 Q1 1.2.11 4032 modules received from China FY08 Q4 Met 1.3.17 106 trays complete FY09 Q1 FY09 Q2 1.3.18 120 trays complete FY09 Q1 FY09 Q3 1.1.10 Project complete FY09 Q2 FY09 Q3

• Baseline milestones

• China project milestone in blue

• Re-baseline milestones

• Actual performance

Re-baseline schedule:

WBS Milestone Description Baseline

completion date

Re-baseline performance or date

Actual performance

1.1.8 Final design review: Infrastructure FY07 Q1 FY09 Q1 FY09 Q2 1.3.16 86 trays complete FY08 Q4 60 67 1.2.11 4032 modules received from China FY08 Q4 No change Met 1.3.18 120 trays complete FY09 Q1 82 94 1.3.19 100 trays complete FY09 Q2 111 1.3.20 120 trays complete FY09 Q3 126 1.1.10 Project complete FY09 Q2 FY09 Q4 FY09 Q3

Financial status:

• The project cost was re-estimated in July 2008.• A baseline change proposal was prepared for the last

review and approved in August 2008. The contingency was reduced by $700k to $200k in that proposal.

• There have been no changes in the estimated cost-to-complete the project since that time.

• In addition to the additional deliverables listed in the change proposal, the number of spare electronics cards has been increased to ~15%.

• The $199k in contingency can be released by the project and used for other purposes.

Project cost:as of June 30, 2009

WBS Baseline To date To completion Estimated cost Est. Contin.(amounts in k$)

1.3.1 Tray 534 482 26 5081.3.2 Gas system 70 61 0 611.3.3 High voltage system 142 167 0 1671.3.4 Start detector 31 6 0 61.3.5 Infrastructure 84 55 0 551.4.1 Board purchase and testing 2683 2378 42 24201.4.2 System testing and integration 296 259 50 3091.4.3 Electronics installation 253 178 33 2111.4.5 Low voltage system 259 188 3 1911.4.6 Electronics design 171 229 0 2291.1.1 Project management 261 401 20 4211.2.1 China Coordination 16 23 0 23

1 Project Total 4800 4427 174 4601 199

Summary:

• The project has completed all deliverables and all requirements have been met.

• Run 9 installation, commissioning, and performance was highly successful.

• The project is ready for this closeout review.• The $199k in remaining contingency can be released by

the project.• Run 10 installation is on track. The final trays has been

received at BNL, tested, and are ready for installation.

Backup

Run 9 performance:

• 94 trays were installed• It was discovered after the pole tips were closed that 2

trays lacked a LV connection and 5 trays lacked a HV connection.– There were sufficient trays to commission the system so the pole

tips were not reopened to investigate these problems.– When the pole tip was re-opened in July following the run, it was

determined that the 2 LV cables had been pulled out when the pole tip was closed. There was not enough slack in the cables. HV cables to 3 trays were simply not connected properly.

– The other 2 trays lacking HV had bad cables. More that 90 HV cables had to be repaired due to bad choice of solder flux by the vendor. All cables were tested but these failed after the test. No other cables have failed since the repairs.

Run 9 performance, continued:

• We do not anticipate a recurrence of LV and HV connection problems in Run 10. There will be time for sufficient testing before the pole tips are closed and time to re-open the poletip if any problem does occur.

• One tray could not be read out due to a TCPU FPGA code loading failure. This is a function of the TCPU that was overlooked in the QA so we do not expect this problem to occur in any other installed trays.

• 86 trays were readout for most of the run.• 2 additional trays could not be read out in the last month

of the run due to TDIG electronics/firmware failures.• The TOF system ran exceptionally smoothly and was

readout successfully in more than 99% of the runs in which it was meant to be included.