today’s lab
DESCRIPTION
Today’s Lab. Start working with Xilinx [pronounced: Zy-links] ISE design suite Create new project Enter code Synthesize code Simulate code. Half Adder. AND to arrive at Carry XOR to arrive at Sum. Half Adder Verilog Code. module half_adder (A, B, Sum, C_out); input A, B; - PowerPoint PPT PresentationTRANSCRIPT
Start working with Xilinx [pronounced: Zy-links] ISE design suite◦Create new project◦Enter code◦Synthesize code◦Simulate code
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012
AND to arrive at Carry XOR to arrive at Sum
Inputs Outputs
A B S C0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012
module half_adder (A, B, Sum, C_out);
input A, B;output Sum, C_out;
xor (Sum, A, B);and (C_out, A, B);
endmodule
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012
JIE CHEN 09/14/2010, Adapted by SCOTT TROCCHIA 3/21/2012