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Engineers’ Guide to AdvancedTCA® & MicroTCA®

Annual Industry Guide AdvancedTCA, MicroTCA and AdvancedMC solutions for telecom, Wi-Fi and WiMAX

LTE and 3G Wireless Infrastructure Drive ATCA Growth

The Case for ATCA in Military and Aerospace Applications

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ATCA Continues to Heat Up

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Cover graphic is incorrect. Refer to my email(s) to Spryte. The text in those ports should be 1 Gb/s, 10 Gb/s and 40 Gb/s

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Text over the blue cable end is hard to read...can you fuzz the cable or make text more legible?

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I have not seen the Pavlat write-up yet. And, did it go in Trends? or Viewpoint? (And did you switch the Alderman piece in the other location?)

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I commented on the titles today - please send a new Cover proof.

ATCA IPM Controller Core Based on SmartFusion™ FPGA

• Delivered as schematic with firmware and FPGA design for integration into customer board or module

• Runs firmware on ARM® Cortex®-M3 built into FPGA; FPGA logic implements some IPMC functions, plus customer functions

• Easily customized at schematic, firmware and/or FPGA design levels

• Corresponding solutions for all xTCA board/module controller types

Celebrating 10 Years of Delivering xTCA™ Management Solutions

Pigeon Point SyStemS

Over the decade, these solutions have been intensively tested in PICMG® plugfests and by leading TEMs and their suppliers, then incorporated in tens of thousands of shelves, plus hundreds of thousands of boards and modules, worldwide. They are supported by xTCA management experts who helped lead the development of the corresponding PICMG specifications.

New ShMM-700R-Based ATCA® Shelf Manager

• 30% less expensive, 20% smaller, fully compatible with market-leading ShMM-500R

• Installed on customer-designed shelf-specific carrier board

F O C U S E D • D E P E N D A B L E • P R O V E N

W o r l d - C l a s s M a n a g e M e n t C o M p o n e n t s

[email protected] www.pigeonpoint.com

Phone: 408.630.0200Fax: 408.360.0222Web: adlinktech.com

Phone: 518.762.1288Fax: 518.762.4399Web: vrmcs.com

V ROSEMICROSYSTEMS, INC.

V ROSE MICROSYSTEMS and ADLINK vigorously promote the advantages of the AdvancedTCA technology by providing complete platform solutions that offer high-density processing power, faster data throughput, and intelligent system management. De-signed for next-generation telecom, datacom, and equipment manufacturers, our AdvancedTCA platforms significantly reduce over-all development costs, come with extended operating lifecycles, and speed up critical time-to-market.

VRM-ATCA-8214

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Dual Intel® Xeon® L5638 Processor 10 Gigabit Ethernet

AdvancedTCA® Processor

20-Port 10GbE AdvancedTCA® Fabric Switch

Blade with 10GbE Uplink

12U 14-slot Dual Dual-Star AdvancedTCA® Shelf

AdvancedTCA Blades and SystemsComplete networking and telecom systems designed by

V Rose Microsystems and built with Adlink Technology.

Engineers’ Guide to ATCA® & MicroTCA Technologies 20122

Welcome to the 2012 Engineers’ Guide to ATCA® &

MicroTCA® Technologies

ATCA is the leading high-availability, commercial off-the-shelf (COTS) architecture for the telecom market, and the number of companies developing around ATCA continues to grow. ATCA- and MicroTCA-based systems are also being evaluated for other applications such as network-centric warfare, and MicroTCA is fulfilling requirements for a range of smaller, field-deployed systems. As the market grows, so do performance demands. Today’s systems integrate some of the industry’s most powerful processors, and the migration to 40 Gigabit Ethernet is begin-ning within a couple of years of the introductionof 10Gigabit Ethernet switch blades.

With rapid market growth and intense performance demands cometechnical challenges, and this resource guide arrives just in time. In this issue, you’ll find a broad range of product, tech-nology and market news to help keep you on track. Industry experts chime in on development strategies, market drivers and specific application opportunities, and top vendors present products and services to help you meet your development goals.

We hope you enjoy this EE CatalogATCA/MicroTCA Resource Guide. As always, we’d love to hear your feedback, thoughts and comments. Send them to [email protected].

Cheryl Berglund CoupéEditor, EECatalog.com

P.S. To subscribe to our series of Engineers’ Guides for embedded developers and engineers, visit:

www.eecatalog.com/subscribe

Engineers’ Guide to ATCA® & MicroTCA® Technologies 2012www.eecatalog.com/atca

VP/Associate PublisherClair Bright [email protected](415) 255-0390 ext. 15

EditorialEditorial DirectorJohn Blyler [email protected](503) 614-1082Managing EditorCheryl Berglund Coupé [email protected]

Creative/ProductionProduction Manager Spryte Heithecker

Graphic DesignersKeith Kelly - SeniorNicky Jacobson

Production Assistant Jenn Burkhardt

Senior Web DeveloperMariam Moattari

Advertising/Reprint SalesVP/Associate Publisher Embedded Electronics Media GroupClair Bright [email protected](415) 255-0390 ext. 15

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To Subscribewww.eecatalog.com/subscribe

Extension Media, LLCCorporate OfficePresident and PublisherVince [email protected]

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Vice President, Marketing and Product DevelopmentKaren [email protected]

Vice President, Business DevelopmentMelissa [email protected]

Special Thanks to Our Sponsors

The Engineers’ Guide to AdvancedTCA® & MicroTCA® Technologies 2012 is published by Extension Media LLC. Extension Media makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this Catalog nor does it make a commitment to update the information contained herein. Engineers’ Guide to AdvancedTCA® & MicroTCA® Technologies is Copyright ®2012Extension Media LLC. No information in this Catalog may be reproduced without expressed written permission from Extension Media @ 1786 18th Street, San Francisco, CA 94107-2343.

All registered trademarks and trademarks included in this Catalog are held by their respective companies. Every attempt was made to include all trademarks and registered trademarks where indicated by their companies.

TO BE UPDATED

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EECatalog Special Feature

According to Heavy Reading Components Insider, ATCA has become a mature market with a stable ecosystem. And the recently released “ATCA, AMCs & MicroTCA: 2012 User Survey” indicates that 40 Gb platforms are helping support this growth. Our roundtable participants reinforce this trend, and provide details around development challenges and strategies to address them. Thanks to Drew Sproul, director of marketing at Adax, Inc. and Rob Pettigrew, marketing director, Embedded Computing for Emerson Network Power for their insights.

EECatalog: How are designers addressing the challenges of building systems to meet new 40 Gigabit demands?

Drew Sproul, Adax: The electronics of 40Gb design have worked out much better than expected. Our chassis partners are all coming out with backplanes that are 40G-capable. As the switch and SBC manufacturers bring out their 40G products, interoperability

testing can begin right away. This approach allows today’s

10/40G systems to migrate swiftly to full 40G support with the switch and carrier blade upgrade.

Rob Pettigrew, Emerson Network Power: ATCA equipment providers are facing demand for higher bandwidth products, even though the ATCA 40G standard is not yet ratified by PICMG. In fact, companies like Emerson Network Power have been

shipping chassis that we are confident are “40G ready” for the past three years. This is possible because the ATCA 40G fabric channel, although not yet standardized by PICMG, is standardized by the IEEE as the 10GBase-KR standard 802.3ap-2007, which defines a 10Gbps Ethernet signal over a copper backplane connection. Four pairs of KR connections are available in each ATCA fabric channel, which can be used independently as four 10GBase-KR connections, or aggregated together in a single 40Gbps 40GBase-KR4 connection.

40Gb Migration Drives ATCA GrowthATCA equipment providers are facing demand for higher bandwidth products, even though the ATCA 40Gb standard hasn’t yet been ratified by PICMG. Migration strategies, interoperability and spec extensions all impact growth opportunities.By Cheryl Coupé, Editor

The recently released “ATCA, AMCs & MicroTCA: 2012 User Survey” analyzed current and projected use of these technologies by telecom equipment manufacturers, and reports a mature market.

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The ATCA 40G standard, when ratified by PICMG (expected July 2012), will map this 40G connection onto ATCA, and assign maximum contributions of cross talk and insertion loss to each of the three elements in a 40G connection: the payload blade, backplane and hub blade.

In the absence of this standard, ATCA manufacturers have typically made very conservative assumptions about how these signal integrity parameters are mapped to each of the system components. Companies that supply all three types of components will be able to guarantee end-to-end signal integrity. There will inevitably be interoperability issues for systems that are integrated from components provided by different companies.

EECatalog: What migration strategies are most successful in that evolution?

Pettigrew, Emerson Network Power: There are three steps to a smooth migration to 40G: introduction of a chassis, then a switch blade and finally payload blades.

40G-ready chassis have been available on the market for a number of years. Deploying these chassis early has enabled carriers to deploy 40G infra-structure early, providing an opportunity for field migration to 40G without the need for an expensive fork-lift upgrade.

Introducing 40G switches into these chassis is the next log-ical step. Emerson Network Power has a fully released 40G switch product, the ATCA-F140, which can be used in one of two 40G chassis: the six slot AXP640, or the fourteen-slot AXP1440. These switches are fully backward-compatible, meaning that they will work with current 10G payload. Deploying these switches early will mean that the complete platform core will be ready for 40G payload.

The last step to 40G heaven is to deploy 40G payload. These products are available now in early access, and will be fully released before the end of the year. Technologies such as the OCTEON II processor family from Cavium pro-vide an unprecedented amount of packet processing and bandwidth for applications such as policy and access con-trol, lawful intercept and various classes of mobile data optimization applications.

EECatalog: With the explosion in data traffic due to VoIP and multimedia/video, how will offload engines for TCP-UDP/IP, TOE, CODEC transcoders and other packet-optimization algorithms play a role?

Sproul, Adax: Packet processing done on specialized NPUs is key in identifying and prioritizing data traffic, especially upgrades to higher quality video as a real-time revenue stream. ‘Premium’ Skype as an OTT voice application is ideal as a revenue-generating managed service. Both of these applications, as well as low-priority Internet traffic off-load and policy-based parental controls, require line-speed packet processing.

Pettigrew, Emerson Network Power: These offload engines are critical to provide the performance boost that general-purpose processor cores require to meet the needs of next-generation network elements. These engines are either available integrated with specialize multicore devices, like the OCTEON II from Cavium, or available as physically separate PCIe-connected devices, like the Cavium Nitrox,

or the recently disclosed Intel Crystal Forest technology.

EECatalog: How effectively is the industry addressing interop-erability standards across ATCA blades, shelves and backplanes?

Sproul, Adax: ATCA has a very strong foundation in PICMG standards. Implementa-tion of these standards has also been augmented by equally strong interoperability forums. The real challenge for ATCA customers is support for the integrated system, sub-systems and middleware like DPI, security and traffic management. In this regard, successful suppliers will move the hardware to the back and bring application development support to the forefront.

Pettigrew, Emerson Network Power: Historically, the industry has collectively worked together to improve ATCA interoperability in the context of a trade association called Communications Platform Trade Association(CP-TA).Within this association, companies that were otherwise competitors worked together to ensure that their products worked well together. This level of co-opetition was critical to the success of the ATCA standard, because if products from competing companies did not work well together, then the standard would not have been truly open.

The electronics of 40Gb design have worked out much better

than expected.

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PICMG has since acquired the assets of CP-TA, which is now the vehicle for this interoper-ability work. The technical specifications and test pro-cedures written by the CP-TA are now managed by PICMG.

EECatalog: How will new MicroTCA and ATCA spec extensions enhance growth opportunities?

Sproul, Adax: In my opinion, not much. ATCA and uTCA manufacturers are already fudging the specs, especially as they relate to power and cooling. 300-400W per-slot chassis with effective cooling are on the market today. I just don’t see new 800+W ATCAblades and 80W AMC cards competing against proprietary blade servers from HP, IBM and Oracle blade servers with support for AMC and PCIe cards.

Pettigrew, Emerson Network Power: The ATCA Extensions specification is being drafted to allow for larger payload and higher density ATCA systems. This is necessary to allow ATCA systems to better compete from a price/performance perspective with traditional IT computing systems. This in

turn will allow for deeper market penetration of ATCA into adjacent markets outside of the traditional telecom net-work core. Look for features like double-wide boards, which can accommodate more memory and larger heat sinks, and back-to-back systems, which can more effectively use the deeper system space available in the traditional data center environment. We

expect the ATCA Extensions specification to be released by PICMG this year.

Cheryl Berglund Coupé is editor of EECatalog.com. Her articles have appeared in EE Times, Electronic Business, Microsoft Embedded Review and Win-dows Developer’s Journal and she has developed presentations for the Embedded Systems Conference and ICSPAT. She has held a variety of production, technical marketing and writing positions within technology com-panies and agencies in the Northwest.

The ATCA Extensions specification is being drafted

to allow for larger payload and higher density ATCA systems.

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From the late 1940’s up through 1990, all computers were CPU-bound: the I/O interconnections could pro-vide more data than the CPU could process. After 1990, clock speeds for microprocessors were doubling every 18 months (Moore’s Law), and CPU vendors started putting multiple cores on the same die. From 1990 through today, computers are I/O-bound: the CPUs can process more data than the interconnects can provide. Before too long, new embedded architectures will be needed such as the 4-dimention hypercube shown in the Figure.

While the increases in CPU performance were revo-lutionary in the past 15 years, the increases in I/O bandwidth have been merely incremental. When we were using parallel buses such as VME or PCI as the primary architecture, we increased performance of the machine

by widening the data buses...from 8 bits, to 16, 32, 64, and in some instances to 128 and 256-bits wide. VME, for instance, went from 16-bits wide to 2-bits wide, and then to 64-bits wide in only 10 years. And, we also clocked-up the buses from time to time. But, the rule of thumb is that every time you double your bus clock speed, the distance you can run the bus is cut in half, due to reflections and other signal integrity problems associated with single-ended signals.

During this period where buses ruled the computer land-scape, we started connecting multiple processors on the already-slow bus connections to create multi-processing systems. Since the bus was a shared resource, CPUs had to arbitrate for the use of the bus, or share data with a cache coherency scheme (Snooping and Snarfing). That’s when we discovered the law of diminishing returns. According to many computer science studies, after four processors we hit the knee of the processing curve: each added pro-cessor did less and less work. A four-processor system could outperform an 8-processor system; not good value for the money.

In the 2000’s, we switched from parallel I/O buses like PCI to multi-gigaHertz high-speed serial buses using differen-tial signaling. That helped a little, but we still remained seriously I/O-Bound. PCI-Express (PCIe) was slightly helpful in relieving some of the bandwidth problems, but the stupid tree structure– a carry-over from the old par-allel PCI bus architecture–and the high latency associated with the transfers just exacerbated the existing problem. PCIe was never designed as an interprocessor communi-cations (IPC) mechanism. Desktop and laptop PC’s were considered single-processor systems, so there was no need for an efficient and powerful IPC technique.

Companies outside the “nefarious PC morass” (such as us the embedded industry) recognized the need for faster interprocessor data bandwidths in multiprocessor systems. They designed Serial RapidIO (SRIO), InfiniBand (IB), and even the Ethernet crowd started efforts to increase IPC

Moving To N-Dimensional Embedded Supercomputers But first, let’s look at where computers startedFrom CPU-bound to today’s I/O-bound architectures. We now have enough CPU horsepower to worry about I/O bottlenecks. But how did we get here? And, where will system designs go next?By Ray Alderman, Executive Director, VITA

Caption: 4-dimension hypercube, image courtesy of Wikipedia

Figure: A 4-dimension hypercube where every node connects to four others. This can scale to n nodes to realize embedded supercomputing architectures. (Courtesy: Wikipedia.)

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bandwidth by eliminating the huge heavy protocol stacks infamous in traditional Ethernet connections. Now we can hook lots of processors together to build some potentially powerful computing systems. But, Gene Amdahl’s Law showed us yet another instance of diminishing returns to consider.

All microprocessors use Von Neumann or Harvard archi-tectures that execute one instruction on one data element at a time in a serial fashion (SISD, or single instruction, single data). This convention matched how programmers think: manipulating data one element at a time. That morphed into architectures that execute multiple instruc-tions on multiple data elements (MIMD), where different parts of the CPU are operating on multiple data elements with multiple instructions in parallel. Amdahl, in his law, says that only a very small segment of a serially-contrived program can be “parallelized” and executed on multiple processors to enhance performance. Amdahl also says that very few programs can gain any significant performance improvement through parallelization.

But, when certain applications are “parsed” by the pro-grammer into specific segments than can run concurrently on different processors, we begin to defeat the law of diminishing returns and Amdahl’s law. Algorithms used in Radar, Sonar, Signal Intelligence (SIGINT), and Elec-tronic Warfare are some interesting examples. These are algorithms for Fast Fourier transforms (FFT) and SWARM algorithms (a collection of autonomous craft operating collectively) for UAVs (Unmanned Aerial Vehicles) and UUVs (Unmanned Underwater Vehicles). Other applica-tions that can be effectively parsed for parallel processing

are simulations in Finite Element Analysis (FEA) and Com-putational Fluid Dynamics (CFD). For the past 80 years, all computer architectures have been stuck in terribly infantile 2-dimensional implementation domains. But, as the high-speed serial connections on both copper and optical links begin to eliminate the I/O-bound limitations of present-day computer architectures, we must move to n-dimensional architectures to recognize supercomputing performance levels. That can be done with 4-dimensional and 6-dimensional hypercubes (see Figure). VITA is now setting the standards for these advanced computing archi-tectures in embedded applications.

After all, there are only three possible hardware and pro-tocol architectures for the I/O and IPC links in a computer system. But, that’s a topic for another paper, since it takes a lot more space to describe than my evil editorial masters have allotted me here.

Ray Alderman is the Executive Director of VITA, an ANSI-certified standards developer for high-performance computer systems and architectures used in critical embedded appli-cations. He was previously Technical Director of VITA, CEO of PEP Modular Computers, and a partner and founder at Matrix Corporation. Ray worked in mainframe computers at Burroughs Corporation, and was a microprocessor applications engineer for both Texas In-struments (TMS9900) and Motorola (6809 and 68000) after serving in the US Army Military Intelligence group during the VN war.

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In recent years, there has been a market and technology trend towards the convergence of network infrastructure to a common platform or modular components that support multiple network elements and functions, such as applica-tion processing, control processing, packet processing and signal processing. In addition to cost savings and reduced time-to-market, this approach provides the flexibility of modularity and the ability to independently upgrade system components where and when needed, using a common plat-form or modular components in shelf systems and networks of varying sizes. In traditional networks, switching modules would be used to route traffic between in-band system mod-ules and out-of-band systems; processor modules used for applications and control-plane functions; packet processing modules used for data-plane functions; and DSP modules used for specialized signal-plane functions.

Enhancements to processor architecture and the avail-ability of new software development tools are enabling developers to use a single blade architecture for consolida-tion of all their application, control and packet-processing workloads. Huge performance boosts achieved by this hardware/software combination are making the processor blade architecture increasingly viable as a packet-pro-cessing solution. To illustrate this evolution, we developed a series of tests to verify that an AdvancedTCA processor blade combined with a data-plane development kit (DPDK) supplied by the CPU manufacturer can provide the required performance and consolidate IP forwarding ser-vices using a single platform. In summary, we compared the Layer3 forwarding performance of an ATCA blade using native Linux IP forwarding without any additional optimization from software with that obtained using the DPDK. We then analyzed the reasons behind the gains in IP forwarding performance achieved using the DPDK.

AdvancedTCA Processor BladeThe ATCA blade used in this study is a highly integrated processor blade with dual x86 processors, each with 8 cores (16 threads) and supporting eight channels of DDR3-1600 VLP RDIMM for a maximum system memory capacity of 64GB per processor. Network I/O features include two

10Gigabit Ethernet ports (XAUI, 10GBase-KX4) compliant with PICMG 3.1 option 1/9, and up to six Gigabit Ethernet 10/100/1000BASE-T ports to the front panel. The detailed architecture of the ATCA blade is illustrated in the func-tional block diagram in Figure 1.

Data-Plane Development KitThe data plane development kit provides a lightweight run-time environment for x86 architecture processors, offering low overhead and run-to-completion mode to maximize packet-processing performance. The environment provides a rich selection of optimized and efficient libraries, also known as the environment abstraction layer (EAL), which are responsible for initializing and allocating low-level resources, hiding the environment specifics from the applications and libraries, and gaining access to the low-level resources such as memory space, PCI devices, timers and consoles.

The EAL provides an optimized poll mode driver (PMD); memory & buffer management;and timer, debug and packet-handling APIs, some of which may also be provided by the Linux OS. To facilitate interaction with application layers, the EAL, together with standard the GNU C Library (GLIBC), provide full APIs for integration with higher level applications. The software hierarchy is shown in Figure 2.

Test TopologyIn order to measure the speed at which the ATCA processor blade can process and forward IP packets at the Layer3 level, we used the following test environment shown in Figure 3.

Two ATCA switch blades with networking software pro-vided non-blocking interconnection switches for the 10GbE Fabric and 1GbE Base Interface channels of all three processor blades in the ATCA shelf, which supports a full-mesh topology. Therefore, each switch blade can provide at least one Fabric and Base interface connection to each processor blade. A test system, compliant with RFC2544 for throughput benchmarking, was used as a packet simulator to send IP packets with different frame sizes and collect the final statistical data, such as frames per second and throughput.

Consolidating Packet Forwarding Services with Data-Plane Development SoftwareConsolidating all three planes to a single ATCA blade is now possible.

By Jack Lin, Yunxia Guo, and Xiang Li, ADLINK

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As shown in the topology of the test environment above, the ATCA processor blade (device under test: DUT) has four

Gigabit Ethernet interfaces: two directly from the front panel (Flow1 and Flow2), and another two from the Base Interfaces (Flow3 and Flow4) via the DUT’s Base switches. In addition to these four 1GbE interfaces, the DUT has two 10GbE inter-faces connected to the test system via the switch blade.

In our test environment, the DUT was responsible for receiving IPv4 packets from the test system, processing these packets at the Layer3 level (e.g., packet de-encapsulation, IPv4 header checksum validation, route table look-up and packet encapsulation), then finally sending the packets back to the test system according to the routing table look-up result. All six flows are bi-directional: for example, the test system sends frames from Interface 1/2/3/4/5/6 to the DUT and receives frames via Interface 2/1/4/3/6/5, respectively.

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Figure 1: ADLINK aTCA-6200 functional block diagram

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Test MethodologyTo evaluate how the DPDK consolidates packet-forwarding services on the processor blade, an IP forwarding application based on the DPDK was used in the following two test cases:

Performance with native LinuxIn this test, UbuntuServer 11.10 64-bit was installed on the ATCA processor blade.

Performance with DPDK The DPDK can be run in different modes, such as Bare Metal, Linux with Bare Metal Run-Time and Linux User Space. The Linux User Space mode is the easiest to use in the initial development stages. Details of how the DPDK functions in Linux User Space Mode are shown in Figure 4.

After compiling the DPDK target environment, an IP forwarding application can be run as a Linux User Space application.

ResultsAfter testing the ATCA processor blade under native Linux and with the data-plane development kit provided by the CPU manufacturer, we compared the IP forwarding performance in these two configurations from the four 1GbE interfaces (2 from the front panel and 2 from the Base Interfaces) and two 10GbE Fabric Interfaces. In addition, we bench marked the combined IPv4 forwarding performance of the processor blade using all six interfaces simultaneously(four 1GbE interfaces and two 10GbE interfaces).

ADLINK aTCA-8505 ShelfIxia XM12 Test System

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Figure 3: IP Forwarding Test Environment

Figure 4: Intel DPDK running in Linux User Space Mode

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Performance comparison using four 1GbE interfacesWhen running IPv4 forwarding on the four 1GbE interfaces of the processor blade with native Linux IP for-warding enabled,a rate of 1 million frames per second can be sustained with a frame size of 64 bytes. As the frame size is increased to 1024 bytes, native Linux IP forwarding can approach 100% of the line rate. But in the real world, frame sizes are usually smaller than 1024 bytes, so 100% line rate forwarding is not achievable. However, with the DPDK running on only two CPU threads under the same Linux OS, the processor blade can forward frames at 100% line speed without any frames lost regardless of the frame size setting, as shown in Figure 5.

The ATCA processor blade running the DPDK provides almost 6 times the IP forwarding performance compared to native Linux IP forwarding.

Performance comparison using two 10GbE interfacesRunning the IP forwarding test on the two 10GbE Fabric Interfaces shows an even greater performance gap between native Linux and DPDK-based IP forwarding than that using four 1GbE interfaces. As shown in Figure 6, the processor blade with DPDK running on only two threads provides a gain of more than 10 times IP forwarding per-formance compared to native Linux using all available CPU threads.

Total IPv4 forwarding performance of the processor bladeTesting the combined IP forwarding performance of the processor blade using all available interfaces (two 10GbE Fabric Interfaces, two 1GbE front panel interfaces and two

1GbE Base Interfaces), the processor blade with the DPDK can forward up to 27 million frames per second when the frame size is set to 64 bytes. In other words, up to 18Gbps of the theoretical 24Gbps throughput can be forwarded (i.e.,75.3% of the line rate). Furthermore, the throughput in terms of the line rate increases to 92.3%, even up to 99%, when the frame size is set to 128 bytes and 256 bytes respectively.

AnalysisThe reasons why the DPDK can consolidate more pow-erful IP forwarding performance than available with native Linux come mainly from the DPDK design features described below.

Polling mode instead of interruptsGenerally, when packets come in, native Linux receives interrupts from the network interface controller (NIC), schedules the softIRQ, proceeds with context switching, and invokes system calls such as read() and write().

In contrast, the DPDK uses an optimized poll mode driver (PMD) instead of the default Ethernet driver to pull the incoming packets continuously, avoiding software inter-rupts, context switching and invoking of system calls. This saves significant CPU resources and reduces latency.

Huge page instead of traditional pagesCompared to the 4 kB pages of native Linux, using larger pages means time savings for page look-ups and the reduced possibility of a translation look aside buffer (TLB) cache miss.

IPv4 L3 Forwarding Performance of Native Linux and Intel DPDK(ADLINK aTCA‐6200 with 4x 1GbE interfaces)

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Figure 5: IP Forwarding Performance comparison using 4x 1GbE interfaces Figure 5: IP Forwarding performance comparison using 4x 1GbE interfaces

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The DPDK runs as a user-space application by allocating huge pages in its own memory zone to store frame buffer, ring and other related buffers, that are out of the control of other applications, even the Linux kernel. In the test described in this white paper, a total of 1024@2MB huge pages are reserved for running IP forwarding applications.

Zero-copy buffersIn traditional packet processing, native Linux decapsulates the packet header, and then copies the data to the user space buffer according to the socket ID. Once the user space application finishes processing the data, a write system call is invoked to send out data to the kernel, which takes charge of copying data from the user space buffer to the

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Figure 6: IP Forwarding Performance comparison using 2x 10GbE interfaces Figure 6: IP Forwarding performance comparison using 2x 10GbE interfaces

IPv4 L3 Forwarding Performance of ADLINK aTCA‐6200 and Intel DPDK(with 2x 10GbE Fabric + 4x 1GbE)

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Figure 7: IP Forwarding Performance comparison using 2x 10GbE + 4x 1GbE interfaces Figure 7: IP Forwarding performance comparison using 2x 10GbE + 4x 1GbE interfaces



kernel buffer, encapsulates the packet header and finally sends it out via the relevant physical port. Obviously, the native Linux process sacrifices time and resources on buffer copies between kernel and user space buffers.

In comparison, the DPDK receives packets at its reserved memory zone, which is located in the user-space buffer, and then classifies the packets to each flow according to configured rules without copying to the kernel buffer. After processing the decapsulated packets, it encapsulates the packets with the correct headers in the same user-space buffer, and finally sends them out to the relevant physical ports.

Run-to-implement and core affinityPrior to running applications, the DPDK initializes to allocate all low-level resources, such as memory space, PCI device, timers, consoles, which are reserved for DPDK-based applications only. After initialization, each of the cores are launched to take over each execute unit, which run the same or different workloads, depending on the actual application requirements.

Moreover, the DPDK provides a way to set each execute unit running in each core to keep more core affinity, thus avoiding cache misses. In the tests described, the physical ports of the processor blade are bound to two different CPU threads according to affinity.

Lockless implement and cache alignmentThe libraries or APIs provided by the DPDK are optimized to be lockless to prevent dead locks for multi-thread appli-cations. For buffer, ring and other data structures, the DPDK also optimizes them to be cache aligned to maximize cache-line efficiency and minimize cache-line contention.

ConclusionBy analyzing the results of our tests using the ATCA pro-cessor blade’s four 1GbE interfaces and two 10GbE Fabric

Interfaces with and without the data plane development kit provided by the CPU manufacturer (Figures 5 and 6), we can conclude that running Linux with the DPDK and using only two CPU threads for IP forwarding can achieve approximately 10 times the IP forwarding performance of that achieved by native Linux with all CPU threads run-ning on the same hardware platform.

As is evident in Figure 7, the IPv4 forwarding performance achieved by the processor blade with the DPDK makes it cost- and performance-effective for customers to migrate their packet processing applications from network processor-based hardware to x86-based platforms, and use a uniform platform to deploy different services, such as application pro-cessing, control processing and packet processing services.

Jack Lin is the team manager of Platform Inte-gration and Validation, Embedded Computing Product Segment, which focuses on validat-ing ADLINK building blocks and integrating application-ready platforms for end customers. He holds a B.S. and M.S. in information and communication engineering from Beijing JiaoTong University. Prior to joining ADLINK, he worked for Intel and Kasenna.

Yunxia Guo is a PIV software system engineer in ADLINK’s Embedded Computing Product Segment and holds a B.S. in communication engineering from Hubei University of Technol-ogy and an M.S. in information and communi-cation engineering from Wuhan University of Technology.

Xiang Li is a member of the platform integra-tion and validation team in ADLINK’s Embed-ded Computing Product Segment. He holds a B.S. in electronic and information engineering from Shanghai Tongji University.



Multicore processor technology combined with the AdvancedTCA form factor results in multi-faceted per-formance scaling options: performance can be scaled by using processor silicon with more processor cores as well as adding more ATCA blades into the chassis. Moreover, ATCA systems are easy to configure for a specific work load by combining standard multi-core x86 processors with specialized packet processors. Having multiple cores within a processor is potentially highly advanta-geous, of course, but they are useless unless the software infrastructure has a means of utilizing these cores. Vir-tualization is one technique that allows multiple cores to run multiple applications and their operating systems in parallel. New application development - or porting an existing application to a mul-ticore environment - is eased by the development tools that are available. Packet processors in particular have a powerful set of tools that allow designing applications that run in parallel on mul-tiple cores.

Multicore on the RiseJust a few years ago, each new processor silicon release brought along a worthwhile clock frequency improvement. Today, however, clock frequency is not the main news in a new generation processor release; it’s the number of pro-cessor cores within the device that’s taking center stage. As usual, small startups such as Cavium Networks and NetLogic (now Broadcom) were the first to market with multicore general purpose processors. Then followed the giants: Intel, AMD and Freescale. Today, 4-8 cores within a processor is the norm - and there are architectures available that feature as many as 64 cores within one processor.

The motivation for multicore processors is fairly simple: when running a typical application, the processor spends

most of its time waiting for data to process. Historically, memory latency improved at a much slower pace than the speed of the processor. Today, the mismatch between processor and memory is such that adding a few extra clocks to the processor doesn’t improve performance to any worthwhile degree. As if this is not a big enough problem, there is the issue of power consumption: adding a few extra Hertz to the clock translates into a significant increase in power consumption.

From the multicore architecture perspective, having multiple cores, each running perhaps at a slightly slower speed, results in a higher overall performance solu-

tion. Considering that the processor spends roughly three quarters of its time waiting for the memory, this approach works well for applications that can benefit from parallel processing. Obviously, the memory subsystem implementation has to support multiple data accesses in parallel, which is typically the case today.

From Enclosure to an AdvancedTCA System

Let’s move the focus from the silicon to the system. When a single server with two or four multicore processors is required the 19-inch rack-mountable enclosure – the ‘pizza box’ - works very well. When the application requires more than that, or when redundancy and higher reliability are required, AdvancedTCA becomes a good choice for system implementation (Figure 1). The AdvancedTCA chassis can support up to 14 dual processor blades interconnected via two high performance Ethernet switches in a redundant fashion (Figure 2). All blades within the chassis share power supplies and cooling fans, which are also imple-mented to support redundancy and higher reliability.

Performance Grows When Multicore Partners with ATCAATCA is the ideal platform for compute-intensive multicore applications. Even when legacy applications can’t use multicore performance, virtualization evens the score in a tidy hardware system.

By Gene Juknevicius, GE Intelligent Platforms

ATCA allows further consolidation of multiple

blades with multiple multicore processors: racks of legacy servers can be reduced to a

single ATCA chassis.



A key requirement when building a multi-blade system is a high speed, reliable interconnect between the blades. From this perspective, an ATCA system interconnects each blade via a Fabric Interface and Base Interface. The Fabric Interface, which is considered to be a data path interface, is predominantly 10Gbit Ethernet today with some appli-cations already switching to 40Gbit Ethernet. The Base Interface is a control path and is implemented using 1Gbit Ethernet. Both Fabric and Base Interfaces are implemented in a redundant fashion, such that each ATCA blade connects to both ATCA hubs which provide the required Ethernet switching resources. All connectivity is provided via the ATCA backplane, reducing external cabling, thereby making the overall system more reliable and more serviceable.

The separation of the control plane and data plane not only enables high performance blade management and control services, but also isolates the control traffic from the revenue-generating data plane traffic. Such isolation of the two planes becomes critical when overall system secu-rity is considered. Plane isolation ensures that data plane traffic, which is typically customer-facing traffic, will not intentionally or unintentionally start managing Ethernet switches and disrupt the operation of the complete system.

Figure 1: A fully populated ATCA integrated platform from NEI, an integration partner with GE Intelligent Platforms.

Figure 2: The internal interconnect diagram for a 16-slot ATCA chassis containing 14 blades and two Ethernet switch blades.

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Compute Application RequirementsDepending on the application type, the high performance interconnect brings a different value proposition. In a com-pute type application, it’s essential that large numbers of processors communicate with high throughput and very low latency. To that extent, 10Gbit and 40Gbit Ethernet can provide the required data throughput via the Fabric Inter-face. Some Ethernet switches also support ‘pass-through switching mode’ where packet transmission starts before the packet is fully received. In such cases, packet switching latency can be lower than 500ns. Although configuring two hubs (Ethernet switches) in an ATCA chassis is primarily for redundancy, it is also possible to use both hubs in par-allel, effectively doubling the available bandwidth.

From the compute power density perspective, it is inter-esting to note that 14 ATCA blades (Figure 3), each featuring dual Intel 8-core Sandy Bridge processors, yields no fewer than 224 x86 cores within a single ATCA chassis, all inter-connected via an in-chassis high speed interconnect.

Compute applications also tend to require significant storage capacity, bandwidth and reliability. There are three main ways to address storage requirements. At the lowest level, each ATCA blade can have local hard disks, located on the blade itself or on an associated rear transition module (RTM): these could be two redundant serial-attached SCSI (SAS) drives. At the next level, one or more storage ATCA blades could be used within the system. Such storage blades would be accessed via Ethernet using either the FCoE (Fibre Channel over Ethernet) or iSCSI protocols. ATCA storage blades can be shared among mul-tiple processor blades. Finally, an external storage array can be connected via Fibre Channel, FCoE or iSCSI.

Communication, Parallel Processing and MulticoreA key feature of communication applications is their require-ment for high data throughput and packet processing. Also, they typically lend themselves well to parallel processing which is where multicore technology finds its optimal advantage. Although processors from both AMD and Intel are excellent computing devices - especially when multiple Figure 3: A GE Intelligent Platforms ATCA single board computer.

When populated with an 8-core CPU, a full ATCA chassis could contain as many as 224 cores.

Figure 4 An ATCA System with two x86 blades and ten Cavium OCTEON blades illustrates the way packet processors can be efficiently used with general purpose CPUs. ATCA is ideal for mixing multi-multicores.

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cores are considered - both lack the ability to efficiently get data in and out at very high data rates.

Packet processors, another type of multicore processor architecture, are specifically optimized to address the problem of efficiently moving packetized data in and out. Such devices are readily available in the ATCA blade form factor allowing system designers to take advantage of both x86 compute resources and packet processor packet manipulation resources within the same system. The interoperability inherent in the ATCA specification enables designers to plug in multiple x86 processor blades as well as multiple packet processor blades and intercon-nect them via high performance Ethernet interfaces.

From this perspective, Ethernet switches within hubs provide additional value in load distribution. Ethernet switches today employ sophisticated Access Control List features that allow packets, based on their Layer-2 to Layer-4 information, to be steered to a specific ATCA blade. Such policy-based routing allows packet streams to be distributed at very high data rates (10Gbit/sec to 100Gbit/sec) among multiple ATCA blades while ensuring that packets belonging to the same flow are always directed to the same blade. An example of a high per-formance communication system is shown in Figure 4.

From the data processing perspective, data enters the system via Ethernet hubs where packets are dis-tributed - based on policies - among packet processing blades. Then, within the packet processor blade, packets are further distributed between two OCTEON devices and finally, within each OCTEON device, between the cores. The packet processors perform the majority of the high throughput packet processing and specific packets requiring more extensive processing power are forwarded to x86-based blades. The key principle here is that although the majority of packets require little processing, a small subset requires more significant processing power.

Software Development Optimizes All Those CoresIt is clear that any ATCA system is useless without soft-ware. Having hundreds of processor cores offers huge potential, however, unless used efficiently, they are a waste of silicon. Historically, most applications were written without any parallel computing concepts in mind. Consequently, although modern compilers attempt to rec-ognize areas in the code that lend themselves to parallel processing and try to harness the power of multiple cores, performance improvements are very limited when run-ning legacy applications on multicore hardware.

Virtualization is often used today to better utilize mul-tiple processor cores. In a virtualized environment, multiple instances of the operating system – or even multiple dissimilar operating systems - run on the same multicore processor. Since each operating system has no relationship with the other, the operating systems can be happily executed in parallel on multiple cores. Hardware, with the help of a Hypervisor, ensures that each operating system can safely access its own memory and I/O devices without disturbing its neighbors. Virtualization allows the consolidation of multiple physical servers into one server with multicore processors.

ATCA allows further consolidation of multiple blades with multiple multicore processors: racks of legacy servers can be reduced to a single ATCA chassis. Virtualization within the ATCA environment provides another benefit -- redundancy and high availability. Using a high availability virtualized operating system, an application can be migrated from one physical server to the other if hardware failure occurs.

Since packet processors were designed for parallel processing from the start, their software environment and development

tools are fully geared toward application development in a multicore environment. Although Cavium’s OCTEON and similar devices are often called packet processors, internally they are based on standard processor architec-tures such as MIPS64, and can run standard operating systems such as Linux. Their

performance advantages, however, are best exposed when running simplified proprietary operating systems, such as Cavium’s Simple Executive. It is important not to confuse these devices and their operating systems with the network processors of the past, such as Intel’s XScale. Modern packet processors are programmed using standard C and C++ even when their proprietary operating system is being used; in fact, they allow existing C code to be simply ported.

Simplistic applications, such as a packet filter or L-2, L-3 switch, can be developed as sequential code which runs to completion and executes in an endless loop. The same code could be run on all cores, and the parallel nature of the processing would be provided by the hardware itself, which would schedule a packet processing event onto the next available processor core, enforcing packet ordering and atomicity rules if desired. The hardware also takes care of memory management and cache coherency, allowing developers to focus on the application itself. Inter-core communication can be implemented by setting aside a shared memory region or by using a shared variable.

Virtualization allows the consolidation of multiple

physical servers into one server with multicore processors.



Depending on the application and development requirements, a number of software packages can help developers get a head start. One notable example is 6WINDGate software which allows the seamless marriage of x86 processors with packet processors, offloading time-critical tasks to be run by the packet processors’ Simple Executive, and providing a large number of frequently needed protocols. 6WINDGate can be used standalone, or as a base platform for a specific application, and can abstract inter-processor and inter-core communica-tions, significantly simplifying software development effort.

ATCA and Multicore: Well MatchedToday, multicore processors are an integral element of elec-tronics design and are well supported by the AdvancedTCA infrastructure. AdvancedTCA enables very high compute density, without sacrificing reliability and redundancy. Redundant high-speed chassis-wide interconnect options support high performance computing clusters as well as high performance communication applications. Load balancing and policy routing techniques enable packet distribution

among the blades, avoiding bottlenecks and fully utilizing multicore devices. Although most legacy applications can’t take advantage of multicore performance, software tech-niques such as virtualization let multiple legacy applications run on the same processor, taking full advantage of the available multiple cores. Finally, software tools and hard-ware offload elements ease new application development or existing application porting to multicore environments.

Gene Juknevicius is a Technologist and Ar-chitect at GE Intelligent Platforms. He has participated in the PICMG, AMC and Mi-croTCA committees, is currently an active member of the SCOPE Alliance and is responsi-ble for new product definition and architecture at GE Intelligent Platforms. He received his M.S. degree in Electrical Engineering from Stanford University. Gene can be contacted at [email protected].

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Modern wireless service providers are continually pushing for more bandwidth to deliver Internet Protocol (IP) services to more users. Long-Term Evolution (LTE) is a next-generation cellular technology promising to answer this demand by enhancing current deployments of 3GPP networks and enabling significant new service opportuni-ties. LTE’s complex, evolved architecture introduces new challenges in designing and testing network and user equipment. One of the key challenges at the air interface is power management during signal transmission.

In a digital communication system such as LTE, the power that leaks from a transmitted signal into adjacent channels can interfere with transmissions in neighboring channels and impair system performance. The adjacent channel leakage-power ratio (ACLR) test verifies system transmitters are performing within specified limits. Performing this critical test quickly and accurately can be challenging given LTE’s complexity (see sidebar, Complexity in LTE Transmitter Design). Meeting this challenge requires a signal generator with LTE-specific signal creation software, a modern signal analyzer with LTE-specific measurement software and use of optimization techniques for the analyzer.

Understanding ACLR Test RequirementsACLR is a key transmitter characteristic included in the LTE RF transmitter conformance tests. These tests verify that minimum requirements are being met in the base station (eNB) and user equipment (UE). Most of the LTE conformance tests for out-of-band emissions are similar in scope and purpose to those for W-CDMA. However, while W-CDMA specifies a root-raised cosine (RRC) filter for making transmitter measurements, no equivalent filter is defined for LTE by standard. Thus, different filter implementations can be used for LTE transmitter testing to optimize either in-channel performance, resulting in improved error vector magnitude or out-of-channel performance, and in turn, better adjacent channel power characteristics.

Given the extensive number of complex transmitter config-urations that can be used to test transmitter performance, LTE specifies a series of downlink signal configurations known as E-UTRA test models (E-TM) for testing the eNB. The models are grouped into three classes: E-TM1, E-TM2 and E-TM3. The first and third classes are further subdivided into E-TM1.1, E-TM1.2, E-TM3.1, E-TM3.2, and E-TM3.3. Note that the “E” in E-UTRA stands for

“enhanced” and designates LTE UMTS terrestrial radio access, whereas UTRA without refers to W-CDMA.

ACLR test requirements differ depending on whether the transmitter tests are being conducted on UE or eNB. For UE testing, the ACLR requirement is not as stringent as for the eNB. Transmitter tests are carried out using the reference mea-surement channels (RMC) specified for eNB receiver testing.

The 3GPP specifications for LTE define ACLR as the ratio of the filtered mean power centered on the assigned channel frequency to the filtered mean power centered on an adja-cent channel frequency. Minimum ACLR conformance requirements for the eNB are given for two scenarios: adjacent E-UTRA channel carriers of the same bandwidth (E-UTRAACLR1), and UTRA adjacent and alternate channel carriers (UTRAACLR1 and UTRAACLR2, respectively).

Different limits and measurement filters are specified for E-UTRA and UTRA adjacent channels, and are provided for both paired spectrum (FDD) and unpaired spectrum (TDD) operation. The E-UTRA channels are measured using a square measurement filter, while UTRA channels are measured using an RRC filter with a roll-off factor of 0.22 and a bandwidth equal to the chip rate.

Addressing the ACLR Measurement ChallengeGiven LTE’s complexity and the complexity of the transmitter configurations that can be used to test transmitter performance, standards-compliant spectrum measurements like ACLR can be quite daunting. Luckily, sophisticated signal evaluation tools are now available to enable engineers to make these LTE measurements quickly and accurately. Power measurements, including ACLR, are generally made using a spectrum or signal analyzer. The required test signals are built using a signal generator.

To help better illustrate how these instruments can be used, consider the case where, according to the specifica-tions, the carrier frequency must be set within a frequency band supported by the base station-under-test and ACLR must be measured for frequency offsets on both sides of the channel frequency, as specified for paired spectrum TDD operation or unpaired spectrum FDD operation. The test is first performed using a transmitted E-TM1.1 signal, in which all of the PDSCH resource blocks have the same power. It is then performed using an E-TM1.2 signal

Techniques for Measuring ACLR Performance in LTE TransmittersBy Jung-ik Suh, Agilent Technologies

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employing power boosting and deboosting. The E-TM1.2 configuration is useful because it simulates multiple users whose devices are operating at different power levels. This scenario results in a higher crest factor, which makes it more difficult to amplify the signal without creating addi-tional, unwanted spectral content (e.g., ACLR).

In this example, Agilent’s Signal Studio for LTE is con-nected to an Agilent MXG signal generator to generate a standards-compliant E-TM1.2 test signal with frequency set to 2.11 GHz. The output signal amplitude—an impor-tant consideration in determining ACLR performance—is set to -10 dBm. A 5-MHz channel bandwidth is selected from the range that extends from 1.4 to 20 MHz.

Figure 1 shows the eNB setup with Transport Channel selected. A graph of the resource allocation blocks for the test signal appears at the bottom. Channels 1 and 2 are the downlink shared channels-of-interest in the measurement.

Channel 1 has an output power level of -4.3 dB. Conse-quently, its channel power has been deboosted. The output power of Channel 2 has been boosted and is set at 3 dB. A complex array of power boosting and deboosting options can be set for the different resource blocks from the resource block allocation graph. The resulting composite signal has a higher peak-to-average ratio than a single channel in which all blocks are at the same power level. Amplifying a boosted signal such as this can be difficult. Without sufficient back-off in the power amplifier, clip-ping may result.

The test signal can then be generated using Signal Studio software running on an Agilent X-Series signal analyzer. Once created, the waveform is downloaded to the signal generator via LAN or GPIB. The RF output of the signal generator is connected to the RF input of the signal ana-lyzer, where the ACLR performance is measured using swept spectrum analysis. In this example, the signal ana-lyzer is in LTE mode with a center frequency of 2.11 GHz

Figure 1. The resource allocation blocks (at bottom) for the E-TM1.2 test signal are shown here. The Y-axis indicates frequency or resource blocks, the X-axis indicates slots or time, the white area represents Channel 1, and the pink area represents Channel 2. The other colors shown represent the synchronization channels, reference signals, etc.

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and the ACP measurement selected. A quick, one-button ACLR measurement can then be made according to the LTE standard by recalling the appropriate parameters and test limits from a list of available choices (e.g., options for paired or unpaired spectrum and type of carrier in the adjacent and alternate channels) in the LTE application.

For FDD operation, LTE defines two methods of making ACLR measurements: the case in which E-UTRA (LTE) is used at the center and offset frequencies, and the case where LTE is at the center frequency and UTRA (W-CDMA) at the adjacent and alternate offsets. Figure 2 depicts the ACLR measurement result for E-UTRA adjacent and alternate offset channels. For this measurement, a 5-MHz carrier was selected; however, the measurement noise bandwidth is 4.515 MHz, because the downlink contains 301 subcarriers.

Optimizing Analyzer SettingsWhile the one-button measurement previously detailed pro-vides a very quick, usable ACLR measurement according to the LTE standard, signal analyzer settings can be optimized to

achieve even better performance. Four ways to optimize the analyzer and further improve the measurement results are:

• Optimize the signal level at the mixer—Optimizing thesignal level at the input mixer requires the attenuator to be adjusted for minimal clipping. Some analyzers auto-matically select an attenuation value based on the current measured signal value. This provides a good starting point for achieving optimal measurement range. Other analyzers, like the X-Series signal analyzers, have both electronic and mechanical attenuators, and use the two in combination to optimize performance. In such cases, the mechanical attenuator can be adjusted slightly to get even better results, about 1 or 2 dB.

• Change the resolutionbandwidthfilter—Resolutionband-width can be lowered by pressing the analyzer’s bandwidth filter key. Note that sweep time increases as the resolution bandwidth is lowered. The slower sweep time reduces vari-ance in the measurement and measurement speed.

Figure 2. Shown here is an ACLR measurement result using Agilent’s X-Series analyzer. The first offset (A) is at 5 MHz, with an integration band-width of 4.515 MHz. The second offset (B) is at 10 MHz with the same integration bandwidth.



• Turnonnoisecorrection—Oncenoisecorrectionisturnedon, the analyzer takes one sweep to measure its internal noise floor at the current center frequency, and in subse-quent sweeps subtracts that internal noise floor from the measurement result. This technique substantially improves ACLR, in some cases, by up to 5 dB.

• Employ a differentmeasurementmethodology. Instead ofusing the default measurement method (integration band-width or IBW), the filtered IBW method, which uses a sharp, steep cutoff filter, can be employed. While this technique does degrade the absolute accuracy of the power measure-ment result, it does not degrade the ACLR result.

Using these techniques in combination, a signal analyzer can automatically optimize the ACLR measurement for performance versus speed via the analyzer’s embedded

LTE application. For a typical ACLR measure-ment, the results may be improved by up to 10 dB or more (Figure 3). For measurement scenarios requiring the maximum performance, the ana-lyzer settings can be further adjusted.

ConclusionStandards-compliant spectrum measurements such as ACLR are invaluable for RF engineers developing next-generation radio systems. With LTE, however, these measurements are complicated by factors such as variations in the bandwidth of adjacent channels, choice of transmission filter and interaction of RF vari-ables between channels of different bandwidth and different susceptibility to interference. The practical solution to this challenge is to use a spectrum or signal analyzer with a stan-dards-specific measurement application. This combination reduces error in complex measure-ments, automatically configuring limit tables and specified test setups, and ensures measure-ment repeatability. Use of analyzer optimization

techniques further improves measurement results.

Jung-ik Suh began his career in Hewlett-Pack-ard/Agilent in 1997 as a technical support engineer partnering with base station, aero-space and defense, automotive and electronic customers. He also worked with key wireless customers at Agilent and Skyworks solutions as a field sales engineer and a sales account manager, re-spectively. In 2006, he joined the Agilent Asia marketing organization and led various wireless marketing initiatives as Asia wireless program manager. From 2010, Jung-ik has worked for worldwide marketing programs in Agilent Electronic Measurement Group marketing organization. Jung-ik holds a bachelor’s degree in electrical engineering from Kwangwoon University in Seoul, Korea.

Figure 3. Shown here is an ACLR measurement result using Agilent’s X-Series signal analyzer after optimization. An 11-dB ACLR improvement is realized compared to Figure 2, using the embedded N9080A LTE measurement application.

Complexity in LTE Transmitter DesignWith performance targets set exceptionally high for LTE, engineers have to make careful design tradeoffs to cover each critical part of the radio transmitter chain. One important aspect of LTE transmitter design involves minimizing unwanted emissions, and in particular, spurious emissions which can occur at any frequency. While LTE is similar to other radio systems, challenges arise at the band edges where the transmitted signal must comply with rigorous power leakage requirements. With LTE supporting channel bandwidths up to 20 MHz and many bands being too narrow to support more than

a few channels, a large proportion of the LTE channels will be at the edge of the band.

Controlling transmitter performance at the edge of the band requires a design with filtering to attenuate out-of-band emissions without affecting in-channel performance. Factors such as cost, power efficiencies, physical size, and location in the transmitter block diagram are also important considerations. Ultimately, the LTE transmitter must meet all specified limits for unwanted emissions, including limits on the amount of power that leaks into adjacent channels (ACLR).

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AdvancedTCA (ATCA) has seen successes from two-slot development/networking applications to five- to six-slot mid-size to the “full” 14-slots for 19-inch rack-mount shelves. Until recently, the mid-size range of 5U to 8U has been mostly reserved for networking and telco applica-tions where the slot size was right or they allowed enough expansion options. Plus, now that the military market has increasingly been adopting ATCA, the mid sizes offer sig-nificant design flexibility for various applications.

The mid-size ATCA chassis of 5U to 8U has always had side-to-side cooling. This was a barrier in achieving NEBS compliance and a problem in other applications where front-to-rear airflow was either strongly preferred or a requirement. Today, there are new mid-sized solutions which vastly improve the computing density of ATCA sys-tems and solve some of the long-standing hurdles to being used in telco and other embedded applications.

The Mid-Size BarrierThe mid-sized chassis should be a very popular size for AdvancedTCA, but traditionally there have been some bar-riers. The 5U/6U height ATCA chassis holds a five- or six-slot backplane. With typically two slots (for redundancy) dedi-cated as switch slots, this leaves only three or four slots for payload. With a two-slot ATCA system (in 2U or 3U height), the routing is point-to-point without the use of switches. Thus, two 3U high ATCA chassis with two slots each gave the same amount of payload slots (four) as one 6U enclosure. This was without the additional costs of the switches, etc. On the other hand, going to a 14-slot enclosure in a 13U to 15U height was another option. Often, the 14-slot shelf is not fully subscribed, wasting valuable rack space and increasing costs. Today, there are solutions that overcome these traditional barriers.

Size Does MatterNew ATCA shelf solutions are allowing ways to greatly increase performance in the mid-sized chassis. One method is to integrate the switch fabric functionality into redundant shelf managers. Thus, the two slots that are usually dedicated switch fabric slots in the ATCA shelf are saved and can be utilized as standard payload (node) slots. Rather than uti-lizing only four payload slots in the 6U shelf, there are a full six slots available. This effectively increases ATCA computing density by 50 percent. See Figure 1 for an example of this

type of space-saving design. Note that this same six-slot configuration can be achieved in a 5U height for DC-only applications. For AC applications, it is typical to increase the height to 6U to allow for single or dual AC power supplies. AC power (or dual AC/DC power) is a key requirement for the flexibility of use in a wide range of applications outside of the central office. It is more conductive to medical, data center, networking and some mil/aero applications.

Now, let’s compare this 6U horizontal-mount configuration with a typical vertical-mount 13U configuration with 14 slots. The vertical-mount shelves commonly use a dual-star configuration. A 14-slot mesh routing is certainly possible, but it can increase costs and be overkill for that many slots. Utilizing the dual-star means that two slots are reserved for switching, leaving 12 slots for payload. For the five- to six-slot horizontal backplanes, a dual-star configuration is also commonly implemented. However, we typically route them in a mesh configuration as it doesn’t add layers or costs in that size. Plus, the dual-star architecture can be implemented across the same backplane.

As you can see in Table 1, there is more functionality in less space with a 5U or 6U horizontal chassis than a 13U vertical chassis. Plus, if you are utilizing all of the slots, you are maximizing rack space/usage and ROI.

The Case for Optimal Mid-Sized Shelves for AdvancedTCA ApplicationsThe doors have opened with new possibilities in mid-sized ATCA shelves, which are gaining traction in applications such as military, data center and telco designs.By Justin Moll, Pixus Technologies

Figure 1: The 6U ATCA SlotSaver Chassis with AC/DC power has a configura-tion that combines the functionality of the switch cards and shelf management.This allows two extra payload slots, increasing computing density by 50%.

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NXP_03_0135_TDA5051A_939775016978_v4.indd 1 12/08/10 17:15

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Offer customers a universal control panel that’s worthy of being the command center for the home. Not only will they be able to better manage their energy usage and benefit from smart thermostats, they can download wide-ranging applications, like

Feature-RichEnable your customers to manage energy consumption by providing them with a home command center, or Dashboard, that recommends solutions, sets effective goals and helps household members make optimum decisions when implementing efficiency measures. The device can support demand response and complex pricing structures in addition to a range of services, some of which could create new revenue streams. With the touch of a button, the flexible home control and energy management panel displays weather, records family video messages, arms the security system, indicates energy usage and sets the temperature, just to name a few functions (Figure 1).

Figure 1. Example Applications

Energy Management> Indicates energy usage> Makes recommendations

Comfort> Sets temperature> Helps reduce energy usage

Weather> Reports weather conditions> Shows the extended forecast

Family Message Board> Records video messages> Sends out messages

Home Surveillance> Controls security system> Displays webcam streams

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Faster and HotterAnother factor that affects AdvancedTCA systems is the usage of more powerful processors, which generate tremendous heat. Some applications are using dual Intel Sandy bridge chips on a board, creating sig-nificant heat buildup. It’s not uncommon to see demands of 325W/front slot or more as we approach the barriers of physics in forced-air cooling, balancing airflow, acoustic noise limits, static pressure, etc. Plus, the rear transition module (RTM) area is now creeping up to the 40-80W/slot levels. In many cases, the only feasible solution is to increase the chassis height. For carrier-grade telco central-office applications, which require NEBS-compliance, front-to-rear cooling is a requirement. This traditionally has required the vertical-mount chassis. With air intake below the card cage and exhaust out the rear, the chassis have increased in size over the years. In fact, there are 15U ATCA shelves entering the market that are geared to cool 400W/slot.

Let’s take our chart from Table 1, and in applying the new cooling paradigm, review the results:

It should be noted however, that the 6U horizontal mount can cool approximately 325W/slot and cannot cool on the level of 400W of the 15U. Further, the 6U utilizes side-to-side cooling. But, what if this chassis configuration had front-to-rear cooling? Is that possible?

Front-to-Rear Cooling for a Horizontal Mount ATCA ShelfWe’ve seen the benefits of the mid-size for 6U shelves with side-to-side cooling. But what if we could provide front-to-rear cooling in a horizontal configuration? This is possible by employing a rear heat extractor. With the air intake at the front, air travels down the sides of the shelf then over the blades and forced out of the rear while impellers pull the heat to the back and out of the rear of the enclosure. However, to achieve this effectively for 300W+ applica-tions, the chassis height in this case needs to go to approximately 8U. Compared to a traditional ATCA system, where there are only four payload slots available, this is still an attractive size. Using the

same combined shelf manager/switch configuration, you are still getting six payload slots in an 8U height – which is about par with the traditional approach. But now it is possible to maintain and even increase performance den-sity in an 8U NEBS-compliant shelf with a front-to-rear cooling solution. In addition, a full mesh 40G backplane offers even more performance density.

The heat extractor needs to be carefully placed to optimize cooling performance. With thermal simulation/testing, the

optimum position can be found so that hot spots can be prevented. As we’ve seen with ATCA’s thermal trends, it is critical that the front-to-rear cooled ATCA shelf be able to dissipate 325W/slot. As with the 6U shelf, the 8U NEBS-level ATCA chassis can be configured for full high availability (HA) redundancy across all FRUs – including power modules, shelf managers/telco alarm, cooling units and switches.

The Mid-Sized StoryMid-sized AdvancedTCA shelves are gaining traction in applica-tions such as the military, where AC/DC versions offer an attractive size/performance solution. Now that the computing density can be significantly increased, one would expect further gains in adoption rates in various applications, including the data center. Further, with front-to-rear cooling for a horizontal ATCA shelf, the mid-size also become not just viable, but quite attractive for Telco designs.

Justin Moll has been with Pixus Technologies since early 2012 as vice president for US market develop-ment. Previously, he was director of marketing at Elma Bustronic, and has worked in the power connector in-dustry at Elcon Products International (now a part of Tyco Electronics Connectivity).Justin has served as VP of marketing for the StarFabric Trade Association, Chair of the VXS Marketing Alliance at VITA, at has been a guest speaker at several industry events. Justin has a B.S. in business administration from UC Riverside. www.pixustechnologies.com

Chassis Type & Height

Mounting Total Slots

Payload Slots

Payload Slots/U

15U Dual Star

Vertical 14 12 .80

6U Dual Star AC

Horizontal 6 6 1.0

5U Dual Star DC

Horizontal 6 6 1.2

Table 2

Today, there are new mid-sized solutions which vastly improve the computing density of ATCA

systems and solve some of the long-standing hurdles to being used in telco and other

embedded applications.

Chassis Type & Height

Mounting Total Slots

Payload Slots

Payload Slots/U

13U Dual Star

Vertical 14 12 .92

6U Dual Star AC

Horizontal 6 6 1.0

5U Dual Star DC

Horizontal 6 6 1.2

Table 1

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After more than a decade of acquisitions and shake-ups, many OEMs are enduring the costs of maintaining multiple hardware platforms and face challenges to drive core product development across dissimilar technology bases. Enter the “Common Platform” strategists who are often confronted with making inter-divisional peace whilst preparing for the next generation platform rollout. This can be tough when competition is ahead of the game and a leap in technology is needed to catch up to deploy next generation services. One way to play leapfrog is to adopt commercial off-the-shelf systems and blades. ATCA is a solid choice for any common platform strategy, where products are required to scale and span several price performance tiers. A healthy ecosystem of vendors exists providing a broad product choice and ensuring competitive pricing. Moreover, 40G ATCA allows OEMs to address their cur-rent bandwidth dilemma and provides the headroom needed to scale their products over time to meet increasing packet processing needs. It certainly helps to mitigate risk more than any other cur-rent architecture.

Benefits of a Common PlatformFor a Network Equipment Provider (NEP), establishing a common platform provides a more cost efficient method for shared product management and a combined strategy across product lines with shared upgrade paths. Product groups can focus on the added value of their individual business without being distracted by base plat-form support. By sharing engineering resources, an efficient and effective development process can be planned whilst leveraging, wherever possible, the lowest cost. Moreover, establishing a best practice and authority on a single platform creates central expertise which can be shared across the organization. Strong interworking control processes help ensure that the platform remains stable and operational. With scalability as a key consideration and by adopting a common platform strategy, a product line can be built out with longer-term scalability considerations built in.

Balancing Differentiation with CommonalityIt’s important to find the balance between commonality and dif-ferentiation. Zero commonality usually means customization for a market where costs are almost impossible to reach any other way. This is often where the debate begins for MicroTCA which scales down from ATCA in all respects, but frequently doesn’t meet the higher volume, lower-cost needs unless seriously cost-optimized. It does however frequently serve for rapid prototyping due to the diversity of available AMCs. Chip manufacturers often choose AMCs to build reference designs for new silicon. This make them compelling for a leapfrog technology insertion strategy with con-trolled cost down transitions depending on market acceptance. However as die sizes shrink and performance increases, so does the system platform. Solutions which may have been deployed across several blades are rapidly being consolidated on to just one.

For example there’s more packet processing power on Advantech’s latest generation ATCA blade based on the Intel® Xeon® E5-2600 than in a fully-loaded 6-slot system of 5-years ago. This increase in miniaturization needs to be accompanied by a similar trend at the mezzanine level in order to bring more I/O and acceleration closer to the processing core to allow a single ATCA blade to become in itself, the new entry-level system. Flexible fabric connectivity is required in order to match processing performance with I/O needs for system scale up.

Fabric Mezzanine Modules (FMM) as Common DenominatorThe FMM concept addresses the above needs and is one of the key elements in Advantech’s Customized COTS (C2OTS) strategy. FMMs are a new denominator for personalizing a common plat-form at the blade level. They scale extremely well for both I/O and acceleration functions. The MIC-5333 ATCA blade based on Intel’s next generation communications platform codename Crystal Forest houses three FMM sites on the front blade and between one and four FMM sites on the rear transition module enabling a wide variety of solutions.

FMMs also facilitate fabric interface flexibility allowing equipment providers to deploy the MIC-5333 into 40G or 10G topologies. A double-sized FMM carrying four i82599’s provides two fabric interfaces with four 10GBaseKR ports each. For designers requiring 40GBaseKR4 interfaces, a Mellanox CX-3 FMM supports two 40G ports enabling dual dual-star backplane architectures with two FMM modules for four times 40Gbps in and out of the blade. Finally a single i82599 FMM makes it possible to adapt MIC-5333 with 10GbE in order to upgrade legacy systems in the field.

The FMM specification defines the high speed interfaces and asso-ciated FRU management. In addition the specification supports a

A Common IA Platform for Workload Consolidation on ATCABy Paul Stevens, Advantech Europe BV

Figure 1 MIC-5333 ATCA Blade from Advantech - A common platform for workload consolidation based on the Intel Xeon E5-2600 Series with FMM sites for 40G Fabrics

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ContaCt InformatIon

[email protected]/nc

zone 2 connector interface for custom fabric connectivity like SRIO. Signal integrity ensured via are-driver between the zone 2 connector and the FMM. A FRU EEPROM on the FMM describes its thermal & power requirements and zone 2 interface information. All other aspects are managed by a BMC on the ATCA blade. FMMs are com-pact, just 7 x 7.5 cms and use FMC compliant connectors for high speed differential I/O. There is adequate space to fit 40mm BGA ASICs and FPGAs and associated components with a thermal budget < 20W. The I/O area provides overhang for connector support on front panels or rear transition modules (RTM) making FMMs a good fit for specialized processing close to the application I/O.

With a common platform for workload consolidation like the MIC-5333, up to 7 FMM sites provide a wide choice of PCIe I/O and acceleration:

• MIC-5333 3FMMs(2Fabric,1FrontPanel)• RTM-5104 1FMMtoRearPanel• RTM-5106 4FMMstoRearPanel

In fact there are sufficient FMMs to turn the MIC-5333 common platform into a 100G line card with crypto acceleration.

By adopting an FMM approach for standard and custom designs, OEMs can effectively redeploy them across form factors scaling from appliances to ATCA systems for functions such as:

• Proprietaryaccelerationhardware• Specializedcodingandtranscodingalgorithms• Signal&imageprocessing• Military&commercialcryptography• Flowprocessingandpacketfiltering

Make and Buy – the best of both worldsBefore going down a “Make” path, OEMs should consider the benefits of ATCA, Customized COTS and FMMs as a potent “Make and Buy” compromise for the best of both worlds. As workload consolidation becomes a reality so does a common platform based on ATCA, and for individual blade personalization FMMs offer the broadest flexibility for mass customization in the integration and build-to-order process of final products.

Figure 2 Advantech’s RTM-5104 provides one further FMM site with PCIe x16 to the front blade for expansion

FMM-5001BIntel 82599ES with 2

x 10GBaseKX4 FI

FMM-5001FIntel 82599ES for 2 x

10GbE with dual SFP+

FMM-5001QQuad Intel 82599ES with

8 x 10GBaseKR4 FI

FMM-5002Server Graphics Controller

with VGA connector

FMM-5004MMellanox CX3 with 2

x 40GBaseKR4 FI

FMM-5006Intel QuickAssist

Accelerator

Figure 3 Examples of FMMs


OvERvIEW

Introducing the New Comtel CO14N-AC, 14U, 14 slot 19” shelf, which is based on the original CO14N-DC shelf with integrated 1U power supply extension.

FEATURES

• 19” Rackmount 14U system

• 14 slot 8U front boards and RTM

• Full Mesh, Dual Star and Dual-Dual Star topologies

available in new Enhanced designs for wider margins

• 40GBASE-KR4 and 10GBASE-KR/10GBASE-KR4

• Dual redundant Pigeon Point Based Shelf Manager

• 5 redundant (N+1) power supplies, each 1600W

• Pull cooling with four hot-swap redundant Blowers

• High Reliability bussed IPMI to PSU’s with PMBus

• Fully PICMG 3.0 Rev 2.0 compatible

• Designed for compliance to NEBS and EN levels

• Air inlet filter with optimized air impedance

BEnEFITS

• 8000W total power, 6400W redundant

• Power distribution more than 300W per slot

• Highly efficient packaging with up to 300W per slot

cooling in an abbreviated 14U form factor

• RTM cooling up to 30W per slot

• High performance Backplane exceeds AdvancedTCA®

specification

• CE and UL Safety Certifications

• Bezel for Front Air Inlet

ACCESSORIES

• Front and Rear Cable Trays

• 23” Mounting Brackets

• Low cost and light weight EMC filters & airflow blocking

modules

• Custom Zone-3 backplanes available

DIMEnSIOnS

AdvancedTCA® CO14N-AC14U, 14 slot Shelf with AC Power

By COMTEL ELECTRONICS

Height 620.0mm (14U)

Width 445.0mm (with ears 485.6mm)

Depth 507.0mm

Weight 47 kg (with 5 PSU)

Colors: Standard: Black powder painted

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BLOWERS

• Cooling direction bottom front to upper rear side

• Blowers speed setting by T-sensors via IPMI

• Fuses for each Blower Unit

• T-Sensor for air outlet and separate ambient

• Cooling capability: up to 300Watts/slot

• Communication by IPMC

PEM

• Built-in PEM for protection and power distribution

• Shared current split into 8 power backplane segments

over Circuit Breakers (4xA-Channel and 4xB-Channel)

• No need for service due to Circuit Breakers

• Optional PEM Monitoring FRU (continuously

monitors Circuit Breakers state)

SHELF MAnAGEMEnT COnTROLLER

• Pigeon Point Systems IPM Sentry Shmm500

• Fully hot swappable

• PMBus support over private I²C Bus

• PMBus interface available on the backplane connector

and front panel

• Remote upgrade capability

• RMCP interface and SNMP interface

FRU DATA BOARD/TELCO ALARM BOARD

• FRU data board to carry the Shelf FRU data information

• Assembly option for TELCO Alarm function (Relays

contacts, Alarm indication LEDs)

• Telco indication in front of the shelf over

additional board

• Communication by IPMC

POWER SUPPLy BAy

• Provisions for 5 PS modules in 19” shelf

• No external wiring, only AC power cords

• Individual AC inlet for

each module

• Up to 6400W (4+1)

POWER SUPPLIES

• High Efficiency 1600W

Modules (1250W low line)

• Internal ORing MOSFET & Current Share

• PM Bus capable

• Presence, AC Failure, Power OK are monitored

• Built-in locking mechanism and service handle

ContaCt InformatIon

COMTEL ELECTRONICSwww.comtel-online.comnasales@comtel-online.com619-573-9770

www.eecatalog.com/atca Hardware•35

ContaCt InformatIon

Adax Inc.

Adax Inc.2900 Lakeshore AveOakland, CA 94610USA+1 510-548-7047 Telephone+1 510-548-5526 [email protected]

◆ Processor: • Cavium Octeon Plus CN5650, 12 Cores at 750 MHz • Cavium Octeon Plus CN5430, 4 Cores at 700 MHz

(option)◆ Ethernet Controller: • APR: Broadcom 56513 • Fullwire speed switching for 24 1GbEs and 3 10GbEs • APR+: Broadcom 56639 • Full wire speed switching for 7 10GbEs and 14 1GbEs◆ Memory: • 2, 4 or 8 GigaBytes of DDR2 Memory (2GB standard) • 32MB of Flash Memory • Compact Flash disk◆ Interfaces: • 4 AMC bays, each with 4x 1GbE & 1x PCIe (APR)

and 1x 10GbE, 2x 1GbE & 1x PCIe (APR+) • 1 front-panel micro-USB port • 1 micro-USB to the Cavium • 2x 1GbE to Base • 2x 10GbE to Fabric

AvAILABILITy

Available Now

APPLICATIOn AREAS

• Policy Control/Enforcement • Lawful Intercept • Data Optimisation • Data Offload • Backhaul & Aggregation • QoS • Traffic Management • SMS, Roaming, Ring Tones, Billing • Monitoring, Test, Measurement • Control & User plane Interworking • IP Tunneling, Switching, Routing & Backhaul

Adax PacketRunner Intelligent ACTA Carrier Blades

Compatible Operating Systems: Linux

Specification Compliance: Standards: • PICMG ATCA 3.0 and 3.1, Region 3 Option 9 • IPMI v1.5 • IEEE 802.3 • Designed to meet Belcore GR-63-CORE

The Adax PacketRunners (APR and APR+) are intelligent, Cavium-based, 4-bay ATCA carrier blades for telecom applications. The on-board Cavium OCTEON 5650 multi-core processor with memory and cache gives developers a high performance, highly flexible and scalable blade for LTE, 4G, and all other demanding telecom network appli-cations. The APRs deliver the perfect ATCA subsystem for secure user and control plane applications.

The APRs uniquely offer I/O and processing scalability with access to the host Cavium. All at a viable price point for IP transport, packet processing and signaling on a single blade without the need for a general CPU or ProcessorAMC. This is the industry’s most cost-effective, multi-purpose solution in one tightly coupled resource.

The flexible architecture of the Adax PacketRunner fulfills ATCA’s promise of horizontal expansion at a reduced cost. In a redundantly designed system, cards and blades may be added, removed, and reallocated with no loss of service and network operators are able to retain the value of their initial CAPEX investment well into the future.

FEATURES & BEnEFITS

◆ Cavium OCTEON Plus CN5650, 12 cores at 750MHz - Option for CN5430, 4 cores at 700 MHz

◆ QuickPort: • Pre-built kernel and Debian file system • Pre-installed Adax software; Linux Streams

(LiS), SIGTRAN, HDC3 and ATM4 board drivers • A development environment • Set-up instructions and support◆ 4 AMC bays for Adax and/or 3rd party mid-size AMC cards◆ 2 GB of DDR2 Memory - Options for 4 GB and 8 GB

DDR2 Memory◆ Ethernet Switch: APR - 4x 1GbE to each AMC bay APR+

- 1x 10GbE and 2x 1GbE to each AMC bay Common to APR/APR+: - 2x 10 GbE to Fabric domain - 2x 1 GbE to Base domain - 10 GbE from Cavium to switch

TECHnICAL SPECS

◆ Standards: • PICMG ATCA 3.0 and 3.1, Region 3 Option 9 • IPMI v1.5 • IEEE 802.3 • Designed to meet Belcore GR-63-CORE

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36•Hardware Engineers’ Guide to ATCA® & MicroTCA Technologies 2012

ContaCt InformatIon

ContaCt InformatIon

Advantech


◆ 40 GbE (KR4) and four 10 GbE (KR) FI with Dual Star routing support

◆ Eight 10GbE SFP+ and four 1GbE SFP Rear I/O support◆ Switch management support on L2, QoS, Multicast

(SW options)

ATCA-7310 Dual Cavium® Octeon® II Cn6880 node Blade with 40G switch

Based on the Cavium Networks CN6880 OCTEON® II processor the high-end ATCA blade features dual proces-sors 32 MIPS64® cores for a total of 64x 64-bit cores per blade. The ATCA Packet Processing Engine is targeted at high-end control, service and dataplane applications in 4G/LTE networks, video and data applications typical of cloud computing and security applications using Deep Packet Inspection (DPI). The ATCA-7310 supports up to 64GB of DDR3-1066 memory with a Broadcom BCM56841 40GbE switch. Four 10G/40G Fabric inter-faces (40GBaseKR4, 10GBaseKX4) are supported with 12 lanes of 10GbE to the RTM for uplinks. The blade also provides support for dynamic clock and cores manage-ment, console server, remote upgrade and LMP boot image supporting HPM.1.

FEATURES

◆ Dual Cavium Octeon II CN6880 1.0 GHz with 32 MIPS™ II processor cores

◆ Up to 64 GB DDR3 1066 MHz DIMMs; 32 GB for each CN6880

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Advantech


◆ Eight DDR3 VLP DIMMs up to 256 GB with ECC support◆ Up to four XAUI ports on Fabric interface and two

1000BASE-T ports on Base interface◆ One Fabric Mezzanine Module support with front I/O

support (type II)◆ Two CFast / one 2.5” SSD storage Device

MIC-5332 AdvancedTCA® 10GbE Dual Socket CPU Blade with Intel® Xeon® E5-2600 Processors

The MIC-5332 is a dual processor blade based on the Intel Xeon E5-2600. It enables the highest performance available in ATCA form factor with up to 16 cores and 32 threads of processing power, fast PCI Express gen. 3 lanes at up to 8Gbps, and best in class virtualization support. Four DDR3 DIMMs per socket in a quad channel design running at up to 1600MT/s gives superior memory bandwidth and up to 256GB LR DIMMs capacity. It outper-forms previous dual socket designs while keeping similar thermal characteristics with balanced airflow resistance.The integrated 4-port SAS controller eliminates the need for an external storage controller. Support for dual dual-star fabrics can be added by installing the FMM-5001B Fabric Mezzanine Module (FMM). An FMM type II socket with PCIe x16 connectivity provides extension for addi-tional front port I/O, and acceleration controllers.

FEATURES

◆ Two Intel® Xeon® E5-2600 Processors and Intel® C600 Series PCH server class chipset

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Advantech

FEATURES

◆ 20 Texas Instruments TMS320TCI6608 DSPs◆ 512MB DDR3 memory per DSP◆ BCM56321 10GbE switch for both Fabric Interface

and Base Interface◆ Freescale QorIQ™ P2020 for Local Management

Processor (LMP)◆ IDT Tsi577 Serial RapidIO switches

MIC-8901 ATCA® DSP Blade with 20 TMS320TCI6608 DSPs

With its 20 onboard TMS320TCI6608 DSPs at 1.0GHz core frequency, the DSPA-8901 provides 160 cores of pro-cessing power to reach the performance density needed to build the highest capacity media gateways. The DSPA-8901 reduces overall system power dissipation and cost, and frees up valuable slots in gateway elements for additional subscriber capacity and throughput. The DSPA-8901 includes a high-performance Freescale QorIQ P2020 processor. A Broadcom BCM56321 switch terminates the 10 GbE fabric connections and distributes traffic to the 20 DSPs. The DSPA-8901 offers unrivalled packet and media processing capabilities. For increased demand in high-end video conferencing, broadcasting and tele-presence, the DSPA-8901 ATCA blade offers unmatched image processing performance for compres-sion and decompression, image analysis, filtering and format conversion.


ContaCt InformatIon

ELMA


ContaCt InformatIon

ContaCt InformatIon

Emerson network Power

◆ Hardware off-loading functions for en/decryp-tion, compression, pattern look-up

◆ Multiple software pack-ages including operating systems & sophisticated, next generation Blade Management Controller software

APPLICATIOn AREAS

Telecom server systems, control and data plane work-load consolidation, deep packet inspection applications such as network optimization platforms and session border controllers

ATCA-7370 Dual Intel Xeon Processing Blade

The Emerson ATCA-7370 uses dual 8-core Intel Xeon processors E5-2600 in a blade design optimized for com-pute and thermal performance. Designed for NEBS and ETSI compliance, it can also be deployed applications both in telecom central offices and network data centers. The ATCA-7370 is built for maximum compatibility with commercial off the shelf software and it supports the use of higher performance processors in temperature-managed environments. While it provides outstanding capability in control plane applications, Emerson’s new ATCA-7370 is designed to provide future support for the next generation communications platform from Intel, codename Crystal Forest, to enable workload consolida-tion across the control and data planes.

FEATURES

◆ Two 8-core Intel® Xeon® processors E5-2648L, 1.8 GHz

◆ Up to 128GB main memory and hot-swappable hard disk with flexible choice of storage options

◆ Multiple network and storage I/O connectivity

BladesBlad

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◆ ‘Gateway-on-a-blade’ architectures for small systems - providing DSP, packet and X86 processing on each blade

◆ ‘Pay-as-you-grow’ capability with field-upgradeable DSP expansion options

◆ Supports TDM applications via RTMs, including vari-ants with multiple OC/3 and OC/12 line terminations

ATCA-8310 DSP/Media Processing Blade

The ATCA-8310 from Emerson Network Power is a state-of-the-art AdvancedTCA® DSP/Media Processing platform designed to provide power-efficient, high-density voice and video transcoding functions. The blade features a uniquely flexible mix of processing tech-nologies. In a fully expanded voice configuration, the ATCA-8310 is capable of handling over 8000 channels of TDM to compressed (G.729AB) Voice over IP conversion including tone detection and echo cancellation, or over 6000 channels of GSM-AMR mobile voice transcode in a single ATCA slot. The ATCA-8310 is also ready for video transcode and transrate applications, estimated to be able to handle up to 350 individual mobile video streams per slot.

FEATURES

◆ High processing density with up to 180 DSP cores on a single blade

◆ ‘DSP farm’ architectures for scalable voice and video gateways based on multiple blades

Emerson Network Power 2900 South Diablo Way, Suite 190Tempe, AZ 85282USA+1 602 438 5720 Toll Free+1 800 759 1107 Telephone +1 602 438 5825 [email protected] Emerson.com/EmbeddedComputing



ContaCt InformatIon

ContaCt InformatIon



◆ Up to 350 Watts/blade power distribution◆ Designed for NEBS/ETSI or network datacenter

APPLICATIOn AREAS

wireless infrastructure, mobile data optimization, net-work policy enforcement and access control, voice core elements, media gateways, session border controllers

Centellis™ Series ATCA® Systems

Emerson has been supplying integrated, application-ready ATCA® systems under the Centellis™ name for over 10 years. Our unrivalled experience and expertise is why new research reports that Emerson is number 1 in ATCA market share and installed base. Our Cen-tellis systems include 2-slot, 6-slot and 14-slot variants designed to meet the needs of telecom central office environments. As the only major ATCA systems vendor that designs and manufactures its own chassis, Emerson understands how to build systems that are capable of meeting your requirements. We also have the only 2-slot and 6-slot systems available with AC power options and front-to-rear cooling, meeting the needs of both central office and network data center deployments.

FEATURES

◆ 40G systems with 2-, 6- or 14-slots◆ Best-in-class cooling, exceeding CP-TA B.4 thermal

specification◆ AC or DC power input options

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ContaCt InformatIon

Scan Enginnering Telecom GmbH

Scan Enginnering Telecom GmbHElisabethstrasse, 91Munich, 80797Germany+49 89 5908 2347 Telephone+49 89 5908 1200 [email protected]

TECHnICAL SPECS

◆ Four high-performance TI TMS320C6457 DSPs, each running up to 1.20GHz

◆ Peak performance 38400MIPS◆ Integrated Viterbi and turbo-code processors ◆ Total DDRII memory capacity 512/1024MB◆ 2 x Gigabit Ethernet and 2 x Serial RapidIO x4 on

AMC edge connector

AvAILABILITy

Available now

APPLICATIOn AREAS

Gateways, Media servers, Security appliances, Broad-cast, Data Processing, Industrial Automation, Medical Imaging, Wired Communcations, Wireless Communica-tions, Wireless infrastructure

SAMC-404 High-performance DSP boardCompatible Operating Systems: Windows, Linux

Specification Compliance: AMC.0 R2.0, AMC.2, AMC.4

The SAMC-404 Single Mid-/Full-Size AMC board is a high performance computing module for use in AdvancedTCA® and MicroTCA™ systems. Designed around high-performance TI TMS320C6457 DSPs, com-bining a wide range of fabric interfaces and colossal amount of memory, it provides exceptional computing power and performance in the convenient and versatile AdvancedMC™ form factor.

The SAMC-404 complies with the most current PICMG® specifications for operation in ATCA and MicroTCA applications. This module supports sub-specifications to insure compatibility with the broad set of interface options presented by AMC carriers – including Ethernet and Serial RapidIO. SAMC-404 gives OEMs in a broad range of industries a high-performance and cost effec-tive solution for reducing size, complexity, risks and costs associated with leading-edge software-defined radio (SDR), networking, telecommunication, data pro-cessing, industrial and medical applications.

Scan Engineering Telecom can also provide custom-ization, turnkey integration and support to ensure that OEMs can focus where they prefer to add their own unique value.

FEATURES & BEnEFITS

◆ High-performance AdvancedMC DSP board◆ 4 TI DSPs provides exeptional peak performance◆ A very cost-effective computing platform for

AdvancedTCA and MicroTCA solutions◆ For OEMs in telecom, datacom, industrial, medical

test & measurement and aerospace industries◆ Customization welcomed

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ContaCt InformatIon



TECHnICAL SPECS

◆ Intel 2nd Generaiton Quad-Core Core-i7 CPU operat-ing at 2.10GHz

◆ Up to 8GB soldered 1333MHz DDRIII memory with ECC support

◆ Up to 128GB SATAII SSD drive◆ 2 x PCI Express Gen2 x4/Serial RapidIO x4/XAUI

lanes, 2 x PCI Express Gen2 x4 lanes, 2 x Gigabit Ethernet, 2 x SATAIII on AMC edge connector

◆ Front panel interfaces – HDMI, 2 x Gigabit Ethernet, 2 x USB 2.0, 1 x Serial

AvAILABILITy

Q2’2011

APPLICATIOn AREAS

Telecom – Edge applications, next-generation convergent media gateways, media servers, messaging servers, ses-sion border controllers, WiMAX and LTE base stations Datacom/Enterprise computing – Routers/gateways, network security/firewall appliances, switches Industrial – Embedded controllers, co-processor applications Med-ical – Imaging, X-Ray, Ultrasound Instrumentation – Test & Measurement systems Aerospace – Avionics and ship-board platforms, Communication systems, Real-Time Intelligence systems, Simulators

SAMC-514 Quad-core Processor AMC based on Core i7Compatible Operating Systems: Windows, Linux

Specification Compliance: AMC.0 R2.0, AMC.1, AMC.2, AMC.4

The SAMC-514 Singe Full-Size Processor AMC board is the second generation of SET’s high-performance Quad-Core Processor AMC boards.

The SAMC-514 is intended for use in AdvancedTCA® and MicroTCA™ systems. Designed around 2nd Genera-tion Intel Core i7 CPU (Sandy Bridge), combining a great amount of soldered DDRIII memory and unsurpassed range of fabric interfaces, it provides exceptional com-puting power and performance in the convenient and versatile AdvancedMC™ form factor.

The SAMC-514 complies with the most current PICMG® specifications for operation in ATCA and MicroTCA applications. This module supports sub-specifications to insure compatibility with the broad set of interface options presented by AMC carriers – including SAS/SATA, Ethernet, PCI Express. It also features an onboard SATA SSD disk drive and option for Serial RapidIO/XAUI system interconnect for extend typical application areas.

SAMC-514 gives OEMs in a broad range of industries a higher performance and cost effective solution. Scan Engineering Telecom can also provide customization, turnkey integration and support to ensure that OEMs can focus where they prefer to add their own unique value.

FEATURES & BEnEFITS

◆ High-performance AdvancedMC processor module with broad range of front and rear connection options

◆ Support options for system interconnect via PCI Express Gen2, SATAIII, Serial RapidIO Gen2 and XAUI

◆ A very cost-effective computing platform for AdvancedTCA and MicroTCA solutions

◆ For OEMs in telecom, datacom, industrial, medical test & measurement and aerospace industries

◆ Customization welcomed

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ContaCt InformatIon

Pinnacle Data Systems, Inc., An Avnet Company

TECHnICAL SPECS

◆ AMD Opteron processors supported include power efficient embedded dual-core, quad-core and hex-core models

◆ 4 x DIMM sockets enable up to 32GB DDR2 ECC Memory

◆ Front Panel Interfaces: 2 x GbE ports, 2 x USB 2.0 ◆ Backplane Interfaces: 2 x GbE Base and 2 x GbE

Fabric, supports dual-star backplane topology ◆ AMC slot for HDD or I/O expansion, plus optional

onboard Compact Flash

AvAILABILITy

Now

APPLICATIOn AREAS

Targeted at Military, Aerospace and Defense applica-tions requiring the ultimate in computing capability and dependability, such as Shipboard Application Servers, Avionics Platforms, and Communications Servers.

ATCA-F1 Dual AMD Socket F AdvancedTCA BladeCompatible Operating Systems: Linux (SuSe, RHEL), Windows (Server 2003, XP), Solaris x86, VMware ESX Server 3.5 and 4.0

Specification Compliance: PICMG ATCA3.0 R2

PDSi’s Dual AMD Opteron™ ATCA® Blade with RTM Inter-face (ATCA-F1) is a military-proven, high-performance general purpose server platform for AdvancedTCA® systems. Architected around AMD Opteron processors with HyperTransport™ technology, it features two CPU sockets that can be populated with the latest AMD 2419 EE “Istanbul” 1.8GHz six-core processors, for a total of twelve-cores. PDSi’s ATCA-F1 blade supports up to 32GB of 667MHz memory.

This third generation blade features a Zone 3 interface for connection to PDSi’s ATCA-RT01 rear transition module (RTM), which adds SAS or SSD storage, video, and USB resources. Other on-blade features include a Compact Flash site and an AdvancedMC™slot for additional I/O or further storage expansion. See PDSi’s AMC-E24D module for an excellent space-saving AMC combining SATA storage and dual hi-res video.

PDSi gives telecom, aerospace, and military OEMs and integrators the ability to deploy configurable, scalable, high-reliability twelve-core ATCA solutions using this powerful compute blade based on AMD’s Istanbul and Shanghai processor technologies. Extended availability from PDSi is assured as key components are supported by embedded roadmaps. PDSi can also provide custom-ization, ruggedization, turnkey integration and support of ATCA systems, as well as extended warranty and repair services.

FEATURES & BEnEFITS

◆ High performance AdvancedTCA server blade featur-ing AMD64 technology

◆ Supports two Dual-core, Quad-core or Hex-core AMD Opteron™ processors with HyperTransport ™ technol-ogy

◆ Zone 3 interface enables I/O and storage expansion via PDSi’s ATCA-RT01 RTM

◆ Certified with VMware ESX Server 3.5 and 4.0 when used with PDSi’s ATCA-RT01 RTM

◆ Proven, third generation design

BladesBlad

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Pinnacle Data Systems, Inc., An Avnet Company6600 Port Road Groveport, OH 43125 USA (614) 748-1150 Telephone(614) 748-1209 Fax [email protected] www.pinnacle.comAn Avnet Company


ContaCt InformatIon


Pinnacle Data Systems, Inc., An Avnet Company6600 Port Road Groveport, OH 43125 USA (614) 748-1150 Telephone(614) 748-1209 Fax [email protected] www.pinnacle.com

TECHnICAL SPECS

◆ VGA Video supports resolutions up to 1600 x 1200 ◆ Onboard 2.5 inch serviceable SAS HDD provides up

to 146 GB storage, external SAS connector for expan-sion

◆ 2 x 10/100/1000 BaseT Ethernet ports (from front blade)

◆ 2 x USB 2.0 ports ◆ 1 x RS232 serial port (from front blade)

AvAILABILITy

Now

APPLICATIOn AREAS

Military, Aerospace, Telecommunications, Enterprise

ATCA-RT01 AdvancedTCA® RTM with video and StorageCompatible Operating Systems: Windows Server® 2003, Win¬dows® XP, Linux (SuSe®, Red Hat® Enterprise Linux), Solaris® 10 x86 and SPARC™, VMware® ESX Server 3.5 and 4.0

Specification Compliance: PICMG® ATCA3.0

PDSi’s Video + Storage ATCA Rear Transition Module (ATCA-RT01) provides high reliability SAS storage, VGA video output and additional I/O functionality for AdvancedTCA systems using x86 processor blades from PDSi or Oracle. In addition, it also operates with Oracle’s UltraSPARC® T2-based Netra™ CP3260 blade. For systems requiring a mix of these compute blades, the ATCA-RT01 can provide a “universal RTM” solution.

The ATCA-RT01 complies with PICMG ATCA 3.0 specifi¬cations for seamless and dependable operation in critical applications. It features a 2.5 inch SAS HDD for local storage as well as front-panel access to the onboard SAS controller for connection to secondary or redun-dant storage arrays. Additional ports include VGA video output and USB I/O for convenient local monitoring or configuration of applications. Serial and Ethernet ports are also routed from the front blade so that all required I/O can be rear-accessible. The RTM includes Pigeon Point’s module management.

Telecom, aerospace, and military OEMs will appreciate the flexibility this advanced RTM brings to their systems. Extended availability from PDSi is assured. PDSi can also provide customization, turnkey integration and sup-port of ATCA systems, as well as extended warranty and repair services.

FEATURES & BEnEFITS

◆ RTM offers VGA video and SAS storage resources for selected ATCA applications

◆ x86 blade compatibility: PDSi ATCA-F1 and Oracle Netra CP3220, SPARC blade compatibility: Oracle Netra CP3260

◆ Robust design for military, aerospace, telco and enterprise applications

◆ Certified with VMware ESX Server 3.5 and 4.0 when used with PDSi’s ATCA-F1 blade

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An Avnet Company


ContaCt InformatIon

Adax Inc.


◆ AMC Front Panel LEDs • AMC.0 IPMI (2x) • Hot Swap (Adjacent to Latch) • Per Port Status (4x) • Board Status/User Programmable◆ Interfaces • Four OC-3/STM-1 • Two OC-12/STM-4 • Support for single mode fiber and multi-mode

fiber (ITU G.957) • Up to 2 GbE interfaces per PCIe • Up to 4 GbE interfaces per AMC card◆ ATM/POS • STM-1 / STS-3c • STM-4 / STS-12c • ATM (ITU I.432) • POS (RFC 1619 / RFC 1662)

AvAILABILITy

Available Now

APPLICATIOn AREAS

• 4G, LTE-SAE • WiMAX • ASN Gateways • 3G RNC, MSC, SGSN, and NodeB • Voice over Packet • Video Streaming • Broadband Networks (incl GPON) • ATM to IP Gateways • Femtocell Access Controller

ATM4-AMC / ATM5-PCIe Signaling and ATM to IP Interworking for Femtocells, Home NodeB Gateways, and Access Concentration

Compatible Operating Systems: Linux and Solaris as standard. Other OS support on request

Specification Compliance: AMC • PICMG AMC.0 Specifi cation R2.0 • PICMG AMC.1 PCI Express Advanced Switching R1.0 • PICMG AMC.2 Gigabit Ethernet R1.x • IPMI V1.5 Intelligent Platform Management Interface Specifi cations PCle • PCI Specifi-cation Revision 2.3 • PCI Express Electrom

These ATM cards are high performance AdvancedTCA Mezzanine and PCIe controllers designed for use in all aspects of telecommunications networks. The ATM4- AMC and ATM5-PCIe include support for ATM host termination, switching and L2/L3/L4 or higher inter-working between Gigabit Ethernet and ATM interfaces. With support for AAL2 and AAL5, the ATM4/5 has the ability for real-time voice and video over AAL2, as well as signaling and IP over AAL5 in 3G/4G networks. The ATM4/5 is ideal for demanding carrier applications in Wireless 3G, 4G, LTE, IMS, Internet Access, Fixed/Mobile Convergence and Next Generation Mobile Networks.

FEATURES & BEnEFITS

◆ Multi-Purpose I/O boards for 3GPP/IMS/LTE/NGMN Wireless Networks

◆ On-board interworking in 3 different modes: - IP Over AAL5 to IP over Ethernet - AALx to UDP/IP over Ethernet - GTP Interworking

◆ 32,560 bi-directional IW channels◆ ATM AAL2 & AAL5 on a single trunk◆ 256 Virtual Circuits (VCs) for AAL5 termination

TECHnICAL SPECS

◆ Protocols • AAL2, ITU-T I.363.2 • AAL5, ITU-T I.363.5 • SSCOP Q.2110 • SSCF NNI Q2140 • SSCF UNI per Q.2130 • SSCS Layer Management Q.2144 • SSSAR/SSTED/SSADT ITU-T I.366.1 • HSL per Telcordia GR-2878-Core◆ AMC System Interconnect • PCI Express One x1 Express Interface • Gigabit Ethernet Four Gigabit Ethernet links on

AMC ports 0-1 and 8-9

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Adax Inc.


• SIGTRAN: M3UA, M2PA, SCTP, M2UA • PCM • I-TDM • 248 channels ‘mix and match’◆ 8 Interfaces • T1: ANSI, AT&T, Bellcore • E1: ETSI • J1: TTC • All ports software selectable • Jitter and Wander ITU-T G.823 • High impedance ports G.772 • Up to 2 GbEs per PCI, PCIe, EM card, 4 GbE per AMC◆ Power Requirements • PMC/LPe: 6-10 watts • PCI/PCIe/EM 7-12 watts • AMC 8-14 watts◆ Bus Type • PMC – PMC 3.3V 66/33MHz 32-bit • PCI – Full Height, Half Length • PCIe – Full Height, Half Length • PCIe EM – PCIe single lane • LPe – Half Height, Half Length • AMC – PCI-e single lane

AvAILABILITy

Available Now

APPLICATIOn AREAS

• Signaling Gateways • Media Gateway Controllers • SGSN / GGSN • MSC / HLR / VLR • BSS Nodes • VAS Applications: SMS, Roaming and Billing; Test

Measurement Simulation, Monitoring Systems • LTE/4G connectivity

HDC3 8 Trunk SS7 Signaling & I-TDM Controller

Compatible Operating Systems: Linux, MontaVista CGE, Solaris X.86 and Solaris SPARC as standard. Other OS support on request.

Specification Compliance: PICMG AMC.0, PICMG AMC.1, PICMG AMC.2, PICMG AMC.3, IPMI

The HDC3 is the 3rd generation of the highly successful Adax SS7 controller and offers up to 8 T1, E1 or J1 trunks per card. Specifically designed to meet the demands of wireline, wireless and convergence platforms, the HDC3 excels at traditional TDM SS7, High-Speed ATM SS7 as well as I-TDM voice interworking. The HDC3 provides a high density,high performance solution for signaling and interworking applications.

Delivering up to 248 LSL MTP2 links, I-TDM flows or 8 HSLs per card, the HDC3 provides one of the highest den-sities on the market today, making it ideal for demanding telecommunications applications with high capacity and throughput requirements. The low-power on board processor performs many thousands of transactions per second, with minimal load on the host, maximizing the performance of the applications and reducing system costs without compromising reliability.

The HDC3 is available in PMC, AMC, PCI and PCIe (including the new ExpressModule) form factors, all of which share a common software driver and have a consistent API for application portability. This makes the HDC3 card a highly flexible, scalable and portable signaling solution for all system architectures that maxi-mizes protection of investment.

FEATURES & BEnEFITS

◆ 8 software selectable E1, T1, or J1 trunks◆ Up to 2 Ethernet ports per PCI, PCIe and PCIe

ExpressModule card◆ AMC, PMC, PCI and PCIe (Full height, Low-Profile and

ExpressModule) board formats◆ Up to 248 LSL MTP2 links per card with high line

utilization◆ Up to 8 HSL (Q.703 Annex A and ATM AAL5) links

per card

TECHnICAL SPECS

◆ Protocol Support • SS7 MTP2 and signaling performance • ATM AAL5, SSCOP, SSCF • HDLC, LAPB/D/F/V5 • X.25 • Frame Relay/PPP

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Adax Inc.


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• PCI Revision 1.1 • Designed to Meet Belcore GR-63-CORE◆ Pkt2-PCIe Confgurations: • “10/10” 2x 10GbEs • “10/4” 1x 10GbEs and 4x 1GbEs • “10/2/2” 1x 10GbE, 2x 1GbEs and 2x GbEs ‘ott’ • “10” 1x 10GbE • “4” 4x 1GbEs◆ Pkt-AMC Network / Carrier Configurations: • “4/4” 4 and 4 GbEs • “4/10” 4 GbEs and 1x 10GbE XAUI + 2x GbEs • “10/10” 1x 10GbE and 1x 10GbE XAUI + 2x GbEs • “10/10M” 2x 10GbEs and 2x GbEs◆ Electrical and Safety Certified: • US/16222/UL IEC 60950-1 (2005) Second Edition • FCC Part 15B, Class A - VCCI • EN55022:2006 +A1 • EN55024:1998 +A1:2001, +A2:2003 • Designed to meet EN61000-4-2,3,4,6

AvAILABILITy

Available Now

APPLICATIOn AREAS

• IPsec • Policy Control/Enforcement • Lawful Intercept • Data Optimisation/Offload • QoS, Traffic Management • Billing • Monitoring, Test, Measurement • LTE Core Network nodes • Security / Femto/Home eNodeB Gateways

Pkt2-PCIe / PacketAMC Secure User & Control Plane Application and Packet Processing for LTE and all IP Networks

Compatible Operating Systems: Linux and Solaris as standard. Other OS support on request

Specification Compliance: Standards - AMC.0 R2.0 Advance Mezzanine Card Base Specifi cation - AMC.1 R2.0 PCI Express and Advance Switching AMC.1 Type 4 - AMC.2 R1.0 AMC Gigabit Ethernet AMC.2 Type 4 E2 or Type 5 E2 - IPMI v1.5 - IEEE 802.3 - Designed to meet Belcore GR-63-CORE

Pkt2-PCIeThe Pkt2-PCIe uses the advanced Octeon II 6645 intelligentprocessor for Traffic and Bandwidth Management, QoS and Security on LTE wireless applications, delivering a highly avail-able, high-performance, carrier-grade transport from the Edge to Core networks. In Rack Mount Servers (RMS) the Pkt2-PCIe provides, high bandwidth carrier applications in LTE nodes such as the MME, SGW and PGW, Security GWs, Femto/Home eNodeB GWs, Policy Servers and Data Offload devices.

PacketAMCThe Octeon Plus PacketAMC offers Pkt2 functionality in AMC form factor. Combined with the Adax PacketRunner ATCA carrier blade provides high performance control and user plane servicesfrom one tightly coupled resource. Contention on the chassis backplane is removed, allowing multiple IP flows to be processed on the APR. Processed packets are then available for immediate transport to system application servers or the IP network.

FEATURES & BEnEFITS

◆ Pkt2-PCIe • High Performance Cavium OCTEON II 6645 • Gen2 4 lane PCIe • 2 GB DDR3 Memory (4 and 8 GB order options) • 5 configuration options◆ PktAMC • High Performance hardware acceleration with

Cavium OCTEON Plus 5650 or 5645 • 2 or 4 GB of DDR2 Memory • 4 configuration options◆ Security with Adax IPsec from AuthenTec◆ Multi-Functional support for

Carrier Ethernet, MPLS-TP, PBB-TE, Deep Packet Inspection (DPI), QoS Queuing and Scheduling

◆ Best of Breed Partner Eco-System for 3rd party applications and sofware

TECHnICAL SPECS

◆ Pkt2-PCIe: • PCI Specification Revision 2.3


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◆ Config space can be displayed in its entirety so that driver registers can be verified.

TECHnICAL SPECS

◆ Analyzer Lanes supported: X1,x2,x4,x8,x16 Speeds: 2.5GT/s, 5GT/s and 8GTs Probes/Interposers: active and passive PCIe slot, XMC, AMC, VPX, express card, express module,

minicard MidBus, multi-lead, external PCIe cable, CompactPCI Serial and othersForm factor: Card, Chassis

◆ Exerciser Lanes supported: X1,x2,x4,x8,x16 Speeds: 2.5GT/s, 5GT/s, 8GT/s Emulation: root complex and endpoint emulation◆ Protocol Test Card Speeds: 2.5GT/s and 5GT/s operation Tests: Add-in-card test BIOS Platform Test Single Root IO Virtualization Test

APPLICATIOn AREAS

Mezzanine Boards, Add-in Cards, Host Carrier Systems, System Boards, Chips

LeCroy’s PCI Express® Protocol Analysis and Test Tools

Compatible Operating Systems: Windows 7/Windows XP/Vista

Specification Compliance: PCI Express Standards: 1.1, 2.0, and 3.0

Whether you are a test engineer or firmware developer, LeCroy’s Protocol Analyzers will help you measure perfor-mance and quickly identify, troubleshoot and solve your protocol problems.

LeCroy’s products include a wide range of probe connec-tions to support XMC, AMC, VPX, ATCA, microTCA, Express Card, MiniCard, Express Module, CompactPCI Serial, MidBus connectors and flexible mult-lead probes for PCIeR 1.0a, 1.1 (“Gen1” at 2.5GT/s), PCIe 2.0 (“Gen2” at 5 GT/s) and PCIe 3.0 (“Gen3” at 8 GT/s).

The high performance SummitTM Protocol Ana lyzers feature the new PCIe virtualization extensions for SR-IOV and MR-IOV and in-band logic analysis. Decoding for SSD/Drive devices that use NVM Express, SCSI Express and SATA Express are also supported.

LeCroy offers a complete range of protocol test solutions, including analyzers, exercisers, protocol test cards, and physical layer testing tools that are certified by the PCI-SIG for ensuring compliance and compatibility with PCI Express specifications, including PCIe 2.0.

FEATURES & BEnEFITS

◆ One button protocol error check. Lists all protocol errors found in a trace. Great starting point for beginning a debug session.

◆ Flow control screen that quickly shows credit balances for root complex and endpoint performance bottlenecks. Easily find out why your add-in card is underperforming on its benchmarks.

◆ LTSSM state view screen that accurately shows power state transitions with hyperlinks to drill down to more detail. Helps identify issues when endpoints go into and out of low power states.

◆ Full power management state tracking with LeCroy’s Interposer technology. Prevents loosing the trace when the system goes into electrical idle.

◆ LeCroy’s Data View shows only the necessary protocol handshaking ack/naks so you don’t have to be a protocol expert to understand if root complexes and endpoints are communicating properly.

◆ Real Time Statistics puts the analyzer into a monitoring mode showing rates for any user term chosen. Good for showing performance and bus utilization of the DUT.

◆ Zero Time Search provides a fast way to search large traces for specific protocol terms.

LeCroy Corporation3385 Scott Blvd.Santa Clara, CA, 95054USA1 800 909-7211 Toll Free1 408 727-6622 [email protected]://www.lecroy.com

LeCroy Corporation


ContaCt InformatIon

Adax Inc.


◆ Availability and Serviceability These systems are designed to exceed the availability

and serviceability requirements specified in the ATCA standard. They have been tested by an external labora-tory and found to exceed the standard MTBF and MTTR measurements, proving their superior availability and serviceability and they are “NEBS Ready”.

TECHnICAL SPECS

◆ 2 Slot 3U ATCA AC/DC◆ 6 Slot 5U ATCA Platform DC◆ 6 Slot 6U ATCA AC/DC◆ 14 Slot 13U AC/DC ATCA

AvAILABILITy

Available Now

APPLICATIOn AREAS

• Policy Control • EPC Core • Public Safety Networks • EPC Test Solutions • Rural Networks • In-Building Networks • LTE Offload Solutions

Application Ready Platform Highly Integrated Platform Ready for Your Value-Add Application

Compatible Operating Systems: Linux

Specification Compliance: PICMG 3.x

The range of Application Ready Platforms from Adax pro-vides integrated hardware and software systems with High Availability and Scalability built in as standard. A full range of cost-effective 2, 6 and 14 slot solutions are available delivering the industry’s lowest cost per slot. By uniquely compressing the dual switch and shelf managers into a small combined module the 6 slot chassis offers 6 payload slots rather than the traditional 4. This means 50% more revenue generating slots than other comparable platforms. They are also greener, more energy efficient, and have a smaller footprint than comparable systems. These integrated platforms are truly ‘Application Ready’ allowing customers to concentrate on their core application development. These applications are the value-add that differentiate from the competition. Devel-oping and deploying on the same platform reduces both CAPEX and OPEX in the fastest time to market.

FEATURES & BEnEFITS

◆ 2, 6 and 14 slot solutions Complete Scalability and Flexibility are what make Adax

ATCA offerings unique. The depth and breadth of the Adax product range provides the flexibility to configure options that meet individual customer requirements and scalability by adding products as required.

◆ Best of Breed Partner Eco-System Adax works with industry leading product and services

suppliers around the globe. World-class solutions from Aricent, Trillium, Vineyard Networks and others are supported out of the box or port your own.

◆ Ethernet Switch Management and OpenArchitect® Using familiar, industry-standard Linux interfaces, Znyx

field proven OpenArchitect® provides advanced perfor-mance, and flexibility in configuration, packet filtering, packet vectoring, and high-availability funtionality.

◆ Load-Balancing Packet Processing at 10G-Per-Sec The ability to send packets port to port using any

information within the packet, enables load balancing, security monitoring, and many other applications that would otherwise not be possible. Because the silicon handles the real-time decision making, all packet vector-ing happens at full line rate without restrictions. Using the familiar Linux iptables control interface network technicians can configure packet vectoring subsystems that eliminate the need for expensive external systems.

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TECHnICAL SPECS

◆ Virtex-6 FPGA (from LX130T/195T/240T/365T to SX315T/475T), 20000-74400 Logic Slices, 9500-38300Kbit Block RAM, 480-2016 DSP48E1 Slices, up to 1000GMACS of processing power

◆ Four independent DDRIII SDRAM memory banks, total memory capacity 2GB

◆ 12 full-duplex lines provides Gigabit Ethernet and PCI Express x1..x8 or Serial Rapid IO x1..x4 interfaces

◆ VITA 57.1 (FMC) expansion site, supports air cooled and conduction cooled with region 1 form-factors with or w/o front panel

◆ Single Mid-Size or Single Full-Size AMC board

AvAILABILITy

Available now

APPLICATIOn AREAS

Aerospace/Defense, Broadcast, Data Processing and Storage, Industrial Automation, Medical Imaging, Wired Communcations, Wireless Communications

SAMC-713 High Performance virtex-6 AMC with FMC expansion siteCompatible Operating Systems: Windows, Linux

Specification Compliance: AMC.0 R2.0, AMC.1, AMC.2, AMC.4, VITA57.1

The SAMC-713 Advanced Mezzanine Card (AMC) is designed around Virtex-6 FPGA LXT and SXT families, combining great fabric flexibility and a colossal external memory benefiting from multiple high-pin-count, mod-ular add-on FMC-based I/O cards.

The SAMC-713 is designed for applications requiring high performance, high bandwidth and low latency. The board takes full advantage of the Virtex-6 FPGAís power which makes the SAMC-713 perfect for reducing size, complexity and costs associated to leading-edge tele-communications, networking, data processing, industrial and medical applications. Moreover, FMC expansion site on the board offers almost unlimited I/O possibilities.

Combining Virtex-6 FPGAs LXT (up to VLX365T) or SXT (up to VSX475T) with four independent 2Gb DDRIII SDRAM memory banks and twelve high performance full-duplex GTX lines supporting Gigabit Ethernet, PCI express x1..x8 and Serial RapidIO x1..x4 The SAMC-713 gives OEMs an effective solution for wide range of applications. Scan Engineering Telecom also provides customization, turnkey integration and support to ensure that OEMs can focus where they prefer to add their own unique value.

FEATURES & BEnEFITS

◆ High performance AMC FPGA board with FMC expansion site

◆ Combines great Xilinx Virtex-6 FPGAs power, colos-sal amount of memory and numerous interface lines

◆ Cost-effective platform for MicroTCA, ATCA and xTCA-based solutions

◆ For OEMs in telecom, datacom, industrial, medi-cal, test & measurement and defence & aerospace industries

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Advantech


◆ 10/40G fabric interface with eight 10GE uplinks◆ Fabric interface bandwidth up to 640G◆ Separate base and fabric interface switching for

enhanced security and protection◆ Mid-size AMC site for host application processing,

acceleration or offload functions

ATCA-9112 Switch blade with 10/40GbE switching for 16 slot systems

The ATCA-9112 40GbE switch blade provides 10/40GbE switching for 16 slots and 8 front panel uplinks with a 640Gbps non-blocking fabric switch from Broadcom. An RTM provides up to 100Gbps of connectivity. Designed for network security, LTE and DPI-centric applications, the ATCA-9112 offers the highest aggregate switching bandwidth within an ATCA chassis enabling support for 16-slot systems. A Broadcom BCM56846 ensures seamless integration through open standard hardware supporting 40GbE or 10GbE ATCA node blades. A Broadcom BCM56321 provides ATCA base interface con-nectivity. The switch offers a flexible approach to switch blade functionality via a mid-size AMC site to host appli-cation processing, acceleration or offload functions. Advantech’s Freescale QorIQ™ P5020-based AMC-4202 or x86-based MIC-5603 PrAMC can be used to consoli-date processing requirements.

FEATURES

◆ 40GbE switch blade provides 10/40GbE switching for 16 slots

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◆ Pigeon Point® IPMC management with Hardware Platform Interface(HPI)

◆ Customization welcomed and extended availability assured

TECHnICAL SPECS

◆ 2 x Intel Xeon E5-26XX Series CPUs (70W or less) ◆ 12 x DIMM sockets, up to 192GB DDR3 1333MHz ◆ Support up to 4 x SATADIMM SSD, MLC and SLC

versions◆ 1 x mSATA SSD ◆ Front Panel I/O: 1 x 1Gb Ethernet, 4 x USB 2.0, 1 x

Serial, 1 x HDMI Micro Video◆ Zone 3 RTM interface

AvAILABILITy

Production, Q4/CY2012

APPLICATIOn AREAS

Rugged military servers, flexible aerospace platforms, powerful telecom convergence

Dual Intel® Xeon® E5 ATCA® Blade (ATCA-n1)Compatible Operating Systems: Red Hat Enterprise Linux® V6.1, Windows Server® 2008 R2 SP1, VMware ESXi 5.0

Specification Compliance: PICMG®ATCA 3.0 R2, ATCA 3.1 R1, IPMI V1.5

The ATCA-N1 blade is a high performance computing platform that is designed to provide maximum com-puting, memory and storage flexibility in a single ATCA chassis slot. The ATCA-N1 features dual Intel six-core or eight-core processors utilizing the Intel Xeon® E5-26XX Series family of CPUs (Sandy Bridge), and supports DDR3 memory. The ATCA-N1 delivers intensive virtual OS computing power in a highly avail-able and flexible multiprocessing system needed in today’s challenging markets.

The ATCA-N1 is designed for NEBS compliance and certi-fied for safety (IEC-CB) and EMC (FCC, CE). The ATCA-N1 is compliant with the PigeonPoint® Hardware Platform Interface (HPI) providing a management interface to many service applications.

Other features include support for up to four SATA-DIMM™ solid state drives, one mSATA solid state drive, 400W per ATCA slot chassis implementations and a Zone 3 interface for connection to a Rear Transition Module.

PDSi gives telecom, aerospace, and military OEMs and integrators the ability to deploy configurable, scalable, high-reliability ATCA solutions using this powerful compute blade based on Intel’s 32nm processor tech-nologies. Extended availability from PDSi is assured as key components are supported by embedded roadmaps. PDSi can also provide customization, ruggedization, turnkey integration and support of ATCA systems, as well as extended warranty and repair services.

FEATURES & BEnEFITS

◆ Intel-based AdvancedTCA blade server utilizing Intel’s 32nm processor technology

◆ Dual purpose memory sockets enable the use of up to 4 x SATADIMM solid state drives

◆ mSATA solid state drive provides flexible expansion storage/boot option

◆ Trusted Platform Module (TPM) capability◆ Redundant BIOS implementation◆ Optional Zone 3 RTM interface ◆ 10Gb on both Ethernet Base and Fabric Interfaces

Pinnacle Data Systems, Inc., An Avnet Company6600 Port Road Groveport, OH 43125 USA (614) 748-1150 Telephone(614) 748-1209 Fax [email protected] www.pinnacle.comAn Avnet Company

ATCA SUMMIT

www.adax.com For more information please visit our website or call: Adax Inc: +1 510 548 7047 Email: [email protected] Europe: +44 (0) 118 952 2800 Email: [email protected]

Boards, Blades, Software and Application Ready Platforms

Adax products provide industry leading performance and capacity for LTE, 4G, NGMN & IMS networks. The Adax PacketRunner provides the keystone product that allows NEPs unlimited I/O confi gurations to choose from. Designed to exceed your system requirements, Adax solutions offer superior scalability, fl exibility and price/performance ratios, on an Application Ready Platform for your SS7, ATM, IP, signaling, data and packet processing needs.

• Application Ready Platform: 3U, 5U or 13U fully integrated ATCA chassis

• Adax PacketRunner: Advanced intelligent application and packet processing ATCA carrier blade with Cavium 5650, 8 GB RAM, 4 AMC bays, robust power and thermals

• Pkt2-PCIe & PacketAMC: Packet processing, fl ow management, DPI, and Layer 2 LTE protocols including Carrier Ethernet

• HDC3: SS7/ATM TDM controller with 8 E1/T1 AnnexA or ATM ports, 248 LSLs and TDM/i-TDM IW in all form factors

• ATM4/5: ATM Signaling, ATM-IP IW, OC3/OC12 and GbE ports in AMC and PCIe form factors

• AdaxGW: Signaling Gateway on ATCA blade or chassis

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