to-leadless package - optimized for high current - infineon
TRANSCRIPT
TO-Leadless Optimized for high current applications
Package for high current applications
TO-Leadless is a perfect fit for applications with high power & high reliability requirements
Forklift
Light electric vehicles (LEV) such as e-scooter, µ-cars
PoL (Point of Load)
Telecom
Differentiation of Infineon’s high power packages @ a glance
D²PAK D²PAK 7pin TO-LeadLess
Current Capability
Power Density
Thermal Performance
Height
Reliability
More details on parameters of high current packages
D²PAK
D²PAK 7pin TOLL
lowest RDS(on)
30V 3.4 mΩ 0.9 mΩ 0.4 mΩ
60V 1.9 mΩ 1.0 mΩ 0.75 mΩ
100V 2.7 mΩ 2.5 mΩ 2.0 mΩ
150V 7.2 mΩ 6.5 mΩ 5.9 mΩ
Package Resistance 0.74 mΩ 0.44 mΩ 0.25 mΩ
Current Capability 120A 180 A 300 A
Footprint 150 mm² 150 mm² 115 mm²
Inductivity 5 nH 5 nH 1-2 nH
2.3mm
TO-Leadless a replacement for D²PAK 7Pin
11.7mm 9.9mm
Footprint: 115 mm²
4.4mm
Footprint: 150 mm²
30%
Footprint
Reduction
10.0mm 15mm
50%
Height
Reduction
60%
Space
reduction
Vo
ltag
Cla
ss
15
0V
3
0V
Level of Parallelization
low high
TO-leadless offers advantages where high level of parallelization is required
TOLL 60
V
10
0V
D²PAK 7pin
SuperSO8
Improved Reliability: Bottleneck Solder Joint / Current density
Contact/Solder area D2PAK 7Pin: =2.65mm*0.6mm*5
= 7.95mm2
D2PAK 7Pin
Contact/Solder area TOLL: ~1.9mm*0.8mm*7+0.7mm*0.4mm*6
= 12.32mm2
TO -LeadLess
bnom =0.6mm Lnom =2.65mm
Bnom =0.8mm Lnom =1.9mm L3nom =0.7mm enom =1.2mm
TOLL: Much bigger contact area results in lower current density, avoiding
electro migration even at higher current level and higher temperature
->Improved Reliability in High Current Applications
Possibility of optical inspection
The TO-LeadLess packages enables a visual inspection due to Tin plated grooved leads
Pin of TO-LeadLess
Groove
PCB
Tracks onPCB
Visible solder joint
Trapezoid Groove
guaranteed wetting
When do we recommend TO-Leadless & why?
applications which require highest efficiency and best EMI behavior
thermal behavior
space
efficiency
high current applications which require best thermal behavior
when space reduction in the application is required
Therm
al Resitance (
K/W
)
TO-Leadless a perfect combination of low package area and thermal resistance
Package Area (mm²)
0.5
1.0
1.5
2.0
25
Cooler Smaller
Hotter
Larger
TO-220
50 100 150 200 250 300 350
D²PAK 7pin
DPAK
S3O8
SuperSO8
CanPAK™ S/M
TO-Leadless
D²PAK
thermal behavior
space
TO-LeadLess offering lowest RDS(on)
TO-LeadLess
D²PAK 7pin
For the first time offering outstanding low RDS(on)
efficiency
TO-LeadLess portfolio
Package Type VDS [V] RDS(on) max [mΩ]
IPT004N03L 30 0.04
IPT007N06N 60 0.7
IPT020N10N3 100 2.0
IPT059N15N3 150 5.9
Summary Why TO-LeadLess?
A leadless package with 60% space reduction
Highest current capability: up to 300A
Very low RDS(on) – up to 30% lower RDS(on)
Enables a visual inspection due to Tin plated grooved leads
Better EMI due to reduced parasitic inductances (cut by half)
High reliability due to improved solder contact area – reduced electro migration
Reduced BOM: Smaller board, less drivers, less MOSFETs
If you have any further questions…
Further information you find on our homepage:
www.infineon.com/toll