tn-47-22: designing for 1.5, low-power...

TN-47-22: Designing for LV FBDIMMsIntroduction

Technical NoteDesigning for 1.5V, Low-Power FBDIMMs

IntroductionToday’s memory power usage may have an adverse affect in the overall system level power and server cooling requirements. This document discusses the memory power trends, identifies new, low-voltage (lower power) solutions for high-density DDR2 memory designs, and provides details for software and hardware implementation.

Where does the memory power come from?Memory has migrated from simple synchronous devices to very complex, digital-state machines. Even the typical data sheet of today's high-speed memory trump the size of the early microprocessor data sheets. Given the complex systems, it’s no wonder more power is consumed in today's high-density memory modules.

Even with the new technology, though, we’ve seen great improvements in the power management of memory since the early days of fast-page DRAM. As shown in Figure 1, you can see how the power per bandwidth significantly decreases with the each new technology. Early SDR-133 ran at a peak bandwidth of 1.1 GB/s for a 64-bit data bus, yet it consumed well over 400mW per active device. In comparison, DDR3-1333 provides a bandwidth for a 64-bit bus of up to 10.7 GB/s but consumes about only 300mW per device. This equates to over a 90% savings in terms of W/GB/s (SDR-133 = 3.1 W/GB/s; DDR3-1333 = 230 mW/GB/s).

Figure 1: Industry power trends for memory

2.750

2.500

2.250

1.750

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SDR (3.3V) DDR (2.5V) DDR2 (1.8V) DDR3 (1.5V)

1.1GB/s

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PDF: 09005aef832a92e7/ Source: 09005aef832a92c2 Micron Technology, Inc., reserves the right to change products or specifications without notice.tn4722_1.5v_fbdimm_design.fm - Rev A 3/6/08 EN 1 ©2008 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All

information discussed herein is provided on an “as is” basis, without warranties of any kind.

TN-47-22: Designing for LV FBDIMMsWhere does the memory power come from?

While Figure 1 shows a true graph, it doesn’t tell the whole story. What it doesn’t show is the total memory power consumption of a fully loaded channel. Even with the lower power per-bandwidth values, the actual system-level power—due to a high memory count and extremely fast cycle times—continues to grow. It’s not uncommon for a dual-channel system, fully populated with eight FBDIMMs, to consume power in excess of 60–90 watts (see Figure 2).

Figure 2: Power of a fully loaded FBDIMM channel

There are many system-level aspects that affect memory power, but the operating speed and actual usage conditions of the DRAM is probably one of the must important factors: the faster the clock, the faster the data rate, the higher the power use. Other factors include whether or not open pages are utilized, the use of special power-down and standby modes—which are initiated with clock enable (CKE), how many slots are popu-lated, and the module configuration types.

For example, a 2GB FBDIMM can be built at least two ways and each result in different power consumption. One method uses 512Mb (128 Meg x 4) devices; another uses 1Gb (128 Meg x 8) devices. The 512Mb-based module requires 36 DRAM, making it a a dual-rank, x4 module. By contrast, the 1Gb-based module only requires 18 DRAM, making it a dual-rank, x8 module. The 1Gb-based module provides the same density at the same speed, but reduces individual module power by approximately 30% (see Figure 3 on page 3).

PC133 Compared to DDR2-667 FBDIMM

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Power per slot Power per channel(4 for PC133, 8 for FBDIMM)

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PC133 SDRAM 3.3V

High-speed DDR2 has over 60 percent increasein channel power as compared to PC133

DR x4 (512Mb-based) 1.8V

PDF: 09005aef832a92e7/ Source: 09005aef832a92c2 Micron Technology, Inc., reserves the right to change products or specifications without notice.tn4722_1.5v_fbdimm_design.fm - Rev A 3/6/08 EN 2 ©2008 Micron Technology, Inc. All rights reserved

TN-47-22: Designing for LV FBDIMMsWhat is an LV FBDIMM?

Figure 3: Comparison of 2GB FBDIMM: 512Mb-based (dual-rank, x4) to 1Gb-based (dual-rank, x8)

As shown above, even by using the reduced chip-count module (dual-rank, x8), a fully loaded (1.8V) FBDIMM channel can still consume a large amount of power. This becomes especially important when we look at a typical data center that may host rows of server racks with hundreds of FBDIMM modules, all operating simultaneously. This model could equate to to kilowatts just for memory. This is why at Micron, we’ve devel-oped our Aspen Memory® line of low-voltage, low-power memory (1.5V DDR2 and LV FBDIMM).

What is an LV FBDIMM?As the development leader of low-voltage DDR2 memory, Micron worked closely with JEDEC and many of the advanced memory buffer (AMB) vendors to ensure that the key AMB suppliers can support low-voltage DDR2 SDRAM. In addition, several of the major AMB suppliers are starting to release reduced-power AMBs that can be utilized with reduced voltage DDR2 memory.

The result of this effort is our LV FBDIMM (low-voltage, fully buffered, dual, in-line memory module) that runs from a true 1.5V supply rail and has a substantially lower operating power than ever possible with conventional 1.8V DDR2 memory. The original FBDIMM required a full 1.8V supplied to the DDR2 memory and an additional 1.5V supplied to the AMB.

What’s even more amazing is that, other than the voltage change, the use of LV FBDIMMs is invisible to the system. The high-speed northbound and southbound links between the memory controller and the FBDIMM modules populated in the channel are exactly the same—they already run at 1.5V. The performance, timing, and other oper-ating requirements for the LV FBDIMM is identical to the 1.8V FBDIMM; it just consumes considerably less power (see Figure 4 on page 4).

2GB FBDIMM Power at DDR2-667

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DRAM power per slot

Reduced chip count modules provide some helpwith power reduction


TN-47-22: Designing for LV FBDIMMsPower advantages of Micron's Aspen Memory® LV FBDIMMs

Figure 4: LV FBDIMM block diagram

Power advantages of Micron's Aspen Memory® LV FBDIMMs

The most obvious advantage of our LV FBDIMM is the power savings. For Micron, the power savings is more than just the savings calculated by Joule's law and Ohm's law, where Power = Voltage × Current. The power savings from P = VI for operating DDR2 at 1.5V rather than 1.8V is about 16%.

Our LV DDR2 (1.5V) has additional power savings, too, since it is designed and manufac-tured on our DDR3 process, which is a true 1.5V process. This process enables us to bypass the voltage regulator—which is not very efficient—and, as such, the unregulated 1.5V DDR2 memory reduces power by an additional 15–20%. An example of power savings for a 2GB LV FBDIMM (dual-rank, x8) as compared to 2GB FBDIMM 1.8V (dual-rank, x8 and dual-rank, x4) is in the 30–45% range, respectively.

AMB Core VCC = 1.5V

DRAM I/O = 1.8V

Memory VDD = VDDQ = 1.8V AMB core (VCC = 1.5V), AMB memory I/O (VDD = 1.8V)

Standard FBDIMM (1.8V)

AMB Core VCC = 1.5V

DRAM I/O = 1.5V

Memory VDD = VDDQ = 1.5V AMB core (VCC = 1.5V), AMB memory I/O (VDD = 1.5V)

LV FBDIMM (1.5V)

1.5V supply1.8V supply


TN-47-22: Designing for LV FBDIMMsOther advantages of Micron's LV FBDIMMs

Figure 5: Micron’s LV FBDIMM offers up to 45% power savings

If you want to estimate the power of other density modules, or modules with other usage conditions, use our DDR2 power calculator at micron.com\powercalc. It’s easy to accu-rately estimate the amount of power savings for a DRAM by loading the power calculator with the 1.5V device IDD values, and then changing both the test and operating voltage from 1.8V to 1.5V.

Other advantages of Micron's LV FBDIMMs

Aside from lower power use, there are other advantages with the LV FBDIMMs. Because LV FBDIMMs use less power, they generate less heat, which means the system cooling requirements can be relaxed. For workstations and smaller servers where acoustics may be an issue, this is an important factor. Because of the lower dissipation of heat, a small system may not need as many fans, or may even get by with a lower air speed using the existing fans.

For enterprise systems with a high concentration of servers in a local area, like data centers, cooling is a major challenge. The amount of heat that is dissipated by these large systems that run simultaneously is phenomenal. These large systems typically don't take a break at the end of the day, so heat is constantly being generated around the clock, 365 days a year. As such, a reduction in heat dissipation directly equates to a lower cooling cost. Refer to Micron’s data center memory-power calculator in our energy-effi-cient pages on micron.com for more information on estimating LV FBDIMM cost savings in large data centers.

Designing large, complex server systems can take years of development time. Many times, these designs are based on limited memory power projections, which may result in inadequate power budgets for the finished product. Sometimes, too, the marketing data available during the time of the original system design may have been intended for lower power-based (x8) modules or lower speeds only. Regardless of reason, systems working in today’s environment may have a limited power budget so the systems can’t be expanded to higher density or take advantage of the faster speed modules currently available. However, if these same systems supported LV FBDIMM, the savings from the 1.5V memory could allow the system to be fully populated, for the systems to utilize x4-based higher density modules or higher speed memory—which could extend the life of an otherwise marginally obsolete system.

DRAMDie Module

Die per TotalMemory AMB

Total per Slot

Dual-rank x4 (512Mb-based) 1.8V 189.6 36 6.83 5.0 11.83

Dual-rank x8 (1Gb-based) 1.8V 176.1 18 3.17 5.0 8.17

Dual-rank x8 (1Gb-based) 1.5V 112.4 18 2.02 4.5 6.52

Estimated (W)

The 1Gb-based (dual-rank, x8), 1.8V consumes 31% less power than the 512Mb-based (dual-rank, x4),1.8V module.

The 1Gb-based (dual-rank, x8), 1.5V consumes 45% less power than the 512Mb-based (dual-rank, x4), 1.8V module.

LV FBDIMM saves up to 45%in power

Est. (mW)


http://www.micron.com/innovations/energy_efficient/http://www.micron.com/innovations/energy_efficient/http://www.micron.com/innovations/energy_efficient/http://www.micron.com/support/part_info/powercalc.aspx http://www.micron.com/support/part_info/powercalc.aspx http://www.micron.com/innovations/energy_efficient/http://www.micron.com/innovations/energy_efficient/http://www.micron.com/innovations/energy_efficient/

TN-47-22: Designing for LV FBDIMMsSystem level options with LV FBDIMMs

System level options with LV FBDIMMs

If we take a closer look at the LV FBDIMM, we need to emphasize there is no perfor-mance, timing, or other differences between the FBDIMM and the LV FBDIMM. From the system side, all module interfaces are done through the AMB high-speed link. This link already operates from a 1.5V rail. There aren’t any changes to any of these differen-tial signals; there are no timing penalties or changes to packet data.

On the DRAM side, the AMB drives and receives all DRAM signals with VDDQ = 1.5V rather than at VDDQ = 1.8V. This interface works identical to the 1.8V interface with the exception of changes to input/output voltage levels. Again, timing, speed, and general performance of the DRAM, AMB, or FBDIMM are not affected. Of course, to take advan-tage of the LV FBDIMM features, the system must use 1.5V DRAM and an AMB that is designed to interface with the 1.5V DRAM.

Preparing to design in LV FBDIMMsThe first step in designing for LV FBDIMMs is to determine if the platform needs to support dual-memory voltages (both the standard 1.8V and the reduced 1.5V). Many times, to optimize design and inventory cost, the flexibility to accommodate a lower end (higher power) system and an upper end (lower power) system may be desirable. This means the same platform must support both voltage standards. The most traditional method, however, is to support only one voltage option for each platform, either the standard (1.8V) or the low voltage one (1.5V). If the platform only supports one voltage, the implementation is much simpler. (This will be addressed a later section.)

Assuming a platform is required to dynamically detect and drive one of the two voltages, there are several methods that can be used. The first, and most common method would be to use the FBDIMM voltage identification (VID) pins on the card edge. The VID pins enable the system to automatically detect the module voltage requirements before the module memory voltage is applied, forcing the system to regulate at either the standard or low-voltage level upon power up.

For the LV FBDIMMs using VID pin options, there are two pins on the edge connector that are set to signal the system of the module voltage requirements. For the standard module with a 1.5V AMB and 1.8V memory, both the VID pins are left open. For the low-voltage FBDIMM with a 1.5V AMB and 1.5V memory, VID(0) would be tied to ground and VID(1) would be left floating. Refer to Figure 6 on page 7 for more details.


TN-47-22: Designing for LV FBDIMMsImplementation of the VID pins

Figure 6: Using module VID pins for voltage detection

Implementation of the VID pins

Systems that dynamically support dual memory voltages and also use the VID pins as a detection method typically employ one of two techniques for voltage detection. One method is to use the VID pins as jumpers to directly configure the voltage regulator circuit to drive either VDD = 1.8V or VDD = 1.5V prior to system power up.

The other method is for the controller to monitor the logic level on the module VID pins, and then for the memory controller to interface with the voltage regulator to set the output voltage levels. This method requires either that the controller power ups before the memory is powered up, or that the memory is initialized after the voltage has been set and is stable (see Figure 7 on page 8).

Secondary side VID(1) pin 136

Primary sideVID(0) pin 16Pin 1

Function Voltage rail Pin nameModule pin

numberLogic level

(OPEN)Logic level

(GROUNDED)

Memory and AMB I/O VDD VID(0) 16 1.8V 1.5V

AMB core and high-speed bus VCC VID(1) 136 1.5V 1.2V

Coltage identification pins (VID) on the FBDIMM module card edge

Pin 240

Pin 120

Pin 121



Figure 7: Using module VID pins for voltage detection

Another method for detecting the voltage requirements of the module is to read the SPD data on the DIMM. (An SPD resides on each FBDIMM, whether it is a standard or reduced-voltage device.) In addition to holding the normal configuration data —critical timing parameters, module type, AMB settings—the SPD also has a reserved byte that defines the module voltage requirements.

For an FBDIMM, this is byte 3, which supports three options for memory voltages:• 1.8V memory only• 1.5V memory only• or an intermediate voltage of 1.55V, which also must be backward-compatible with

the 1.8V memory

Byte 3 works like the VID pins because it flags different voltage options for the AMB core. Some AMB vendors may support a lower AMB core voltage. Under normal conditions and for most AMBs, this voltage is always set to 1.5V.

Memory Controller

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VID pins from memory

Memory Controller

VID pins from memory

VID pins from memory are routed to the memory controller, and the memory controller sets thevoltage

VID pins from memory are routed directly to the voltage controller

Method One

Method Two

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If the module supports VCC = 1.5V for the AMB core and VDD = 1.8V for the memory, byte 3 is programmed as 12hex. If the module supports VCC = 1.5V for the AMB core and VDD = 1.5V for the memory, byte 3 will be programmed as 22hex. See Figure 8 for more detail on the decoding of each bit.

Figure 8: LV FBDIMM SPD voltage decode (Byte 3)

For a platform that supports dual voltages and uses the SPD to detect the memory voltage, the system must read the status of byte 3 and then condition the power as required. There are three ways to accomplish this: 1. The system can power up only the SMBus without providing a power source to the

memory, read the status of byte 3, then configure the power for either the standard memory voltage level or the optional, low-voltage level of 1.5V. The system can then power up the complete FBDIMM with the correct memory voltage, as determined by the contents of byte 3 in the SPD.

2. A second method is to power up the complete FBDIMM module with the memory voltage set to the standard voltage level of 1.8V. As part of the normal sequence, the system will read the contents of the SPD and configure the memory timing, loading, and other as required. If the system detects that byte 3 has been set for the reduced voltage level, the system will reset and cycle the memory voltage to 1.5V and restart the initialization sequence.

3. The third method is to power up the complete FBDIMM with the memory voltage set to 1.5V, read the SPD data, and then reset the voltage to 1.8V, if indicated by byte 3 in the SPD. These methods and flows are clearly identified in the following charts.

VDD (memory voltage)0001 = 1.8V0010 = 1.5V0011 = 1.2V

0100 = 1.55V (TBD)All others reserved

VCC (AMB voltage)0001 = 1.8V0010 = 1.5V0011 = 1.2V

All others reserved

SPD Byte 3

Bit 7–Bit 4 Bit 3–Bit 0

For LV FBDIMM with standard voltage AMB,byte 3 equals 22hex



Figure 9: Flowchart for first power up of system (VDD = 1.5V or 1.8V)

System support 1.5V memory?

System power on

Power memory at VDD = 1.5V


Does system utilize VID pins?



VID pins are NOT used

Initialize memory at VDD = 1.5V




Is VID(0) pulled to GND?

YesNo

Yes

No

Yes

No

Yes

No

Does system support dual memory voltages?



Figure 10: Reading SPD data (VID pins not used)

Power memory atVDD = 1.5V

Initialize memory atVDD = 1.5V

YesNo

VID pins are NOT used

Does system read SPDbefore VDD ramp?

Yes

NoIs byte 3, bit 7–4 equalto 0010 for all slots?

Yes

Shut down system and generate error

Is byte 3, bit 7–4 equalto 0001 for all slots?

No

SMBus and VDD powerup simultaneously


Initialize memory atVDD = 1.8V



Figure 11: Flowchart where SMBus and VDD power up simultaneously at 1.5V

Continue to initialize memory at VDD = 1.5V

YesNo

SMBus and VDD power up simultaneously

Does system default to VDD = 1.5V?

Yes

NoIs byte 3, bit 4–7 equalto 0010 for all slots?

Yes



No

SMBus and VDD power up simultaneously (VDD = 1.8V)

Restart memory at VDD = 1.8V

Reinitialize memory atVDD = 1.8V


TN-47-22: Designing for LV FBDIMMsHardware implementation

Figure 12: Flowchart where SMBus and VDD power up simultaneously at 1.8V

Hardware implementation

Most platforms will use a voltage or current regulator for the memory channel, which is either tuned for 1.8V operation, 1.5V operation, or may be configurable by the user through the BIOS or jumper settings. This section discusses systems that are currently tuned for 1.8V operation only and will give a few examples of how to change the regu-lator to drive the memory voltage (VOUT or VDD) to 1.5V rather than 1.8V. The examples are intended to show the simplicity of the changes and are not meant to be exact guide-lines for changing over any platform to support only 1.5V memory.

Typically, memory power is controlled by a high-resolution voltage regulator, or the first stage, that drives high current output drivers, or the second stage. Second stage drivers usually include switching type regulators that ensure an even distribution of power through multiple sources. The second stage remains about the same in terms of circuit design, regardless of memory voltage, but varies somewhat by manufacture or the type of voltage controller used.

Likewise, the primary higher resolution voltage controllers operate about the same between vendors. Each controller has a method for selecting the output voltage level and each has a method for interfacing with the second stage devices. Some first stages will be controlled by an analog circuit that biases the internal circuits for an exact output level. Other first stage controllers will be digitally controlled by logic levels present on input VID pins. Finally, some controllers may rely on a combination of digital and analog techniques for selecting the output voltage level. Any of these methods provide the user adjustability in the output voltage levels.

Continue to initialize memory at VDD = 1.8V

YesNo

SMBus and VDD power up simultaneously (VDD = 1.8V)


Yes



No

Restart memory at VDD = 1.5V

Re-initialize memory atVDD = 1.5V


TN-47-22: Designing for LV FBDIMMsUnderstanding analog-type voltage regulators

The interface between the first and second stages typically includes some type of signal(s) that drives the switching schemes for the larger output drivers. A current feed-back circuit from the second stage back to the first stage monitors the current flow through the individual FETs. Most have a voltage monitoring loop that detects any varia-tion in the final (stage two) regulated output voltage level.

See Figure 13 for a simplified block diagram. Most controllers have many additional features, including power-good signals, over-current protection schemes, under-voltage controls, and items like over-temperature sensors and such, but this document doesn’t cover those features or functions.

Figure 13: Simplified block diagram of the memory voltage controller

When we examine the first stage of the voltage controller, we see there are two types, including one that is controlled by an external voltage level (analog circuit) and one that includes logical inputs (digitally controlled). Both are very much the same in that the desired output voltage is determined by the status of external sources.

Understanding analog-type voltage regulatorsIn their simplest form, many analog voltage controllers use an external voltage divider network with a set voltage level for the midpoint of the resister divider. By setting the midpoint voltage at a static value, the user can change the current flow through the divider network by varying the resistor values. This allows a wide range of values for the biasing resistors and allows the user to select a specific output voltage level (the voltage level at the top of the divider). See Figure 14. Of course, the full functionality of these devices is much more complex, as most will monitor the output voltage or current levels and continually compare the output voltage level to the required output voltage level and make fine adjustments internally to compensate for any output voltage variation.

Voltage Controller

Driver Controller

Driver Controller

VOUT = VDD

V(source)

V(source)

Current FB

Current FB

Driver Control

Driver Control

Voltage FB

Stage 2Stage 1


TN-47-22: Designing for LV FBDIMMsUnderstanding analog-type voltage regulators

For typical analog-type voltage controllers, minor changes to the value of the output voltage level (memory voltage) can be made by changing the bias on the voltage divider input. For example, if we look at a typical voltage controller, such as the Analog Devices ADP3182, biased to drive 1.8V on the output, the voltage divider resister network consists of a 1KΩ resistor with 800mV across it, and a 1.24KΩ resistor with approximately 800µA through it. On the reference side of the 1.24KΩ resistor, the voltage level is 800mV, so with 800µA through the 1.24KΩ resistor, the VOUT level is ~1.8V [800mV + (1.24KΩ x 800µA)].

Figure 14: Typical 1.8V bias for analog-type of controller

For analog-type devices, changing the output drive level (memory voltage) from 1.8V to 1.5V is just a matter of changing resister values on the voltage divider network. We can either use the 1KΩ resistor on the lower leg of the network for a constant 800µA, or we can change the lower leg resistor to adjust the current value.

Seeing that a 1KΩ resistor is a very common 1% resistor value, for this example, let’s assume R1 will continue to be 1KΩ. We know the lower leg (R1) of the voltage divider will always have V1 = 800mV, and if we keep the 1KΩ resistor, there will continue to be 800µA of current. We can solve for the value of the top leg (R2) of the divider by using Ohm’s law:

R2 = V2/I2where V2 = 700mV (1.5V - 800mV) and I2 = 800µA

This makes R2 equal to 875Ω. But 875Ω is not a standard 1% resistor size (standard sizes include 866Ω and 887Ω). V(OUT), using the closest value of 866Ω, would be ~1.492V; V(OUT), using 887Ω, would produce a voltage level of ~1.5096V. If this value is not precise enough for your design, the value of R1 can be changed as well. Figure 15 illustrates this example of changing an analog-type regulator to provide 1.5V rather than 1.8V.

R1 = 1KΩVoltage Controller

R2 = 1.24KΩ

V(REF) = 800mV

V(OUT) = 1.8V

V(2) = V(OUT) - V(REF) = 1.8V - 800mV = 1V

R(2) = V(2) ÷ 800µA = 1V ÷ 800µA = 1.25KΩ

V(OUT) Actual = [R(1) + (R2)] × I(REF) = 1,240Ω × 800µA = 1.792V

I(REF) = 800µA

+

-


TN-47-22: Designing for LV FBDIMMsChanging the output voltage on digital-type voltage regulators

Figure 15: Example of changing analog-type of controller to 1.5V

Changing the output voltage on digital-type voltage regulatorsMost digitally controlled voltage regulators will have several input pins that configure an internal digital-to-analog converter (D/A) that regulates the controller to a constant reference voltage level. The D/A converter enables the voltage controller to be regulated by logic levels in addition to that of just an external voltage divider network.

Changing the output voltage for a digitally controlled regulator may be accomplished two ways. The external voltage divider network can be changed similarly as it’s done on the analog-type voltage regulators. For example, if the VID pins on the Intersil HIP6311 are set to a reference voltage of 1.25V and the regulated output is set for 1.8V, it can be easily changed to regulate the output voltage level to 1.5V. Refer to the figures below for additional information.

R1 = 1KΩVoltage Controller

R2 = 887Ω

V(REF) = 800mV

V(OUT) = 1.5096V

V(2) = V(OUT) - V(REF) = 1.5V - 800mV = 700mV

R(2) = V(2) ÷ 800µA = 700mV ÷ 800µA = 875Ω

V(OUT) Actual = [R(1) + (R2)] × I(REF) = 1,887 ohm × 800µA = 1.5096V

I(REF) = 800µA

Alternately, R1 could be changed if needed to fine tune V(OUT). For example:

R1 = 988Ω I(REF) = V(REF) ÷ R(1) = 800mV ÷ 988Ω = 809.7µA

R(2) = V(2) ÷ 809.7µA = 700mV ÷ 809.7µA = 866Ω

V(OUT) Actual = [R(1) + (R2)] × I(REF) = 1,854Ω × 809.7µA = 1.5012V

Both 988Ω and 866Ω are standard values for 1% resistors.

+

-

ΩΩ



Figure 16: Example of digital controller set to 1.8V

Figure 17: Example of changing a digital controller to 1.5V using different resistor values

The real advantage of a digital voltage regulator is that it can also be configured by the logic levels on the VID pins. In fact, this enables some system vendors to allow them to control the voltage through the BIOS. A good example of a digital voltage controller is the Intersil HIP6311, which has 5 input pins that are used to configure the internal D/A. The logic levels on these input pins provide a wide range of reference voltage levels in 25mV increments. For this device there are 32 voltage options selectable from the VID pins. (Intersil’s data sheet provides a table of VID pin codes for each voltage option. ) Using the same voltage divider configuration as the 1.8V example above, by simply changing the logic levels on the VID pins the voltage regulator will regulate the output voltage of 1.5V or 1.8V, and no other changes are required. With the voltage divider

R(1) = 9,880Ω

R(2) = 4,420Ω

R1 = 9,880Ω I(REF) = V(REF) ÷ R(1) = 1.25V ÷ 9,880Ω = 126.5µA


R2 = 4,420ΩV(REF) = 1.25V

V(PULL-UP) = 5V

V(OUT) = 1.80V

Voltage Controller

Dig

ital

-to

-an

alo

g c

on

vert

er

VID(1)

VID(2)

VID(3)

VID(4)

VID(0)

V(PULL-DOWN) = GND

+

-

V(REF) = VID logic

1,976Ω is not a standard 1% resistor value, so the next closest (1,978Ω).

R(1) = 9,880Ω

R(2) = 1,978Ω

R1 = 9,880Ω

I(REF) = V(REF) ÷ R(1) = 1.25V ÷ 9,880Ω = 126.5µA

R(2) = V(2) ÷ I(REF) = 250mV ÷ 126.5µA = 1,976Ω


V(2) = V(OUT) - V(REF) = 1.5V - 1.25V = 250mV

V(REF) = 1.25V

V(PULL-UP) = 5V

V(OUT) = 1.50V

Voltage Controller

Dig

ital

to

an

alo

g c

on

vert

er

VID(1)

VID(2)

VID(3)

VID(4)

VID(0)

V(PULL-DOWN) = GND

+

-

V(REF) = VID logic



resistor values of R1 = 9,880Ω and R2 = 1,978Ω, if the VID pins are equal to 19hex, the output voltage will be regulated to 1.5V; if the VID pins are set to 0Ehex ,the output voltage is regulated to 1.8V (see Figure 18 below).

Figure 18: Example of digital voltage regulator set (by VID pins) to V(OUT) = 1.8V

Figure 19: Exampe of setting memory voltage (by VID pins) on a digital regulator

As demonstrated, there are several methods for regulating memory voltage and they can vary by board manufacture, system requirements, and cost constraints. Likewise, there are several ways to change the memory voltage in the lab, including using variable resis-tors in the bias circuits, changing current going into the feedback loops, bypassing regu-lators with power supplies, or by modifying logic-based circuits, as shown above. The examples given are intended for informational purposes only; they should be discussed with the voltage controller manufacture and/or motherboard vendor before imple-mented.

R(1) = 9,880Ω

R(2) = 4,420Ω



R2 = 4,420ΩV(REF) = 1.50V

V(PULL-UP) = 5V

V(OUT) = 1.80V

Voltage Controller

Dig

ital

-to

-an

alo

g c

on

vert

er

VID(1)

VID(2)

VID(3)

VID(4)

VID(0)

VID = 0Ehex

V(PULL-DOWN) = GND

+

-

V(REF) = VID logic



R2 = 4,420ΩV(REF) = 1.25V

VID(1)

VID(2)

VID(3)

VID(4)

VID(0)

VID = 19 hex

R(1) = 9,880Ω

R(2) = 4,420Ω

V(PULL-UP) = 5V

V(OUT) = 1.50V

Voltage Controller

Dig

ital

-to

-an

alo

g c

on

vert

er

V(PULL-DOWN) = GND

+

-

V(REF) = VID logic


TN-47-22: Designing for LV FBDIMMsConclusion

ConclusionThe result of using LV FBDIMMs is an immediate reduction in power consumption, lower operating temperatures, and a possible increase in memory capacity within the channel. Micron can support all combinations of LV FBDIMMs, including 2GB (dual-rank, x8), 4GB (dual-rank, x4), 4GB (dual-rank, x8), 8GB (dual-rank, x4), which are based on our 1.5V, 1Gb and 2Gb DDR2 memory technologies. Several AMB suppliers currently support LV FBDIMMs, and many have new reduced-power designs. Although not discussed in this document, many of these new AMB designs support quad-rank for both FBDIMM and LV FBDIMMs. Quad-rank modules help to expand memory density and reduce power, as there is only one AMB per four ranks of memory. The most common quad-rank modules are built with 1Gb DRAM and are the 4GB (dual-rank, x8) or the 8GB (quad-rank, x4); both are available in the LV FBDIMM option.

The simplicity of modifying a platform design to accommodate LV FBDIMMs has been demonstrated. In some cases, it's as simple as changing the resistance values of a voltage divider circuit or the logic levels on a digital voltage regulator. In other cases, it may require a slightly different regulator or other biasing circuit. Taking advantage of LV FBDIMMs is very doable for most designs.

Low-voltage DDR2 provides the low-power advantages of DDR3 without having to change controllers. Low-voltage DDR2 is available in other configurations, including SODIMMs and loose components in x4, x8, and x16 options. Looking ahead, Micron is leading the initiative to develop low-voltage DDR3, which will provide many of the same benefits as low-voltage DDR2.

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Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respec-tive owners.

PDF: 09005aef832a92e7/ Source: 09005aef832a92c2 Micron Technology, Inc., reserves the right to change products or specifications without notice.tn4722_1.5v_fbdimm_design.fm - Rev A 3/6/08 EN 19 ©2008 Micron Technology, Inc. All rights reserved.

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Technical NoteIntroductionWhere does the memory power come from?What is an LV FBDIMM?Power advantages of Micron's Aspen Memory® LV FBDIMMsOther advantages of Micron's LV FBDIMMsSystem level options with LV FBDIMMs

Preparing to design in LV FBDIMMsImplementation of the VID pinsHardware implementation

Understanding analog-type voltage regulatorsChanging the output voltage on digital-type voltage regulatorsConclusion

tn-47-22: designing for 1.5, low-power...

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