tn-30: digitization at the antenna with dta- 9500 ...the simplified block diagram of the dta-9500 is...

TN-30: Digitization at the Antenna with DTA-9500, Featuring Multi-GSPS ADC and DACand Multiple 10 GbE Networks

Introduction

Digitization at the antenna has been the ultimate objective for implementing a trueSoftware Radio transceiver. However, the obstacles of achieving high dynamic range andhandling a large instantaneous bandwidth have prevented users from having a deployablesolution. The DTA-9500 addresses these challenges by utilizing D-TA's 10 GigabitSensor Processing Architecture. The DTA-9500 is available in two versions: <i>conduction cooled module operating from a 24/28V DC power supply providing twochannel digitization at 1.8 GSPS each and up to four (4) 10GbE links for high-speed datatransfer and <ii> air-cooled module that provides up to four channels at 1.8 GSPS eachand up to eight (8) 10GbE links for data transfer. Unlike other board level limitedcapability products available in the market place, the 10GbE links in the DTA-9500 allowthe ability to record and process in real time, the entire RF bandwidth for an extendedperiod of time. Thus, DTA-9500 is the only solution that allows recording of multiple 1.5GHz bandwidth RF signals for hours and hours.

System Architecture

The simplified block diagram of the DTA-9500 is shown in Figure 1. The DTA-9500includes a high speed dual ADC, with 12-bit precision that can handle 2-channels at 1.8GSPS each or a single channel at 3.6 GSPS. A single channel 12-bit DAC capable ofrunning at 4 GSPS is also available as an option. An integrated optional GPS receiver isalso available for GPS time-stamping and providing a GPS locked 10MHz reference.

Major Features:

• Dual 12-bit ADC providing 2-channel digitization at 1.8 GSPS each or 1-channelat 3.6 GSPS. The Air cooled version doubles the channel count (4-channel at 1.8GSPS each or 2-channel at 3.6 GSPS each)

• 12-bit DAC at 4 GSPS (single channel for the conduction cooled version, twochannels for the air-cooled version)

• Flexible clocking and multi-unit synchronization for higher channel count• Built in RF front end with gain, programmable attenuator and band-pass filters.

TN-30 Rev: A Updated: November 2011 www.d-ta.com

Specification subject to change

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The band-pass filters can be customized for specific application• Built in clock delay function in the ADC chip (36 fs steps) for calibration and

multi-unit synchronization• Large Virtex 6 (LX130T as standard, SX315T available as upgrade) FPGA• Up to four (4) 10GbE Networks (fiber) for full rate data transfer • Seamless operation with DTA-5000 record and playback unit for wideband RF

record and playback capability• 1GbE link (fiber) for command and control

ADC / DAC RF Front End

The ADC RF Front End is shown in Figure 2.

TN-30 Rev: A Updated: November 2011 www.d-ta.com AR 2


Figure 1: System Block Diagram of the conduction cooled DTA-9500 transceive system

ADC(ADC12D1800)

Front EndLNA, F ilter

RFIn

10GbEPHY

10

GbE

Op

tical

Mo

dule

10GbEPHY

10

Gb

E O

ptica

lM

od

ule10GbEPHY

10G

bE

Op

tical

Mod

ule

10GbEPHY

10G

bE O

ptica

lM

odu

le

2 / 4ports

1G

bE

Opt

ica

l

V6 FPGA V6 FPGA

REF IN/OUT

CLKIN/OUT

SYNCIN/OUT

TRIG2 IN/OUT

PLL

,C

LOC

KG

EN

ER

ATT

ION

& D

IST

RIB

UT

ION

DDR3DDR3

1-ch at 3.6 GSPS OR2-ch at 1.8 GSPS

TRIG2 IN/OUT

GP

S R

EC

EIV

ER

PPS, LOC,TIME, ETC.

GPS IN(from GPSAntenna)

1G

bE O

ptic

al

DAC(MAX19693)

4ports

Filters, Amp

RF Out1-ch at 3.6 GSPS

DDR3DDR3 DDR3DDR3 DDR3DDR3 DDR3DDR3 DDR3DDR3 DDR3DDR3 DDR3DDR3NAND

Figure 2: ADC RF Front End offers a maximum gain of 18 dB

~~~~~~

BPF AMPPROGATTN

~~~~~~

BPF AMP

~~~~~~

BPF

TO ADCXFRMRBALUN

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The DAC RF Front End is shown in Figure 3.

The attenuators used in the RF Front End are software programmable in 0.25 dB stepswith a maximum settable value of 31.75 dB. These programmable attenuators can be usedto balance gain. When used in conjunction with the clock delay feature of the ADC, itoffers a powerful way of accurate synchronization of multiple channels.



Added Features that makes DTA-9500 ideal for a variety of applications

RF Front End: The DTA-9500 has asophisticated RF front end with customizablefilters, LNA and programmable attenuator(0.25 dB steps). The max gain for the ADCfront end is 18dB, while for the DAC it is 7dB.

Full Data Rate: Four 10GbE network links,allow the DTA-9500 to handle the entire RFbandwidth and enable continuous andsustained recording of the RF spectrum.

GPS Receiver: The in-built GPS receiverallow GPS time stamping on the data as wellas having a GPS locked sampling.

Clocking Options: The DTA-9500 sampleclock can be internal or external. In case, it isinternally generated, the internal synthesizercan be locked the internal (100 MHz TCXO)or external reference signal (10 to 100 MHz).

Ideal for ECM / EW applications: Byintegrating the DAC in the unit, the DTA-9500 is ideal for EW, ECM, DRFM

applications. The received signal can besuitably modified to be transmitted out viathe high speed DAC for lowest latency.

FPGAs available for user Processing: TheDTA-9500 has two Virtex 6 FPGAs that canbe used to implement custom DSP modules.The standard FPGA is LX130T and can beupgraded to SX315T.

Conduction Cooling and Digitization at theAntenna: The DTA-9500 has four fiber linksfor transfer of data. The conduction cooledbox enables the unit to be placed near theantenna for maintaining performance whilethe fibers allow data transfer over a longdistance. The 1GbE control link is also overfiber.

10GbE Networks: Like all D-TA products,the DTA-9500 implements four (4) 10 GbEnetworks for high speed data transfer forrecording and processing. This allows realtime processing and recording of the entirebandwidth.

Figure 3: DAC RF Front End offers a maximum gain of 7 dB

~~~~~~

BPF AMPPROGATTN

~~~~~~

BPF

XFRMRBALUN

FROMDAC

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Major Specification

FEATURES VALUE COMMENTS

ADC Section

Number of ADC Channels 1-ch at 3.6 GSPS Or2-ch at 1.8 GSPS each

ADC Chip ADC12D1800 From National Semiconductors

Maximum Sample Rate 3.6 GSPS

Minimum Sample Rate 300 MHz Contact Factory for extending range

Precision 12 bits nominal Data is also available as 8-bit to reducedata rate

Full Scale Input 0 dBm With 0 dB gain in the RF Front End

Input Impedance 50 Ohm

Input Coupling AC Coupled with transformer On board RF Front End provided

Input 3-dB Bandwidth 450 to 1500 MHz Limited by standard BPFs. BPFs can beremoved or changed

ADC Input Connector 50 ohm SMA Female

SFDR < -65dBc ADC data sheet performance achieved

Integrated SNR 58 dB ADC data sheet performance achieved

ADC RF Front End NoiseFigure

7 dB With Maximum Gain

ADC RF Front End Gain 18 dB

ADC RF Front End IP3 35 dBm Output IP3

ADC RF Front End GainControl

31.75 dB in 0.25 dB steps Software programmable attenuator.

DAC Section

Number of DAC Channels 1

DAC Chip MAX19693 From Maxim IC

Maximum Conversion Rate 4 GSPS

Precision 12 bits nominal

Output Impedance 50 Ohm

DAC Output Connector 50 Ohm SMA Female

SFDR < -68 dBc Limited by the DAC performance. Nonincluding FDAC/4, FDAC/2, FDAC/2-FOUT

spurs

DAC RF Front End Gain 7 dB

DAC RF Front End IP3 35 dBm Output IP3



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DAC RF Front End GainControl

31.75 dB in 0.25 dB steps Software programmable attenuator.

Maximum Output Level 5 dBm DAC operating at full scale

Clock Section

Internal Reference Clock 100 MHz TCXO

TCXO Phase Noise(typical)

< -100 dBc/Hz @ 100 Hz offset< -150 dBc/Hz @10 kHz offset

TCXO Frequency Stability +/- 5 ppm over all+/-1 ppm (initial tolerance at25C)

PLL Chip ADF4350 From Analog Devices with integratedVCO

VCO Integrated with the PLL chip

External Clock andreference Input

50 Ohm SMA Female

External Reference 10 to 100 MHz

External Reference Level Sine +6 dBm (Maximum)

Data FPGA Section

Number of FPGAs 2

Standard FPGA Virtex 6: XC6VLX130T FFG1156 package used

Upgraded FPGA as option Virtex 6: XC6VSX315T Other options may be provided (contactfactory)

10GbE MAC Implemented in the FPGA

10GbE Interface XFP: 850 nm for Short ReachMulti Mode Fiber

Up to four (4) interfaces

Memory per FPGA 4 x 128 Mbytes of DDR3SDRAM

Total 1 Gbytes of DDR3 SDRAMdistributed over 2 FPGAs

Input Power

Input Voltage Conduction Cooled: 24 /28V DCAir Cooled: AC Power

Maximum PowerConsumption

150 W

Mechanical

Dimension – ConductionCooled

11.5” (W) x 11” (D) x 3.5” (H) Flanges provided for mounting. Contactfactory for exact mechanical drawing



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Dimension – Air Cooled 1U high, 20” deep, 19” rack-mountable

Maximum Mass 8 kg (17.7 lbs)

Environmental

Operating Temperature -20C to +70C ambient(conduction cooled)0 to +55C ambient (air cooled)

Ambient at cold plate. The environmentmust be able to adequately dissipate thethermal load of the DTA-9500. Provisionsof attaching an external fan to blow air onthe conduction cooled chassis available.The air cooled chassis comes with fansand the user has to ensure that airflow isnot blocked.

DTA-9500 Configurations

The DTA-9500 is a modular design and thus various configurations can be easilysupported. Customized packaging of these configurations are also possible. Figure 4shows the ADC only configuration with 2 fiber links.

Figure 5 shows the ADC only configuration with 2 fiber links.



Figure 4: System Block Diagram of DTA-9500S-1R-2F (ADC only with two 10GbElinks)

ADC(ADC12D1800)

Front EndLNA, F ilter

RFIn

10GbEPHY

10G

bE O

ptical

Modu

le

10GbEPHY

10Gb

E O

ptica

lM

odule

2 / 4ports

1G

bE O

ptic

al

V6 FPGAV6 FPGA

DDR3DDR3


DDR3DDR3 DDR3DDR3 DDR3DDR3DDR3DDR3 DDR3DDR3 DDR3DDR3 DDR3DDR3

NAND

REF IN/OUT

CLKIN/OUT

SYNCIN/OUT

TRIG2 IN/OUT

PLL

,C

LOC

KG

EN

ER

AT

TIO

N&

DIS

TR

IBU

TIO

N

TRIG2 IN/OUT

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Similar configurations are also available with the DAC only version.



Figure 5: System Block Diagram of DTA-9500S-1R-4F (ADC only with four 10GbElinks)

ADC(ADC12D1800)

Front EndLNA, Filter

RFIn

10GbEPHY

10G

bE

Optica

lM

odule

10GbEPHY

10GbE

Optica

lM

odule

10GbEPHY

10GbE

Optica

lM

odule

10GbEPHY

10G

bE O

ptica

lM

odule

2 / 4ports

1G

bE O

ptic

al

V6 FPGA V6 FPGA

DDR3DDR3


DDR3DDR3 DDR3DDR3 DDR3DDR3 DDR3DDR3 DDR3DDR3 DDR3DDR3 DDR3DDR3

NAND

REF IN/OUT

CLKIN/OUT

SYNCIN/OUT

TRIG2 IN/OUT

PLL

,C

LOC

KG

EN

ER

ATT

ION

& D

IST

RIB

UTI

ON

TRIG2 IN/OUT

Figure 6: The same modules used for the air-cooled version to achieve up to fourchannels sampling at 1.8 GSPS each with up to eight 10GbE links

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The same modules can be packed in a air-cooled chassis to provide four channels at 1.8GSPS each with eight 10GbE links as shown in Figure 6 and Figure 7 .

High Speed Continuous and Sustained Record / Playback

The four 10GbE interfaces in the DTA-9500 enable continuous and sustained recordingof wideband RF signals as shown in Figure 8. The configuration shown is capable ofrecording a 3.2 Gbytes/sec on a continuous and sustained basis. Thus, a single channel at3.2 GSPS sampling rate (with 8-bit data) or two channels at 1.6 GSPS each can berecorded to disks.

Using the air-cooled chassis, up to four ADC channels at 1.6 GSPS each, or two channelsat 3.2 GSPS each can be recorded for an extended period of time as shown in Figure 9.The total recording rate for the configuration is 6.4 Gbytes/sec.



Figure 8: Recording of RF signal with full 1.5 GHz bandwidth. The configurationshown can record at 3.2 Gbytes/sec and offers up to 19.2 TB of storage.

Figure 7: An air-cooled version of the DTA-9500 with 2 ADC channels at 3.6 GSPSeach or 4 channels at 1.8 GSPS each

ADC 1 ADC 2

2 x Virtex 6 FPGA

Clock &Control

10GbE 10GbE 10GbE 10GbE

ADC 3 ADC 4

2 x Virtex 6 FPGA

Clock &Contro l


User Laptop / Computer(GUI / Control API)

10GbE

10GbE

10GbE

10GbE

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Clocking and Multi-Unit Synchronization

The DTA-9500 is designed to make multi-unit synchronization easy and allow immenseflexibility and scalability. It provides an extremely versatile clock generation mechanismas well as re-timing feature for control signals to allow for synchronization for high speedADCs.

Clock Generation and Distribution

The clock generation and distribution circuit is shown in Figure 10. The DTA-9500allows the following clocking options for the user:

• Internally generated sampling clock locked to an internal 100 MHz TCXO servingas the reference source

• Internally generated sampling clock locked to an externally provided reference

• Externally provided sampling clock



Figure 9: Recording at 6.4 GSPS each with the air-cooled DTA-9500. The total storageis 38.4 TB

ADC 1 ADC 2

2 x Virtex 6 FPGA

Clock &Control


ADC 3 ADC 4

2 x Virtex 6 FPGA

Clock &Contro l


1 GbE Switch

User Laptop / Computer(GUI / Control API)

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The ADC and the DAC section have separate clock generation and distribution sectionand thus may be run at different clock frequencies or locked to different referencesources. By using the sampling clock in/out feature they can also be operated from thesame sampling clock. Note that the re-timing clock is also created from the same sourceand can be at an integral multiple of the ADC sampling clock.

Re-timing of Control Signals

For seamless multi-unit synchronization, there is a re-timing circuit in the DTA-9500 thatretimes the control signals using the high speed sampling clock, as shown in Figure 11.

The ADC chip has a feature where the trigger signal can be embedded in the data. In thismode, only the 11 MSBs are used for sampling the analog signal and the LSB is theTrigger signal. This mode is also supported with the design as shown in Figure 11. Pleaserefer to the ADC data sheet (ADC12D1800 from National Semiconductor) for moredetails regarding the other signals in the ADC.



Figure 10: Clock Generation and Distribution

Internal RefTCXO(100 MHz)

Reference In

Reference Out

ADF4350

PLL &VCO

REF IN

RFoutA

LC Ba

lun SCLK In

SCLK Out

SCLK_180deg_Out

RFoutBThe 10MHz Out from the internal GPS (not shown in this diagram) can be connected to the Reference In for achieving a GPS locked Reference signal.

LC Ba

lun Retiming Clock

RT_CLK

RT_CLK In

RT_CLK Out

RT_CLK_ 180deg_Out

CLK

ADC

RCLK

RCLK In

DCLK (I, Q)

ADC_DCLK ToFPGA, Ret iming

RC Out 1

RC Out 2

RCOut1

RCOut1

DCLK_RSTFromRetiming

Section

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The clock generation and distribution design makes multi-unit synchronization extremelyeasy. For multi-unit synchronization, the sample clock, trigger, etc. are generated in theMaster unit and distributed to all units (slave as well as the master unit) by using an



Figure 11: Retiming DCLK RST and TRIG 1 signals

Figure 12: Retiming of other control signals

>

ADC DCLK (From ADC)

D Q

Internal DCLK RST

DCLK RSTIn

>

RT_CLK

D Q

DCLK RST Out

>D Q

>D Q

FPGA_DCLK_RST In(To FPGA)

>

ADC DCLK (From ADC)

D Q

Internal Trig 1

TRIG 1 In

>

RT_CLK

D Q

TRIG 1 Out

>D Q

>D Q

FPGA_TRIG 1 In(To FPGA)

DCLK RST

TRIG 1

ADC DCLK RST(To ADC)

>

D Q

>

D Q

D Q D Q

D Q D Q

D Q D Q

>

D Q

Internal EVENT 1

>

D Q

D Q D Q

D Q D Q

D Q D Q

ADC DC LK (From ADC)RT_C LK

TRIG 2 In

EVENT 1 In

EVENT 2 In

EVENT 3 In

Internal TRIG 2

Internal EVENT 3

Internal EVENT 2

FromFPGA EVENT 1 O ut

EVENT 2 O ut

EVENT 3 O ut

FPGA_EVENT 1 In

FPGA_EVENT 2 In

FPGA_EVENT 2 In

To FPGA

TRIG 2 O ut

FPGA_TRIG 2 In(To FPGA)

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external splitter (see Figure 13). The clock delay feature in the ADC can be used tocorrect any imbalance. All control signals are re-timed using the same fast sampling clockto ensure synchronization in all units.

DTA-9500 Configurations

Table 1: DTA-9500 Configurations

Number Description

DTA-9500S-1RT-4FG Tranceive system in a conduction cooled chassis with 1-ch ADCat 3.6 GSPS (or 2-ch ADC at 1.8 GSPS each), 1-ch DAC at 4GSPS, four 10 GbE interfaces and a GPS receive module.

DTA-9500S-1R-2F Receive only system in a conduction cooled chassis with 1-chADC at 3.6 GSPS (or 2-ch ADC at 1.8 GSPS each) and two (2)10 GbE interfaces.



Figure 13: Multi-Unit Synchronization

Ref OutRef In

SCLK In SCLK Out

RT_CLK In

RT_CLK Out

RC Out1RCLK In

DCLK_RST Out

DCLK_RST In

TRIG 1 In

TRIG 1 Out

TRIG 2 Out

TRIG 2 In

1:2 RFSplitter

Ref OutRef In

SCLK In SCLK Out

RT_CLK In

RT_CLK Out

RC Out1RCLK In

DCLK_RST Out

DCLK_RST In

TRIG 1 In

TRIG 1 Out

TRIG 2 Out

TRIG 2 In

1:2 RFSplitter

Same S ignal(Created Internally)

DTA-9500: Master DTA-9500: S lave

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Number Description

DTA-9500S-1R-4F Receive only system in a conduction cooled chassis with 1-chADC at 3.6 GSPS (or 2-ch ADC at 1.8 GSPS each) and four (4)10 GbE interfaces.

DTA-9500-AC-2R-8F Receive only system in an air-cooled chassis with 2-ch ADC at3.6 GSPS (or 4-ch ADC at 1.8 GSPS each) and eight (8) 10 GbEinterfaces.

DTA-9500-AC-1R-4F Receive only system in an air-cooled chassis with 1-ch ADC at3.6 GSPS (or 2-ch ADC at 1.8 GSPS each) and four (4) 10 GbEinterfaces.

Performance

ADC performance is shown in Figure 14, Figure 15, and Figure 16.



Figure 14: ADC Performance at Fs at 1.0 GSPS with input signal at 140 MHz

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Figure 15: ADC Performance at Fs at 640 MHz with input signal at 140 MHz

Figure 16: ADC Performance at Fs at 1.6 GSPS with input signal at 140 MHz

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FPGA Applications

D-TA has extensive FPGA design capability including having standard cores like FFT,DDC etc. D-TA can also offer customized FPGA design services to implement userspecific application in the FPGAs. Please contact factory for details.

Customization

DTA-9500 can be easily customized to meet specific user requirements. Please contactfactory to discuss your specific requirement. Typical customization can include:

• Custom FPGA application coding• Different packaging options

D-TA Systems also provides custom development capability to meet specific userrequirements. D-TA Systems offers technical leadership in all aspects of sensorprocessing and sensor interfacing solutions – RF design, mixed signal and FPGA design,10GbE design, real time multi-threaded and multi-core software design, etc.

Programming Interface and API support

The DTA-9500 can be programmed over a 1GbE interface (optical). The softwaredevelopment kit contains extensive API functions that allow the user to control the unit.The SDK also allows the user to very easily integrate the control functionality of theDTA-9500 into user applications.

The SDK also includes the Data SDK that can be used for development of multi-threaded, multi-core applications running on standard servers using the 10GbE interfacesfor data transfer. The SDK shields the users from mundane data management issues andallows users to concentrate on developing their own applications. Please refer to TN-14for more details.

Training

We also offer hand-on interactive training either in our fully equipped Training Center orin your facility. The Training Center boasts of a fully equipped conference room and adedicated Training Laboratory with access to D-TA products as well as test equipmentlike Oscilloscopes, Spectrum Analyzers, Network Analyzers, Signal Generators, etc. Thehand-on training cover a full discussion of the SDK structure, detailed productdiscussions and actual demo application development with actual equipment. The userwould be able to create processing applications and determine optimal speed andperformance. The specific applications are tailored to meet the user's exact requirement.

We also offer custom application development to meet the users' exact requirement.Please contact us for more information.



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Conclusion

The DTA-9500 is an ideal wideband SDR platform for a variety of applications. Togetherwith the high speed and sustained record / playback option the DTA-9500 providesunprecedented wideband capability unmatched in the industry. DTA-9500 is the onlysolution available that allows transfer of the entire bandwidth in a continuous andsustained fashion. The 10GbE back-end allow the fastest data transfer capability andenables real time recording and monitoring of the entire bandwidth on a continuous andsustained basis.

Contact Information

US INTERNATIONAL

Toll Free: 1-877 382-3222 +1 (613) 745-8713

www.d-ta.com

Sales: [email protected]

Support: [email protected]



tn-30: digitization at the antenna with dta- 9500 ...the simplified block diagram of the dta-9500 is...

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