TMS320TCI6616 Breakthrough performance for wireless base stations

Product bulletin

With an explosive growth in data usage, cellular networks are evolving to newer standards with greater bandwidth and speed. Mobile device users are devouring data at tremendous rates on their smartphones and superphones, which can degrade performance for all users. Mobile phone users expect that their calls will go through, regardless of network traffic. This explosion of data growth impacts the base station, forcing operators to move to heterogeneous networks combining macro cells and small cell solutions to affordably deliver the bandwidth needed. Multiple input, multiple output (MIMO) antenna arrays and advanced receivers are key elements of the new wireless standards that increase the

bandwidth capabilities of the network.

• Highestperformingmulticorebasestation systemonchip(SoC)onthemarkettoday whichdeliversunmatchedthroughputand lowestlatencyformulti-standardwireless basestationsdelivering2Xthewireless systemperformanceofanyother basestationSoC• TI’snewC66xDSPcombinesfloatingand fixedpointonthesamecore,delivering floating-pointperformanceatfixed-point speedsforthefirsttime.• Onlysolutiontofeaturecoprocessorsfor everystandard,includingWCDMAchip rate–noFPGA/ASICrequired.• NetworkcoprocessorandMulticore NavigatorcombinetoprovideLayer2and transportaccelerationforallwirelessbase stationstandards.• FirstproductwithTI’snewKeyStone architecture,enablingscalabilityand portabilityfrommacrotosmallcells reducingproductdevelopmentexpense.• MulticoreNavigatorbringssingle-core simplicitytomulticoreSoCs.• Bestpower/performanceratio,coupledwith uniquepower-savinghibernationmodes, deliversthelowestpowerforbasestations.• Leverageshigh-performance40-nm processtechnology

Key features

TheTMS320TCI6616isthefirstdedicatedbasestationsystem-on-chip(SoC)tocombinefield-provenPHYtechnologywithhigh-performancepacketprocessing.Itisideallysuitedforthedata-centricperformancewire-lessnetworkoperatorsaredemandingtoday.ItsmultipleTMS320C66xDSPcoresprovideprogrammablepowerthatallowsbasestationmanufacturerstodeliverthespectralefficiencythatoperatorscrave. TI’sTCI6616isascalableSoCbasedonTI’sKeyStonearchitectureandC66xDSPcore.Itfeaturesthehighestfixed-andfloating-pointoperation,allowingbasestationdesignerstodeliverthecapacityandperfor-mancetomeettomorrow’sdemandstoday.TheTCI6616enablesmanufacturerstoreducethecostperbitontheoperator’sexpensiveairinterface,aswellaslowerpowerconsump-tionfornewbasestationdesigns.MulticoreNavigator,aqueue-basedpacketstructure,coupledwithTI’sOpenNavigatorprogramminginterface,givesdesignerstheabilitytoeasilyadddifferentiating,value-addedfeatures. Withbothfloating-andfixed-pointDSP

coresonthesamedevice,theTCI6616enablesbasestationdesignerstotakeadvantageofrapidalgorithmprototypingandquicksoftwareredesigns,reducingcostsanddevelopmenttime.BecausetheC66xcoresaresopowerful,significantlyfewercoresareneededtoprovidefourtimestheprocessingpowerofpreviousgenerationsofTIproces-sorsandmorethandoubletheprocessingpowerofanyannouncedcompetitiveproducts.Designerswillenjoysimplifiedprogram-mingwithfewercores,alongwithincreasedperformance.

TCI6616 high-performance solution for base stationsDesignedspecificallyforwirelessinfrastruc-turebasebandapplications,theTCI6616isanidealsolutionformacrobasestationsandenablesSoCbasebandsolutionsforGSM/EDGE,UMTS,TD-SCDMA,WiMAXandLTEapplications.TomakethetransitionfromC6000™DSPseasier,theTCI6616isbackwardcode-compatible,allowingsoftwarereuseandmaintainingvalue-addeddesignsandIP.In

addition,TI’sTCI6616leveragestheKeyStonearchitecturetoenablecodecompatibilityandscalabilitytomeettheneedofallbasestations,fromsinglesectorsmallcellstomulti-sectormacrocells.Withonesoftwarebasedrivingavarietyofbasestationproducts,developerswillrealizethehighestR&Defficiencypossibleaswellasoptimizedproductcosts. TheTMS320TCI6616isbasedon40-nmprocesstechnologyanddelivers4.8GHzof

TMS320CTCI6616 block diagram

2

anddatamemoriesontheTCI6616deviceare32KBeachpercore.Thelevel-2(L2)memoryissharedbetweenprogramanddataspaceandisatotalof4,096KB(1,024KBpercore).TheTCI6616contains2,048KBofmulticoresharedmemory(MSM)thatisusedasasharedL2SRAMorsharedL3SRAM.AdedicatedMulticoreSharedMemoryController(MSMC)preventsmemorycontentionbetweenthecoresandarbitratesaccesstothesharedmemorybetweenthecoresandotherIPblocks. TheTCI6616hasahigh-performanceperipheralsetwitheverythingneededtodeveloprobustbasestationsofvaryingcoverageandcapacity,including:• I2C,SPIandUART• PCIExpressportwithtwolanessupporting GEN1andGEN2• Sixteen64-bitgeneral-purposetimers(also configurableasthirty-two32-bittimers)

C66X Core

L2 memory/cache, 1MB

C66X Core

L2 memory/cache, 1MB

C66X Core

L2 memory/cache 1MB

Multicore Navigator

Tera

Net 2

Memory system

Multicore shared memory controller (MSMC)

Shared memory 2 MB

DDR3-64b

System elementsPower

management System monitor

Debug EDMA

IPsec/GTP-U

Cryptographic

Fast path

IEEE 1588

Network coprocessor

Peripherals and I/O

SRIO x4 AIF2 6x

SGMII, 1588 PCIe 2x

GigE switch UART, SPI, 12C

Layer 3 coprocessor

Message processing

Layer 2 coprocessors

RoHC

QoS

Air ciphering

RLC/MAC

Scheduler Fast path

Layer 1 coprocessors

Turbo encoder

Viterbi decoder

Turbo decoder

FFT/DFT

TFCI CQI, Reed Muller

Uplink CR Downlink CR

InterferencecancellatationHy

perli

nk 5

0

C66x DSPCore

L2 memory/cache 1 MB

rawDSPprocessingpower,aswellasperfor-manceofuptoor153,60016-bitGMACspersecond,makingitacost-effectivesolutionforhigh-performanceDSPprogrammingchal-lenges.Withtheadditionofthefloating-pointcapability,theTCI6616offersperformanceofupto76billionfloating-pointoperationspersecond(GFLOPs),makingittheindustry’smostpowerfulfloating-andfixed-pointSoC.Byincorporatingbothfixed-andfloating-pointcapabilitiesonthesamecore,theTCI6616isabletoperformuptofivetimesfasterthanafixed-pointimplementationalone.Inaddition,thedevelopmentanddebuggingcycletimeforcomplexalgorithmsissignificantlyreducedfromamultiple-monthcycletojustafewdays. TheTCI6616integrateslargeon-chipmemoryorganizedasatwo-levelmemorysystem,minimizinglatencyandincreasingsystemperformance.Thelevel-1(L1)program

• 16-pingeneral-purposeinput/output (GPIO)portwithprogrammableinterrupt/ eventgenerationmode• Twotelecomserialinterfaceports(TSIPs) supporting1,024DSOsperTSIP.• MulticoreNavigatorforhardware- accelerateddispatch• FourlanesofserialRapidIO®(SRIO), compliantwithRapidIO2.1specforup to5-Gbpsoperationperlane• 64-bitDDR3SDRAMinterface• 16-bitexternalmemoryinterface(EMIF) forconnectingtoflashmemory(NAND andNOR)andasynchronousSRAM• Second-generationSERDES-based antennainterface(AIF2)capableofup to6.25Gbpsoperationperlinkwithsix high-speedseriallinks,complianttoOBSAI RP3andCPRIstandards

Forefficientcommunicationsbetweenthedeviceandthenetwork(aswellasotherdevices),theTCI6616includesanetworkcoprocessorthatconsistsof:

• Two10/100/1000Ethernetmediaaccess controllers(EMACs),whichprovidean efficientinterfacebetweentheTCI6616 DSPcoreprocessorandthecorenetwork• Managementdatainput/output(MDIO) module(alsopartoftheEMAC)that continuouslypollsall32MDIOaddresses inordertoenumerateallPHYdevicesin thesystem• PacketcoprocessorthatprovidesL2to L4classificationfunctionalitiesandthe processingpowerofupto1.5Gbps• Cryptoblockcapableofwire-speed processingon1-GbpsEthernettrafficon IPSec,SRTPand3GPPairinterfacesecurity protocols• EmbeddedEthernetswitchthatallows multipledevicestobeconnectedthrough SGMII,eliminatingtheneedforaboard- levelEthernetswitch

TheTCI6616hasninehigh-performanceembeddedcoprocessorstoperformintensivesignalprocessingfunctionscommontowirelessbasestationapplications.Theresultisincreasedoverallsystemperformance.ThecoprocessorsarefourenhancedViterbidecodercoprocessors(VCP2_A,VCP2_B,VCP2_CandVCP2_D),twothird-generation

turbodecodercoprocessors(TCP3d_AandTCP3d_B),turboencodercoprocessor(TCP3e)andtwofastFouriertransformcoprocessors(FFTC_AandFFTC_B).Together,theysignifi-cantlyacceleratechannelencoding/decodingoperations.AlsoincludedintheTCI6616arefourtightlycoupledrake/searchaccelera-tors(RSAs)forcodedivisionmultipleaccess(CDMA)assistancewithchip-rateprocessing.

Faster coprocessors for optimized base station designsSince2001,TIhasdeliveredradiocoprocess-ingfunctionsconsistingofconfigurableIPblockstooffloadprocessingdemandsaswellasincreaseoverallsystemperformance.TI’scoprocessorsalsoreducebasestationpowerrequirementsanddissipationaswellasboardcomplexity,makingnewproductseasiertodesign,buildanddebug. Aswirelessradiostandardsevolveandrelatedimplementationsbecomestandardized,eachevolutionofTI’swirelessSoCdeviceshasincludedmoreandmoreradioaccelera-tion/coprocessing,andassuchprovidesacompellingroadmaptolowerpowerandcostswhiledeliveringhigherperformingbasestationsolutionsforourcustomers.TI’sSoCstrategyofintegratingDSPcoresalongwithcoproces-sorsisthesimplestandmosteconomicalapproachtowirelessbasestationsolutionsandcontinuestobethemarket-leadingsolutiontoday.TI’scoprocessorseliminateexternalFPGAsandASICsthatwerepreviouslyneededtodelivertheperformanceneededforbasestations,loweringthesystemcostanddesigncomplexity. TheTCI6616hasmultiplededicatedhigh-performanceembeddedcoprocessorstoperformintensivesignalprocessingfunctionscommontowirelessbasestationapplica-tions.ThecoprocessorsareenhancedViterbidecodercoprocessors,third-generationturbodecodercoprocessor,turboencodercoproces-sorandfastFouriertransformcoprocessors.ItalsoincludesWCDMAspecificspreadinganddespreadingenginesandrakesearchcopro-cessorstoassistwithchip-rateprocessing.

Delivering full multicore entitlementTI’sTCI6616multicoreSoCarchitectureisthefirstofitskindtoprovidefullmulticore

entitlement,allowingforadequatesystembandwidthtoprovidenon-blockingaccesstoallprocessingcores,peripherals,coproces-sorsandI/Os.InnovationswhichunleashfullmulticoreentitlementareMulticoreNavigator,TeraNet,MulticoreSharedMemoryController(MSMC)andHyperlink.

Multicore Navigator – TI’sMulticoreNavigatorisaninnovativepacket-basedmanagerthatcontrols8,192queuesandabstractstheconnectionsbetweenthevarioussubsystemsontheTCI6616.Withaunifiedinterfaceforcommunication,datatransferandjobmanagement,MulticoreNavigatorenableshighersystemperformancewithfewerinter-ruptsandreducedsoftwarecomplexitywitha“fireandforget”paradigm. MulticoreNavigatorwillinstructthenextfreeDSPcoretoreadthejobandprocessit.MulticoreNavigatorisabletosimplifythesoftwarearchitectureaswellasimproveperformanceofbasestationswith:• Dynamicresource/loadsharing• OffloadingofCPUoverhead/delayrelated tointer-subsystemcommunications• Hardware-basedtaskprioritization• Dynamicloadbalancing• Commoncommunicationmethodologyfor allIPblocks(software,I/Oandaccelerators) TeraNet – TeraNetprovidesahierarchalswitchfabricwhichcombinestodeliverover2terabitsofbandwidthfordatatransferwithintheSoC.Thisvirtuallyguaranteesthatthe

Coprocessor Total performance(@1.2-GHz core frequency)

FFT/DFT 1,272MSPS@256-FFT1,122MSPS@192-DFT

Turbodecode LTE–313Mbps@6144blocksizeWCDMA–201Mbps@5114blocksize

Turboencode LTE–643Mbps@6144blocksizeWCDMA–639Mbps@5114blocksize

Viterbidecoder >38Mbps(K=9)Mbps=9)

RakeSearchAccelerator 32-bitmultiplicationpercycleWCDMAdespreading 256AMRuserssupported@eightfingersWCDMAspreading 256userssupportedwithtworadiolinksanddiversityEncryption/decryptionIPSec 2.8GbpsFirmware-basedinfrastructure,multicoreaccelerationorLayer2dataprocessing

coresorcoprocessorsareneverstarvedfordataandcandelivertheentitledprocessinghorsepower.Astheswitchfabricisarchitect-edhierarchicallyratherthanbeingaflatcrossbartheoverallpowerconsumptionismuchlowerinidlestatesandalsodeliverssystemswithminimallatencywhichisakeyrequire-mentinnext-generationbasestations.

Multicore Shared Memory Controller (MSMC) – TI’sTCI6616includesauniquememoryarchitectureforenhancedperfor-mance.TI’sMulticoreSharedMemoryControl-ler(MSMC)allowsthecorestodirectlyaccesssharedmemorywithouthavingtouseanyofTeraNet2’sbandwidth.TheMSMCarbitratesaccesstosharedmemorybetweenthecoresandotherIPblocks,eliminatingmemorycontention.SharedmemoryaccessforcodeisnearlyidenticalinlatencytolocalL2access,withhighlyeffectiveprefetchmechanismsforcodeanddata. TI’sTCI6616’sDDR3isa1,600MHz,64-bitbuswith8GBofaddressablememoryspace.TieddirectlytotheMSMC,theDDR3reduceslatencyassociatedwithexternalmemoryfetchesandprovidesthespeedincreaseandsupportneededforlargerapplicationsthatoperateonlargeamountsofdata,whichisessentialforadvanced3Gand4Gbasestations.

Hyperlink – Hyperlink,with4lanesatupto12.5Gbps/lane,isaproprietaryhigh-speedinterconnectallowinglowprotocolandhigh-speedcommunicationandconnectivitytootherKeyStonedevicesprovidingOEMs

3

TI’s coprocessors

aseamlesspathtoscalablesolutions.TheHyperlinkontheTCI6616worksinconjunctionwiththeMulticoreNavigatortotransparentlydispatchtaskstotandemdevicessotheyex-ecuteasiftheyarerunningonlocalresources.

TCI6616 as Layer 2 and transport processing engineTCI6616combinestheunmatchedPHYprocessingcapabilitieswithdedicatedcopro-cessorsfortheLayer2andtransportlayerprocessing.Thisenablesdesignerstocreatebasestationswithoutaseparatenetworkprocessortherebyreducingboardcomplexityandcostwithoutcompromisingperformance.Thenetworkcoprocessorenablesfast-pathprocessinginthetransportnetworklayeranddeepintotheLayer2oftheradionetwork.WithinthenetworkcoprocessorinsidetheTCI6616,thePacketAcceleratorandtheSecurityAcceleratorperformfullyacceleratedautonomouspacket-to-packetprocessing.TheyleveragetheMulticoreNavigatorwhichutilizesazero-copyapproachtooptimizedataprocessingatalllayers.Classsificationandordering,multicore-accessiblestorage,memorymanagement,segmentationsandreassembly,anddeliveryacrossmultiplecoresanddevicesareallsupportedbyMulticoreNavigator.Layer2data-planeandtransportplaneoverheadcanbereducedby10-15xduetothefast-pathandzero-copyprocessingenabledbytheMulticoreNavigator.

Lowest power consumption for performanceTIhasahistoryofprovidingthelowestpowerwirelessbasestationSoCsonthemarket.TIisabletoachieveitsultimatelowpowerthroughthecombinationofitsprocesstechnologyincluding,SmartReflex™technologyandtheproactiveuseofpowermanagementtech-

niques,(suchasadaptivevoltagescaling)ineverywirelessbasestationsemiconductordevicetokeepactivepowerataminimum.Inaddition,TIhasleverageditsextensiveknowledgeinthewirelessbasestationmarkettoestablishmultiple,dynamicpowermodesfortheTCI6616device(shownintheabovediagram),allowingcustomerstoworkwithnetworkoperatorstocustomizeaprogram-mablestrategyforoptimizingpowerusagebasedonoperationandregionalusemodes.UtilizingTI’spowermanagementtechniquesontheTCI6616enablesdesignerstodevelopcompellingbasestationsolutionscapableofoperatingatlessthan30WforfullLayer1and2operations.AtypicalLayer1and2fulloperationsolutiontodayusesmorethan150Wandrequiresmanyadditionalsemicon-ductordevices,drivinguppowerrequirements.TI’ssolutionisfivetimeslowerthanthetypicalfulloperationsolution,resultinginsignificantpowersavingsandreduceddesigncosts.

Complete tools and supportTIprovidesafullsuiteofbest-in-classEclipse-baseddevelopmentanddebuggingtoolswiththeTCI6616,whichincludesanewCcompiler,anassemblyoptimizertosimplifyprogrammingandscheduling,andaWindowsdebuggerinterfaceforvisibilityintosource-codeexecution.TI’scompilergenerateshighlyef-ficientcodethatis“first-passefficient”sothereislessneedtooptimizeit.TI’sdebuggingtoolshelpdevelopersvisualizeproblemsandresolvethemquickly,helpingdesignersgetproductstothefieldfasterwhilesavingdevelopmentresources.Inaddition,TIwillofferaTCI6616evaluationmodule(EVM)thatwillhelpcustom-erstoquicklyprototypeusingtheTCI6616.

For more informationTolearnmoreabouttheTCI6616SoCvisitwww.ti.com/tci6616.DiscoverhowtheTCI6616canaddperformancetoyournextwirelessbasestationdesign.

Fulloperation

Standby

Deephibernation

Recovery time

100%

-75%

-50%

-30%

0 <25ms >100ms

I/O Active

TCI6616power modes

Lighthibernation

B042210

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Dynamic power modes

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