tms320c6745 manual

1

DIGITAL SIGNAL PROCESSING LAB

Fixed/Floating

Hardware & Software

TMS320C6745 Evaluation Board Manualwww.pantechsolutions.net

DIGITAL SIGNAL PROCESSING LAB

TMS320VC6745

/Floating-Point Digital Signal Processor

Hardware & Software User Manual

TMS320C6745 Evaluation Board Manual

2

CONTENTS:

� Introduction about TMS320C6745

� TMS320C6745 Processor Features

� Functional Block Diagram

� Physical Description

� Kit Peripherals Details

o UART

o SPI

o I2C

� Applications

� Software Description

� Programs


TMS320C6745

TMS320C6745 Processor Features

Functional Block Diagram


3

INTRODUCTION AND OVERVIEW

INTRODUCTION:

The C6745/6747 is a Low-power digital signal processor based on C674x DSP core. It

significantly lower power than other members of the TMS320C6000™ platform of DSPs.

enables OEMs and ODMs to quickly bring to market devices featuring

The C6745/6747 DSP core uses a two

(L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2

cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between

program and data space. L2 also has a 1024KB ROM. L2 memory can be configured as mapped memory,

cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the s

additional 128KB RAM shared memory ( C6747 only) is available for use by other hosts without affecting

DSP performance.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data

Input/output (MDIO) module; two inter

serial port (McASP) with 16/9 serializes

configurable (one configurable as watchdog); a configurable 16

up to 8 banks of 16 pins of general

generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS); 3

enhanced high-resolution pulse width modulator (eHRP

(eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width

modulator (APWM) outputs; 2 32-

memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower

memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the

C6745/6747 and the network. The EMAC supports

and 100 Mbps in either half- or full

(MDIO) interface is available for PHY configuration.


INTRODUCTION AND OVERVIEW

power digital signal processor based on C674x DSP core. It

lower power than other members of the TMS320C6000™ platform of DSPs.

enables OEMs and ODMs to quickly bring to market devices featuring high processing performance.

The C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache

(L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set

cache (L2P) consists of a 256KB memory space that is shared between


cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the s



(MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio

serializes and FIFO buffers; 2 64-bit general-purpose timers each

configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) [C6747

up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event


resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture


-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external

n asynchronous and SDRAM external memory interface (EMIFA) for slower

memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.


he network. The EMAC supports 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps)

or full-duplex mode. Additionally an Management Data

(MDIO) interface is available for PHY configuration.


power digital signal processor based on C674x DSP core. It consumes

lower power than other members of the TMS320C6000™ platform of DSPs. The C6745/6747

performance.

based architecture. The Level 1 program cache

way set-associative

cache (L2P) consists of a 256KB memory space that is shared between


cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an



ntegrated circuit (I2C) Bus interfaces; 3 multichannel audio

purpose timers each

bit host port interface (HPI) [C6747 only];

purpose input/output (GPIO) with programmable interrupt/event


bit enhanced capture


bit enhanced quadrature pulse (eQEP) peripherals; and 2 external

n asynchronous and SDRAM external memory interface (EMIFA) for slower


TX, or 10 Mbits/second (Mbps)

duplex mode. Additionally an Management Data Input/output

4

The rich peripheral set provides the ability to control external peripheral devices and

communicate with external processors. For details on each of the peripherals, see the related sections

later in this document and the associated peripheral reference guides.

ELECTROSTATIC WARNING:

The TMS320-C6745 development board is shipped in protective anti static packaging. The board

must not be subject to high electrostatic potentials. General practice for working with static sensitive

devices should be applied when working with this

BOARD USE REQUIREMENTS:

CABLES : 1.8 meter USB A

HARDWARE : Power supply adapter 4.5

TMS320-JTAG for programming and debugging.

SOFTWARES : Texas Instr

drivers available on the


provides the ability to control external peripheral devices and


later in this document and the associated peripheral reference guides.

development board is shipped in protective anti static packaging. The board


devices should be applied when working with this board.

1.8 meter USB A-B cable to connect with USB host.

Power supply adapter 4.5-5VAC.

JTAG for programming and debugging.

SOFTWARES : Texas Instruments Code Composer Studio V4 and

drivers available on the www.ti.com


provides the ability to control external peripheral devices and


development board is shipped in protective anti static packaging. The board


5

TMS320VC6745 FEATURES:

� Highlights:

• 300 or 200-MHz C674x VLIW DSP

• TMS320C674x Fixed/Floating

• Enhanced Direct

• 128K-Byte RAM Shared Memory (C6747Only)

• Two External Memory

• Three Configurable 16550 type UART Modules

• LCD Controller (C6747 Only)

• Two Serial Peripheral Interfaces (SPI)

• Multimedia Card (MMC)/Secure Digital (SD)

• Two Master/Slave Inter

• One Host-Port Interface (HPI) (C6747 only)

• USB 1.1 OHCI (Host) With Integrated PHY (USB1) (C6747 Only

� Software Support:

• TI DSP/BIOS™

• Chip Support Library and DSP Library

• 300 or 200-MHz C674x VLIW DSP

� C674x Instruction Set Features:

• Superset of the C67x+™ and C64x+™ ISAs

• 2400/1800 C674x MIPS/MFLOPS

• Byte-Addressable (8

• 8-Bit Overflow Protection

• Bit-Field Extract, Set, Clear

• Normalization, Saturation, Bit

• Compact 16-Bit Instructions


:

MHz C674x VLIW DSP

TMS320C674x Fixed/Floating-Point VLIW DSP Core

Enhanced Direct-Memory-Access Controller 3 (EDMA3)

Byte RAM Shared Memory (C6747Only)

Two External Memory Interfaces

Three Configurable 16550 type UART Modules

LCD Controller (C6747 Only)

Two Serial Peripheral Interfaces (SPI)

Multimedia Card (MMC)/Secure Digital (SD)

Two Master/Slave Inter-Integrated Circuit

Port Interface (HPI) (C6747 only)

OHCI (Host) With Integrated PHY (USB1) (C6747 Only)

Chip Support Library and DSP Library

MHz C674x VLIW DSP

C674x Instruction Set Features:

Superset of the C67x+™ and C64x+™ ISAs

2400/1800 C674x MIPS/MFLOPS

Addressable (8-/16-/32-/64-Bit Data)

Bit Overflow Protection

Field Extract, Set, Clear

Normalization, Saturation, Bit-Counting

Bit Instructions


6

� C674x Two Level Cache Memory Architecture:

• 32K-Byte L1P Program RAM/Cache

• 32K-Byte L1D Data RAM/Cache

• 256K-Byte L2 Unified Mapped RAM/Cache

• Flexible RAM/Cache Partition (L1 and L2)

• 1024K-Byte L2 ROM

� Enhanced Direct-Memory

• 2 Transfer Controllers

• 32 Independent DMA Channels

• 8 Quick DMA Channels

• Programmable Transfer

• TMS320C674x Fixed/Floating

• Load-Store Architecture with Non

• 64 General-Purpose Registers (32 Bit)

• Six ALU (32-/40

• Two Multiply Functional Units


C674x Two Level Cache Memory Architecture:

Byte L1P Program RAM/Cache

Data RAM/Cache

Byte L2 Unified Mapped RAM/Cache

Flexible RAM/Cache Partition (L1 and L2)

Byte L2 ROM

Memory-Access Controller 3:

2 Transfer Controllers

32 Independent DMA Channels

8 Quick DMA Channels

Programmable Transfer Burst Size

TMS320C674x Fixed/Floating-Point VLIW DSP Core

Store Architecture with Non-Aligned Support

Purpose Registers (32 Bit)

/40-Bit) Functional Units

Two Multiply Functional Units


7

FUNCTIONAL BLOCK DIAGRAM


FUNCTIONAL BLOCK DIAGRAM:


8

PHYSICAL DESCRIPTIONS

� BOARD LAYOUT

The VC6745 Kit is a 100 x 100 cm six (6) layer printed circuit board which is powered with 5V supply. This

means this board has require an external power supply.


Kit is a 100 x 100 cm six (6) layer printed circuit board which is powered with 5V supply. This

means this board has require an external power supply.


Kit is a 100 x 100 cm six (6) layer printed circuit board which is powered with 5V supply. This

9

� POWER CONNECTOR:

TMS320C6745 Board can take

consumption is around 180 mA with all peripherals and MCU ru

Steps down Voltage Regulator 1.2V (

3.3V.

PIN #

1.

2.

� RESET CIRCUIT:

Reset circuit is made with RC group R5

made provision for Internal reset. Manual reset is

� ON BOARD XDS100 EMULATOR INTRFACE:

The USB connector, J1, is used to attach the

laptop. The signals on the pins of this connector are shown below.

Provides complete debug capabilities and visibility inside the processor for algorithm optimization and

benchmarking.


Board can take power from connector (4.5V to 5V) from U7.

consumption is around 180 mA with all peripherals and MCU running at full speed. TMS320C6745

1.2V (TP7), 3.3V (TP5). The core Voltage is 1.2V and Peripherals Voltage is

SIGNAL NAME

5VDC

GND

Reset circuit is made with RC group R5 – 10K and C1– 0.001UF. Although on the schematic is

made provision for Internal reset. Manual reset is possible by the RST button.

ON BOARD XDS100 EMULATOR INTRFACE:

The USB connector, J1, is used to attach the VC6745 eZDSP stick to a personal computer or

laptop. The signals on the pins of this connector are shown below. On-board XDS100 emulator

complete debug capabilities and visibility inside the processor for algorithm optimization and


7. The board power

nning at full speed. TMS320C6745 has two

V and Peripherals Voltage is

Although on the schematic is

eZDSP stick to a personal computer or

board XDS100 emulator

complete debug capabilities and visibility inside the processor for algorithm optimization and

10

TARGET CONNECTION and CCS v4

1. All XDS100 USB drivers and CCS v

2. Connect the included USB cable to a USB port on the host computer, then connect the

to the XDS100. Windows will recognize the new hardware connection and

installation automatically.

3. Launch Code Composer Studio v

v4 was installed.)

4. The Code Composer Studio v

>Target Configuration File”

5. The “New Target Configuration” window will appear. Enter a file name that describes the

Emulator connection and/or Texas Instruments processor being used and then click

6. The “Basic” configuration setup window will appear. Select “Texas Instruments XDS100

Emulator” from the “Connection” menu and select the target processor being used

“Device” menu. (Refer the demo video

7. Click the “Save” button to save the configuration

8. Apply power to the target processor board.

9. Click the “View” menu and select

10. That have been built or imported. A new tab labeled “Target configurations” will become

11. Available in the CCS window.

12. Expand the “User Defined” folder. Right

13. Created and click “Launch Selected Configuration”.

14. CCS will now attempt to connect to the target processor through the XDS100.

15. Code Composer Studio may now be used to download code and debug code on the

16. Target board.


TARGET CONNECTION and CCS v4 CONFIGURATION INSTRUCTIONS:

All XDS100 USB drivers and CCS v4 drivers are included with the CCS v4 software

Connect the included USB cable to a USB port on the host computer, then connect the

to the XDS100. Windows will recognize the new hardware connection and Complete the XDS100

Launch Code Composer Studio v4 from the shortcut on the desktop. (This was created

The Code Composer Studio v4 window will appear. Click the “File” menu, then select

Target Configuration” window will appear. Enter a file name that describes the

Emulator connection and/or Texas Instruments processor being used and then click

The “Basic” configuration setup window will appear. Select “Texas Instruments XDS100

Emulator” from the “Connection” menu and select the target processor being used

“Device” menu. (Refer the demo video.)

Click the “Save” button to save the configuration

Apply power to the target processor board.

Click the “View” menu and select “Target Configurations” to expose the configuration(s)

That have been built or imported. A new tab labeled “Target configurations” will become

Available in the CCS window.

Expand the “User Defined” folder. Right-click on the configuration that has been

eated and click “Launch Selected Configuration”.

CCS will now attempt to connect to the target processor through the XDS100.

Code Composer Studio may now be used to download code and debug code on the


software Installation.

Connect the included USB cable to a USB port on the host computer, then connect the USB cable

Complete the XDS100

from the shortcut on the desktop. (This was created When CCS

window will appear. Click the “File” menu, then select “New--

Target Configuration” window will appear. Enter a file name that describes the

Emulator connection and/or Texas Instruments processor being used and then click “Finish”.

The “Basic” configuration setup window will appear. Select “Texas Instruments XDS100 USB

Emulator” from the “Connection” menu and select the target processor being used From the

“Target Configurations” to expose the configuration(s)

That have been built or imported. A new tab labeled “Target configurations” will become

click on the configuration that has been

Code Composer Studio may now be used to download code and debug code on the

11

� SYSTEM LED:

The VC6745 eZDSP USB Stick has one green Light Emitting Diode (LED). This LED is software

Controlled via the XF status bit and XF pin on the DSP. External Flag Output. XF is used for signaling other

processors in multiprocessor configurations or XF can be used as a

� DIGITAL INPUTS & OUTPUTS:

A digital input typically consists of a power supply (voltage source), a switch and a voltage

sensing device (analog-to-digital converter). Depending on the switch’s open/closed status, the sensi

device detects a voltage or no voltage condition, which in turn generates a logical 0 or 1, on or off, alarm

or normal or similarly defined state.

outputs.

� TEST POINTS:

The VC6745 e ZDSP USB Stick has sixteen (16) test points for the monitoring of signals.

The location of the test points are shown in the figure below.

The signals on the test points are shown in the table below.

TEST POINTS


eZDSP USB Stick has one green Light Emitting Diode (LED). This LED is software


processors in multiprocessor configurations or XF can be used as a fast general-purpose output pin.

DIGITAL INPUTS & OUTPUTS:

A digital input typically consists of a power supply (voltage source), a switch and a voltage

digital converter). Depending on the switch’s open/closed status, the sensi


or normal or similarly defined state. The jumper J9 & j7 is used to enable & disable the Digital inputs and

ZDSP USB Stick has sixteen (16) test points for the monitoring of signals.

The location of the test points are shown in the figure below.

The signals on the test points are shown in the table below.

TEST POINTS VOLTAGE

TP1 1.2

TP2 3.3

TP3 1.2

TP4 3.3

TP5 3.3


eZDSP USB Stick has one green Light Emitting Diode (LED). This LED is software


purpose output pin.

A digital input typically consists of a power supply (voltage source), a switch and a voltage-

digital converter). Depending on the switch’s open/closed status, the sensing


is used to enable & disable the Digital inputs and

ZDSP USB Stick has sixteen (16) test points for the monitoring of signals.

12

KIT PERIPHERALS

� UART:

The serial communications interface is a two

as UART. On the 28016, the SCI contains a 16

servicing overhead.

The TMS320C6745 processor provides a full

(UART) port, which is fully compatible with PC

interface to other peripherals or hosts, supporting full

UART port includes support for 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd

parity. The UART port supports two modes of operation.

PIO (programmed I/O) – The processor sends or receives d

UART registers. The data is double-buffered on both transmit and receive.

point-to-point data transfer. It is commonly used in data Acquisition applications, for the transfer of data

between the c5505 Processor and a PC.

• The voltage levels of a TMS320C5505 Processor and PC are not directly compatible with

those of RS-232, a level transition buffer such as MAX3222 be used.

• Rs-232(P1) is a female connector. The 2

for transferring the data as shown in fig .


The serial communications interface is a two-wire asynchronous serial port, commonly known

On the 28016, the SCI contains a 16-level receive and transmit FIFO for reducing interrupt

processor provides a full-duplex universal asynchronous receiver/transmitter

(UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART

interface to other peripherals or hosts, supporting full-duplex, asynchronous transfers of serial data. The


parity. The UART port supports two modes of operation.

The processor sends or receives data by writing or reading I/O

buffered on both transmit and receive. Rs-232 communication enables

point data transfer. It is commonly used in data Acquisition applications, for the transfer of data

the c5505 Processor and a PC.

The voltage levels of a TMS320C5505 Processor and PC are not directly compatible with

232, a level transition buffer such as MAX3222 be used.

232(P1) is a female connector. The 2nd

and 3rd

pin of P1 is receiving and transmitting

for transferring the data as shown in fig .


wire asynchronous serial port, commonly known

level receive and transmit FIFO for reducing interrupt

duplex universal asynchronous receiver/transmitter

standard UARTs. The UART port provides a simplified UART

ous transfers of serial data. The


ata by writing or reading I/O-mapped

232 communication enables

point data transfer. It is commonly used in data Acquisition applications, for the transfer of data

The voltage levels of a TMS320C5505 Processor and PC are not directly compatible with

ng and transmitting pin

13

� GENRAL PURPOSE INPUTS &OUTPUTS:

� GPIO MUX:

The GPIO Mux registers are used to select the ope

pins can be individually selected to operate as “Digital I/O” or connected to “Peripheral I/O” signals (via

the GPxMUX registers).If selected for “Digital I/O” mode, registers are provided to configure the pin

direction (via the GPxDIR registers)

GPxQUAL) registers). TMS320C6745

A, PORT B.

� ADC:

The VC5505 includes a 10-bit SAR ADC using a switched capacitor

analog input signal to a digital value at a maximum rate of 62.5

the DSP. This SAR module supports six channels that are connected to four general purpose analog pins

(GPAIN [3:0]) which can be used as general purpose outputs.

� SERIAL PORT INTERFACE (SPI):

The VC5505 serial port interface (SPI) is a high

allows a serial bit stream of programmed length (1 to 32 bits) to be shifted into and out of the device at a

programmed bit-transfer rate. The SPI supports mul

SPI can operate as a master device only, slave mode is not supported. The SPI is normally used for

communication between the DSP and external peripherals. Typical applications include an interface to

external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EEPROMs, and

analog-to-digital converters.

� THE SPI HAS THE FOLLOWING FEATURES:

� Programmable divider for serial data clock generation.

� Four pin interface (SPI_CL

� Programmable data length (1 to 32 bits).

� 4 external chip select signals.

� Programmable transfer or frame size (1 to 4096 characters).


GENRAL PURPOSE INPUTS &OUTPUTS:

The GPIO Mux registers are used to select the operation of shared pins on the c674X



direction (via the GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the

GPxQUAL) registers). TMS320C6745 has 30 general purpose I/O lines. The J4, J11 Connectors like PORT

bit SAR ADC using a switched capacitor architecture which converts an

analog input signal to a digital value at a maximum rate of 62.5-k samples per second (ksps) for use by


can be used as general purpose outputs.

SERIAL PORT INTERFACE (SPI):

The VC5505 serial port interface (SPI) is a high-speed synchronous serial input/output port that


transfer rate. The SPI supports multi-chip operation of up to four SPI slave devices. The



xternal I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EEPROMs, and

THE SPI HAS THE FOLLOWING FEATURES:

Programmable divider for serial data clock generation.

Four pin interface (SPI_CLK, SPI_CSn, SPI_RX, and SPI_TX).

Programmable data length (1 to 32 bits).

4 external chip select signals.

Programmable transfer or frame size (1 to 4096 characters).


ration of shared pins on the c674XX and The



and to qualify the input signal to remove unwanted noise (via the

has 30 general purpose I/O lines. The J4, J11 Connectors like PORT

architecture which converts an

k samples per second (ksps) for use by


speed synchronous serial input/output port that


chip operation of up to four SPI slave devices. The



xternal I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EEPROMs, and

14

� Optional interrupt generation on character completion.

� Programmable SPI_CSn to SPI_TX dela

� Programmable signal polarities.

� Programmable active clock edge.

� Internal loopback mode for testing.

In this board we are using M95512

Interface with positive clock modes. Power supply is 2.5 to 5.5V for M95512

R. These electrically erasable programmable memory (EEPROM) devices are accessed by a high speed

SPI-compatible bus. The memory array is organized as 65536 x 8 bit.

During all operations, VCC must be held stable and within the specified valid range: VCC (min) to VCC

(max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH,

VIL or VOL). These signals are described next.

� Serial Data Output (Q).

Data is shifted out on the falling edge of Serial Clock (C).

signal is used to transfer data serially into the device. It rece

the data to be written. Values are latched on the rising edge of Serial Clock (C).

(C). This input signal provides the timing of the serial interface. Instructions, addresses, or

data present at Serial Data In

on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

� Chip Select (S). When this input signal is High, the device is deselected and Serial Data

Output C (Q) is at high impedance. Unless an internal Write cycle is in progress, the device

will be in the Standby Power mode. Driving Chip Select (S) Low selects the device, placing it

in the Active Power mode. After Power

to the start of any instruction.

� Hold (HOLD). The Hold (HOLD) signal is used to pause any serial communications with the

device without deselecting the device. During the Hold condition, the Serial Data Output (Q)

is high impedance, and Serial Data Inp

Hold condition, the device must be selected, with Chip Select (S) driven Low.


Optional interrupt generation on character completion.

Programmable SPI_CSn to SPI_TX delay from 0 to 3 SPI_CLK cycles.

Programmable signal polarities.

Programmable active clock edge.

Internal loopback mode for testing.

95512 512kbit serial spi bus eeprom.It is Compatible with SPI Bus Serial

clock modes. Power supply is 2.5 to 5.5V for M95512-W, 1.8 to 5.5V for M95512


compatible bus. The memory array is organized as 65536 x 8 bit.

perations, VCC must be held stable and within the specified valid range: VCC (min) to VCC

All of the input and output signals must be held High or Low (according to voltages of VIH, VOH,

VIL or VOL). These signals are described next.

Serial Data Output (Q). This output signal is used to transfer data serially out of the device.

Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D).

signal is used to transfer data serially into the device. It receives instructions, addresses, and

the data to be written. Values are latched on the rising edge of Serial Clock (C).

This input signal provides the timing of the serial interface. Instructions, addresses, or

data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data

on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

When this input signal is High, the device is deselected and Serial Data

h impedance. Unless an internal Write cycle is in progress, the device


in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required pri

to the start of any instruction.

The Hold (HOLD) signal is used to pause any serial communications with the


is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the



y from 0 to 3 SPI_CLK cycles.

512kbit serial spi bus eeprom.It is Compatible with SPI Bus Serial

W, 1.8 to 5.5V for M95512-


perations, VCC must be held stable and within the specified valid range: VCC (min) to VCC

All of the input and output signals must be held High or Low (according to voltages of VIH, VOH,

This output signal is used to transfer data serially out of the device.

Serial Data Input (D). This input

ives instructions, addresses, and

the data to be written. Values are latched on the rising edge of Serial Clock (C). Serial Clock

This input signal provides the timing of the serial interface. Instructions, addresses, or

put (D) are latched on the rising edge of Serial Clock (C). Data

When this input signal is High, the device is deselected and Serial Data

h impedance. Unless an internal Write cycle is in progress, the device


up, a falling edge on Chip Select (S) is required prior

The Hold (HOLD) signal is used to pause any serial communications with the


ut (D) and Serial Clock (C) are Don’t Care. To start the


15

� Write Protect (W). The main purpose of this input signal is to freeze the size of the area of

memory that is protected

and BP0 bits of the Status Register).This pin must be driven either High or Low, and must be

stable during all write instructions.

� I2CSPI EEPROM:

The inter-integrated circuit (I2C) m

devices compliant with Philips Semiconductors Inter

components attached to this 2-wire serial bus can transmit/receive 2 to 8

through the I2C module. The I2C port

� The I2C port supports the following features:

o Compatible with Philips I2C Specification Revision 2.1 (January 2000)

o Data Transfer Rate from 10 kbps to 400 kbps (Philips

o Noise Filter to Remove Noise 50 ns or Less

o Seven-

o Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality

o One Read DMA Event and One Write DMA Event, which can be used by the

DMA Controller

o One Interrupt that can be used by the CPU

o Slew-Rate Limited Open


The main purpose of this input signal is to freeze the size of the area of

memory that is protected against Write instructions (as specified by the values in the BP1


stable during all write instructions.

integrated circuit (I2C) module provides an interface between VC5505 and other

devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External

wire serial bus can transmit/receive 2 to 8-bit data to/from the DS

through the I2C module. The I2C port does not support CBUS compatible devices.

The I2C port supports the following features:

Compatible with Philips I2C Specification Revision 2.1 (January 2000)

Data Transfer Rate from 10 kbps to 400 kbps (Philips Fast-Mode Rate)

Noise Filter to Remove Noise 50 ns or Less

and Ten-Bit Device Addressing Modes

Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality

One Read DMA Event and One Write DMA Event, which can be used by the

DMA Controller

ne Interrupt that can be used by the CPU

Rate Limited Open-Drain Output Buffers


The main purpose of this input signal is to freeze the size of the area of

against Write instructions (as specified by the values in the BP1


odule provides an interface between VC5505 and other

bus™) specification version 2.1. External

bit data to/from the DSP

Compatible with Philips I2C Specification Revision 2.1 (January 2000)

Mode Rate)

Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality

One Read DMA Event and One Write DMA Event, which can be used by the

16

The I2C module clock must be in the range from 6.7 MHz to 13.3 MHz This is necessary for

proper. Operation of the I2C module. With the I2C module clock in this range, the

SDA and SCL pins suppress noise that has a duration of 50 ns or shorter. The I2C module clock is derived

from the DSP clock divided by a programmable prescaler.

APPLICATIONS:

� Industrial Control

� USB, Networking

� High-Speed Encoding

� Professional Audio



proper. Operation of the I2C module. With the I2C module clock in this range, the noise filters on the


from the DSP clock divided by a programmable prescaler.



noise filters on the


17

SOFTWARE DESCRIPTION:

CCS v4 is a major new release of Code Composer Studio that is based on the Eclipse open source

software framework. The Eclipse software framework was originally developed as a development tool

primarily for Java application development and an open framework for creating development tools. It is

becoming very popular in the embedded development community and is now being used or adopted by

many different vendors. Code Composer streamlines the design proce

combined with leading C code density and powerful debugging capabilities. Major upgrades include

optimizations and improvements focused on improving design flow, simplifying debugging and

verification and speeding time-to-market while keeping system costs low.

Key New Features

New functionality Code Composer Studio includes:

• Emulation Drivers—included

those emulators that are sold through the TI eStore wil

things easier for initial installation. The drivers for DSKs are also present.

• Migrating Existing Projects

previous versions. Therefore there are so

move your development from previous versions to v4. There are some tools to help you, such as

the project import wizard. The overall environment is much different so you will need to

patiently adjust to it.

o CCS v3.3 Projects—CCSv4 uses the Eclipse concept of projects. To help you import your existing

projects into CCSv4 we have created a project import wizard. Use the Project >

CCSv3.3 Project menu command. This starts a wizard that guides you through the conversion

process. If you don't want to convert your projects at this time, you may want to create a

standard make project that calls

o CCE v3 Projects—CCSv4 and CCEv3.x projects are very similar. Please use Project

Existing CC/CCE Eclipse projects menu.




for Java application development and an open framework for creating development tools. It is


many different vendors. Code Composer streamlines the design process with a more intuitive interface



market while keeping system costs low.

New functionality Code Composer Studio includes:

included some third-party emulation drivers in the installation. Essentially

those emulators that are sold through the TI eStore will have their drivers on the CD to make

things easier for initial installation. The drivers for DSKs are also present.

Migrating Existing Projects—CCSv4 is a major release and as a result it is quite different from

previous versions. Therefore there are some migration steps that you need to go through to



CCSv4 uses the Eclipse concept of projects. To help you import your existing

projects into CCSv4 we have created a project import wizard. Use the Project >



standard make project that calls timake to build your existing project file.

CCSv4 and CCEv3.x projects are very similar. Please use Project

Existing CC/CCE Eclipse projects menu.




for Java application development and an open framework for creating development tools. It is


ss with a more intuitive interface



party emulation drivers in the installation. Essentially

l have their drivers on the CD to make

CCSv4 is a major release and as a result it is quite different from

me migration steps that you need to go through to



CCSv4 uses the Eclipse concept of projects. To help you import your existing

projects into CCSv4 we have created a project import wizard. Use the Project > Import Legacy



CCSv4 and CCEv3.x projects are very similar. Please use Project -> Import

18

• Target Configuration and Setup Editor

Target-> New Target Configuration menu. If you have a project selected in C/C++ project view,

then target configuration wizard will use that project as the location where to create this file.

User may adjust it. Alternatively, target configuration file

target configuration file is added to the project, then it will be automatically used by the

debugger when the Debug Active Project

target configuration files usi

connection and board/device). Setup Editor may also be used to configure target settings from

scratch using Advanced tab in Setup Editor. One of these configurations can be designated as

your Default Target Configuration

• Real-time Analysis—transfers DSP/BIOS (and user

processor's kernel task execution and resource usage. Once the logs are tra

target to the host, you can display graphs of Task Interaction over time, CPU Usage, CPU Load on

a Task basis, and the System Execution States. A control panel helps you select which logs you

want to collect, transfer, and display.

• Profiling and Code Coverage

profiling. User can sort functions by name or percentage of time usage in the display viewer.

Profiling data from multiple runs can be displayed. Displays produced include Fun

Profile, Application Level Profiling, and Code Coverage analysis tables.

• Memory View changes—enable viewing different levels of memory. That is, inspect the contents

of the L1P cache, L1D, L2, and so forth. On devices that support MMU (Memory M

Units, such as OMAP35xx) users need to display and edit virtual memory data. For devices that

support multiple memory pages, users need to edit and display memory on different pages.

Memory view permits the user to configure the data format, prec

type appropriate for your application.

• GEL (General Extension Language)

used by the CCS debugger. Each location where you enter in a start address, variable name, or

condition on a breakpoint it is using GEL to evaluation that expression.

has changed to be part of the CCS debugger and not the top level user interface, you can not run

some of the old GEL functions that accessed the user interface

project related functions. However debug related functions still work. Hotmenu items defined in


Target Configuration and Setup Editor—New target configuration files may be created f

> New Target Configuration menu. If you have a project selected in C/C++ project view,


User may adjust it. Alternatively, target configuration files are created in default location. If


Debug Active Project action is selected. Setup Editor allows users to create

target configuration files using basic tab where simplified selection are available (i.e. select



Default Target Configuration using Target Configuration View (View->Target Configuration)

transfers DSP/BIOS (and user-defined) logs to provide a pattern of a

processor's kernel task execution and resource usage. Once the logs are tra



want to collect, transfer, and display.

ing and Code Coverage—perform function-level and source line (within a function)


Profiling data from multiple runs can be displayed. Displays produced include Fun

Profile, Application Level Profiling, and Code Coverage analysis tables.

enable viewing different levels of memory. That is, inspect the contents

of the L1P cache, L1D, L2, and so forth. On devices that support MMU (Memory M



Memory view permits the user to configure the data format, precision, endianness, and data

type appropriate for your application.

GEL (General Extension Language)—GEL is still present in CCSv4. GEL is the expression evaluator


condition on a breakpoint it is using GEL to evaluation that expression. (Changes)


some of the old GEL functions that accessed the user interface such as GEL_WatchAdd() or the



New target configuration files may be created from

> New Target Configuration menu. If you have a project selected in C/C++ project view,


s are created in default location. If


action is selected. Setup Editor allows users to create

ng basic tab where simplified selection are available (i.e. select



>Target Configuration)

defined) logs to provide a pattern of a

processor's kernel task execution and resource usage. Once the logs are transferred from the



level and source line (within a function)


Profiling data from multiple runs can be displayed. Displays produced include Function Level

enable viewing different levels of memory. That is, inspect the contents

of the L1P cache, L1D, L2, and so forth. On devices that support MMU (Memory Management



ision, endianness, and data

GEL is still present in CCSv4. GEL is the expression evaluator


(Changes) In CCSv4 GEL


such as GEL_WatchAdd() or the


19

GEL scripts are visible under "Scripts" menu, they are visible after debugger is started and are

sensitive to processor selected

menu's user would need to select ARM processor in Debug View.

• Increased ease-of-use—streamlined options dialog boxes reduce the number of steps required

for commonly performed design tasks.

• High-performance debugger

200 percent faster performance for tasks such as downloading applications, single

refreshing registers and variables.

• Updated C-code syntax—helps develope

the rich diversity of code examples, libraries and demos from TI and TI third parties.

• Language flexible—programming languages supported include assembly, C, and C++.

Creating a new CCS Project

This procedure helps you to create single or multiple new CCS Projects (multiple projects

be open simultaneously). Each project in the workspace must have a unique name.

1. Start Code Composer Studio from the

2. Select File > New > CCS Project

3. When the New CCS Project

the Use default location check box and set the project storage location. By default, the project will

be created inside the workspace directory. Click



sensitive to processor selected in Debug View. i.e. in multi-processor scenario to see ARM GEL

menu's user would need to select ARM processor in Debug View.

streamlined options dialog boxes reduce the number of steps required

for commonly performed design tasks.

performance debugger—replaces the GDB debugger with the TI Debug Server yields up to

200 percent faster performance for tasks such as downloading applications, single

refreshing registers and variables.

helps developers to directly import code without modification, from


programming languages supported include assembly, C, and C++.

Creating a new CCS Project:

This procedure helps you to create single or multiple new CCS Projects (multiple projects

be open simultaneously). Each project in the workspace must have a unique name.

Start Code Composer Studio from the desktop shortcut.

File > New > CCS Project action from the Workbench main menu.

New CCS Project wizard displays, type the Project name. You can optionally de

check box and set the project storage location. By default, the project will

be created inside the workspace directory. Click Next.



processor scenario to see ARM GEL

streamlined options dialog boxes reduce the number of steps required

replaces the GDB debugger with the TI Debug Server yields up to

200 percent faster performance for tasks such as downloading applications, single-stepping, and

rs to directly import code without modification, from


programming languages supported include assembly, C, and C++.

This procedure helps you to create single or multiple new CCS Projects (multiple projects can

. You can optionally de-select

check box and set the project storage location. By default, the project will

20

4. Select the desired platform (


sired platform (Project Type) and Configuration. Click Next.


21

5. Optionally, define any inter-project dependencies and select type of project indexing (

None). Click Next.

6. Select your project settings, including selecting the

down selection list or click More... to search through available devices using a filter. Click


project dependencies and select type of project indexing (

Select your project settings, including selecting the Device Variant for your project. Use the drop

to search through available devices using a filter. Click


project dependencies and select type of project indexing (Full, Fast, or

for your project. Use the drop-

to search through available devices using a filter. Click Finish.

22

TMS320C6745 Evaluation Board Manualwww.pantechsolutions.net TMS320C6745 Evaluation Board Manual

23

The new project displays in the C/C++ Projects vie

After creating the project, create your source files, set object libraries using the project Properties dialog,

and add or link other files into the project.


The new project displays in the C/C++ Projects view and is set as the currently active project.


and add or link other files into the project.


w and is set as the currently active project.


24

7. To build your project, click the Build Activ

8. To launch a debug-session and download your application onto the target device, click the

button on the main Workbench toolbar (

Building Your Project

Now that you have created a functional

1. Select the Project > Build All

2. The project should build successfully. The Console View displays the standard and error outputs

of the code-generation tools. When the build

or warnings.

3. After the project builds successfully, you can launch a debug

the target. If you need to load the program manually, select

Composer creates a subdirectory for the currently active build

within your project directory and stores the

Alternatively, you can launch a debug

Composer will automatically perform an incremental build of your project before starting the debug

session. Debug Active Project is a single action that builds a project and launches the debugger using

target configuration information contained in the project

4. You will automatically be taken to the Debug perspective. To manually switch to the Debug

perspective, select the Debug icon in the far right of the Code Composer window, or by selecting

Window > Open Perspective > Debug

Note: Remember to reload the pro

after making changes.


Build Active Project button on the main Workbench toolbar (

session and download your application onto the target device, click the

button on the main Workbench toolbar ( )

Now that you have created a functional project, you can build it.

Build All menu action to build all the projects in your workspace.

The project should build successfully. The Console View displays the standard and error outputs

generation tools. When the build is finished, the Problems View displays any errors

After the project builds successfully, you can launch a debug-session and load the program onto

the target. If you need to load the program manually, select Target > Load Program

r creates a subdirectory for the currently active build-configuration (Debug or Release)

within your project directory and stores the .out file in it.

Alternatively, you can launch a debug-session using the Debug Active Project toolbar button, and Code

poser will automatically perform an incremental build of your project before starting the debug

is a single action that builds a project and launches the debugger using

target configuration information contained in the project.

You will automatically be taken to the Debug perspective. To manually switch to the Debug


Debug.

: Remember to reload the program by choosing Target > Load Program if you rebuild the project


button on the main Workbench toolbar ( ).

session and download your application onto the target device, click the Debug

menu action to build all the projects in your workspace.

The project should build successfully. The Console View displays the standard and error outputs

is finished, the Problems View displays any errors

session and load the program onto

Load Program. Code

configuration (Debug or Release)

toolbar button, and Code

poser will automatically perform an incremental build of your project before starting the debug-

is a single action that builds a project and launches the debugger using

You will automatically be taken to the Debug perspective. To manually switch to the Debug


if you rebuild the project

25

There are several options available for building projects:

• Full Builds — re-build and re

to re-build the currently active project, or

projects in the workspace.

• Incremental Builds — build and re

Select Project > Build Active Project

All ( ) to build all the open projects in the workspace.

• Build automatically — performs an incremental build automatically whenever any source

relevant header-files are saved.

Procedure for ADD Existing Project:

• Open CCS Software

• Go to Project menu�Add existing project

Which contains the all the programs

• Then go to view menu�click

• Set any one of the project as an active project

• Then set target configuration

• Debug the program

• Run the coding

• See the output


There are several options available for building projects:

build and re-link all the source-files. Select Project > Rebuild Active Project

build the currently active project, or Project > Rebuild All ( ) to re-

build and re-link only the source-files that were modified since last build.

Project > Build Active Project ( ) to build the currently active project, or

) to build all the open projects in the workspace.

performs an incremental build automatically whenever any source

files are saved.

for ADD Existing Project:

Add existing project�Browse folder,�select the folder

Which contains the all the programs

click view CCS projects

Set any one of the project as an active project

Then set target configuration


Project > Rebuild Active Project ( )

-build all the open

files that were modified since last build.

to build the currently active project, or Project > Build

performs an incremental build automatically whenever any source-files or

select the folder

26

1. Linear Convolution of the two given sequences

THEORY:

Convolution is a formal mathematical operation, just as multiplication, addition, and integration.

Addition takes two numbers and produces a third

produces a third signal. Convolution is used in the

statistics. In linear systems, convolution is used to describe the relationship between three signals of

interest: the input signal, the impulse response, and the output signal.

In this equation, x1(k), x2(n-k) and y(n) represent the input to and output from the system at time n.

Here we could see that one of the inputs is shifted in time by a value every time it is multiplied with the

other input signal. Linear Convolution is quite often used as a meth

types.


1. Linear Convolution of the two given sequences


and produces a third number, while convolution takes two

l. Convolution is used in the mathematics of many fields, such as probability and


interest: the input signal, the impulse response, and the output signal.

k) and y(n) represent the input to and output from the system at time n.


other input signal. Linear Convolution is quite often used as a method of implementing filters of various



r, while convolution takes two signals and

mathematics of many fields, such as probability and


k) and y(n) represent the input to and output from the system at time n.


od of implementing filters of various

27

Program:

#include<stdio.h> main () {

int m=4; /*Lenght of i/p samples sequence*/int n=4; /*Lenght of impulse response Coint i=0,j; int x[10]={1,2,3,4,0,0,0,0}; /*Input Signal int h[10]={1,2,3,4,0,0,0,0}; /*Impulse Response Co/*At the end of input sequences pad 'M' and 'N' no. of zero's*/int *y; y=(int *)0x0000100;for(i=0;i<m+n- 1;i++)

{ y[i]=0; for(j=0;j<=i;j++)y[i]+=x[j]*h[i

} for(i=0;i<m+nprintf("%d

}

Output:

1, 4, 10, 20, 25, 24, 16.


int m=4; /*Lenght of i/p samples sequence*/ int n=4; /*Lenght of impulse response Co - efficients */

int x[10]={1,2,3,4,0,0,0,0}; /*Input Signal Samples*/ int h[10]={1,2,3,4,0,0,0,0}; /*Impulse Response Co - efficients*//*At the end of input sequences pad 'M' and 'N' no. of zero's*/

y=(int *)0x0000100; 1;i++)

for(j=0;j<=i;j++) y[i]+=x[j]*h[i -j];

for(i=0;i<m+n -1;i++) printf("%d \n",y[i]);


efficients */

efficients*/

/*At the end of input sequences pad 'M' and 'N' no. of zero's*/

28

Hardware Output


29

MATLAB program for linear convolution

%linear convolution program

clc;

clear all;

close all;

disp('linear convolution program');

x=input('enter i/p x(n):');

m=length(x);

h=input('enter i/p h(n):');

n=length(h);

x=[x,zeros(1,n)];

subplot(2,2,1), stem(x);

title('i/p sequence x(n)is:');

xlabel('---->n');

ylabel('---- >x(n)');grid;

h=[h,zeros(1,m)];

subplot(2,2,2), stem(h);

title('i/p sequence h(n)is:');

xlabel('---->n');

ylabel('---- >h(n)');grid;

disp('convolution of x(n) & h(n) is y(n):');

y=zeros(1,m+n-1);

for i=1:m+n-1

y(i)=0;

for j=1:m+n-1

if(j<i+1)

y(i)=y(i)+x(j)*h(i- j+1);

end

end

end

y

subplot(2,2,[3,4]),stem(y);

title('convolution of x(n) & h(n) is

xlabel('---->n');

ylabel('---- >y(n)');grid;


MATLAB program for linear convolution:

%linear convolution program

disp('linear convolution program');

x(n):');

h=input('enter i/p h(n):');

subplot(2,2,1), stem(x);

title('i/p sequence x(n)is:');

>x(n)');grid;

subplot(2,2,2), stem(h);

title('i/p sequence h(n)is:');

>h(n)');grid;

disp('convolution of x(n) & h(n) is y(n):');

j+1);

subplot(2,2,[3,4]),stem(y);

title('convolution of x(n) & h(n) is :');

>y(n)');grid;


30

Matlab Output


31

2. Circular convolution of two sequences

THEORY

Circular convolution is another way of finding the convolution sum of two input signals. It

resembles the linear convolution, except that the sample values of one of the input signals is folded and

right shifted before the convolution sum is found. Also note that circular convolution could also be found

by taking the DFT of the two input signals and finding the product of the t

The Inverse DFT of the product would give the output of the signal in the time domain which is the

circular convolution output. The two input signals could have been of varying sample lengths. But we

take the DFT of higher point, which ever signals levels to.

For eg. If one of the signals is of length 256 and the other spans 51 samples, then we could only

take 256 point DFT. So the output of IDFT would be containing 256 samples instead of 306 samples,

which follows N1+N2 – 1 where N1 & N2 are the lengths 256 and 51 respectively of the two inputs. Thus

the output which should have been 306 samples long is fitted into 256 samples. The 256 points end up

being a distorted version of the correct signal. This process is called circul

Program:

#include<stdio.h> int m,n,x[30],h[30],y[30],i,j,temp[30],k,x2[30],a[3 0];void main()

{ int * y; y=(int *)0x0000100;printf(" enter the length of the first sequencescanf("%d",&m);printf(" enter the length of the second scanf("%d",&n);printf(" enter the first sequencefor(i=0;i<m;i++)scanf("%d",&x[i]);printf(" enter the second sequencefor(j=0;j<n;j++)scanf("%d",&h[j]);


2. Circular convolution of two sequences


except that the sample values of one of the input signals is folded and


by taking the DFT of the two input signals and finding the product of the two frequency domain signals.



t, which ever signals levels to.



here N1 & N2 are the lengths 256 and 51 respectively of the two inputs. Thus


being a distorted version of the correct signal. This process is called circular convolution.

int m,n,x[30],h[30],y[30],i,j,temp[30],k,x2[30],a[3 0];

y=(int *)0x0000100; printf(" enter the length of the first sequence \scanf("%d",&m); printf(" enter the length of the second sequencescanf("%d",&n); printf(" enter the first sequence \n"); for(i=0;i<m;i++) scanf("%d",&x[i]); printf(" enter the second sequence \n"); for(j=0;j<n;j++) scanf("%d",&h[j]);



except that the sample values of one of the input signals is folded and


wo frequency domain signals.





here N1 & N2 are the lengths 256 and 51 respectively of the two inputs. Thus


ar convolution.

\ n");

sequence \n");

32

if(m- n!=0) /*If length of both sequences are not equal*/{ if(m>n) /* Pad {

for(i=n;i<m;i++)h[i]=0;n=m;

} for(i=m;i<n;i++)x[i]=0;m=n;

} y[0]=0;a[0]=h[0];for(j=1;j<n;j++) /*folding h(n) to h(a[j]=h[n/*Circular convolution*/for(i=0;i<n;i++)y[0]+=x[i]*a[i];for(k=1;k<n;k++)

{ y[k]=0;/*circular shift*/for(j=1;j<n;j++)x2[j]=a[jx2[0]=a[nfor(i=0;i<n;i++)

{ a[i]=x2[i];y[k]+=x[i]*x2[i];

} } /*displaying the result*/

printf(" the circular convolution isfor(i=0;i<n;i++)printf("%d ",y[i]);

}


n!=0) /*If length of both sequences are not equal*/

if(m>n) /* Pad the smaller sequence with zero*/

for(i=n;i<m;i++) h[i]=0; n=m;

for(i=m;i<n;i++) x[i]=0; m=n;

y[0]=0; a[0]=h[0]; for(j=1;j<n;j++) /*folding h(n) to h(a[j]=h[n -j]; /*Circular convolution*/ for(i=0;i<n;i++) y[0]+=x[i]*a[i]; for(k=1;k<n;k++)

y[k]=0; /*circular shift*/ for(j=1;j<n;j++) x2[j]=a[j -1]; x2[0]=a[n -1]; for(i=0;i<n;i++)

a[i]=x2[i]; y[k]+=x[i]*x2[i];

/*displaying the result*/ printf(" the circular convolution is \for(i=0;i<n;i++) printf("%d ",y[i]);


n!=0) /*If length of both sequences are not equal*/

the smaller sequence with zero*/

for(j=1;j<n;j++) /*folding h(n) to h( -n)*/

\ n");

33

Output:

enter the length of the first sequence

4

enter the length of the second sequence

4

enter the first sequence

4 3 2 1

enter the second sequence

1 1 1 1

the circular convolution is

10 10 10 10


length of the first sequence

enter the length of the second sequence


34

MATLAB program for circular convolution program

clc; clear all; close all; disp('circular convolution program');x=input('enter i/p x(n):');m=length(x); h=input('enter i/p sequence h(n)');n=length(h); subplot(2,2,1), stem(x);title('i/p sequencce x(n)is:');xlabel('---->n'); ylabel('---- >x(n)');grid;subplot(2,2,2), stem(h);title('i/p sequencce h(n)is:');xlabel('---->n'); ylabel('---- >h(n)');grid;disp('circular convolution of x(n) & h(n) is y(n):' );if(m-n~=0) if(m>n) h=[h,zeros(1,m-n)]; n=m; end x=[x,zeros(1,n-m)]; m=n; end y=zeros(1,n); y(1)=0; a(1)=h(1); for j=2:n a(j)=h(n-j+2); end %ciruclar conv for i=1:n y(1)=y(1)+x(i)*a(i); end for k=2:n y(k)=0; % circular shift for j=2:n x2(j)=a(j-1); end


MATLAB program for circular convolution program

disp('circular convolution program'); x=input('enter i/p x(n):');

h=input('enter i/p sequence h(n)');

subplot(2,2,1), stem(x); title('i/p sequencce x(n)is:');

>x(n)');grid; stem(h);

title('i/p sequencce h(n)is:');

>h(n)');grid; disp('circular convolution of x(n) & h(n) is y(n):' );


35

x2(1)=a(n); for i=1:n if(i<n+1) a(i)=x2(i); y(k)=y(k)+x(i)*a(i); end end end y subplot(2,2,[3,4]),stem(y);title('convolution of x(n) & h(n) is:');xlabel('---->n'); ylabel('---- >y(n)');grid;

Output:


subplot(2,2,[3,4]),stem(y); title('convolution of x(n) & h(n) is:');

>y(n)');grid;


36

3. N-point DFT of a given sequence

THEORY

Discrete Fourier Transform:

which allows us to evaluate the Fourier Transform X(ejω) on a digital

digital hardware. Since X(ejω) is continuous and

the Fourier Transform at a finite Number

content of a signal, DFT is used to perform linear filtering operations in the frequency domain.

sequence of N complex numbers x0,...,

Complex numbers X0... XN−1 by the DFT according to the formula:

Program :

#include <stdio.h> #include <math.h> #define N 4 //number of data valuesfloat pi = 3.1416; short x[N] = {1,1,0,0}; //1float out[2] = {0,0}; //initialize Re and Im result svoid dft(short *x, short k, float *out) //DFT function

{ float sumRe = 0; //initialize real componentfloat sumIm = 0; //initialize imaginary componentint i = 0; float cs = 0; //initialize cosine componentfloat sn = 0; //initialize sine componentfor (i = 0; i < N; i++) //for N

{ cs =cos(2*pi*(k)*i/N); //real componentsn = sin(2*pi*(k)*i/N); //imaginary componentsumRe = sumRe + x[i]*cs; //sum of real componentssumIm = sumIm - x[i]*sn; //sum of imaginary components


given sequence

Discrete Fourier Transform: The Discrete Fourier Transform is a powerful

which allows us to evaluate the Fourier Transform X(ejω) on a digital Computer or specially designed

digital hardware. Since X(ejω) is continuous and periodic, the DFT is obtained by sampling one period of

Number of frequency points. Apart from determining the frequency

DFT is used to perform linear filtering operations in the frequency domain.

0,..., xN−1 is transformed into the sequence of N

1 by the DFT according to the formula:

#define N 4 //number of data values

short x[N] = {1,1,0,0}; //1 -cycle cosine float out[2] = {0,0}; //initialize Re and Im result s

dft(short *x, short k, float *out) //DFT function

float sumRe = 0; //initialize real component float sumIm = 0; //initialize imaginary component

float cs = 0; //initialize cosine component float sn = 0; //initialize sine component

i < N; i++) //for N -point DFT

cs =cos(2*pi*(k)*i/N); //real component sn = sin(2*pi*(k)*i/N); //imaginary component sumRe = sumRe + x[i]*cs; //sum of real components

x[i]*sn; //sum of imaginary components


Computation tool

or specially designed

, the DFT is obtained by sampling one period of

points. Apart from determining the frequency

DFT is used to perform linear filtering operations in the frequency domain. The

x[i]*sn; //sum of imaginary components

37

} out[0] = sumRe; //sum of real out[1] = sumIm; //sum of imaginary componentsprintf("%f %f\ n",out[0],out[1]);

} void main() { int j; for (j = 0; j < N; j++)dft(x, j, out); //call DFT function

}

Output:

2.000000 0.000000

0.999996 -1.000000

0.000000 0.000007

1.000011 1.000000


out[0] = sumRe; //sum of real components out[1] = sumIm; //sum of imaginary components

n",out[0],out[1]);

for (j = 0; j < N; j++) dft(x, j, out); //call DFT function


38

PROGRAM:

%MATLAB Program to find Fast Fourier Transform

clc;

clear all;

close all;

tic;

x=input('enter the sequence');

n=input('enter the length of fft');

%compute fft

disp('Fourier transformed signal');

X=fft(x,n)

subplot(1,2,1);stem(x);

title('i/p signal');

xlabel('n --->');

ylabel('x(n) -- >');grid;

subplot(1,2,2);stem(X);

title('fft of i/p x(n) is:');

xlabel('Real axis --- >');

ylabel('Imaginary axis --

grid;


%MATLAB Program to find Fast Fourier Transform

x=input('enter the sequence');

n=input('enter the length of fft');

transformed signal');

>');grid;

title('fft of i/p x(n) is:');

>');

-- >');


39

Matlab Output


40

4. To verify FIR filters.

THEORY:

A Finite Impulse Response (FIR) filter is a discrete linear time

based on the weighted summation of a finite number of past inputs. An FIR transversal filter structure

can be obtained directly from the equation for discrete

In this equation, x(k) and y(n) represent the input to and output from the filter at time n. h(n

the transversal filter coefficients at time n. These coefficients are generated by using FDS (Filter Design

Software or Digital filter design package).

FIR – filter is a finite impulse response filter. Order of the filter should be specified. Infinite

response is truncated to get finite impulse response. Placing a window of finite length does this. Types of

windows available are Rectangular, Barlett, Hamming, Hanning, Black mann windowetc. This FIR filter is

an all zero filter.

Program

#include<stdio.h> #include<math.h> #define pi 3.1415 int n,N,c; float wr[64],wt[64]; void main() {

printf("\ n enter no. of samples,N= :");scanf("%d",&N); printf("\ n enter choice of window function\n c= :"); scanf("%d",&c); printf("\ n elements of window function are:");switch(c)

{


Finite Impulse Response (FIR) filter is a discrete linear time-invariant system whose output is


can be obtained directly from the equation for discrete-time convolution.

In this equation, x(k) and y(n) represent the input to and output from the filter at time n. h(n


er design package).

filter is a finite impulse response filter. Order of the filter should be specified. Infinite


ngular, Barlett, Hamming, Hanning, Black mann windowetc. This FIR filter is

n enter no. of samples,N= :");

n enter choice of window function \ n 1.rect

n elements of window function are:");


invariant system whose output is


In this equation, x(k) and y(n) represent the input to and output from the filter at time n. h(n-k) is


filter is a finite impulse response filter. Order of the filter should be specified. Infinite


ngular, Barlett, Hamming, Hanning, Black mann windowetc. This FIR filter is

n 1.rect \n 2. triang

41

case 1: for(n=0;n<=N- 1;n++)

{ wr[n]=1; printf(" \ n wr[%d]=%f",n,wr[n]);

} break; case 2: for(n=0;n<=N- 1;n++)

{ wt[n]=1- (2*(float)n/(Nprintf("\ n wt[%d]=%f",n,wt[n]);

} break;

} }

Hardware Output


1;n++)

n wr[%d]=%f",n,wr[n]);

1;n++)

(2*(float)n/(N -1)); n wt[%d]=%f",n,wt[n]);


42


43


44

Matlab PROGRAM:

% MATLAB program for FIR filter design using window techniques

clc;

clear all;

close all;

rp=input('enter passband ripple');

rs=input('enter the stopband ripple');

fp=input('enter passband freq');

fs=input('enter stopband freq');

f=input('enter sampling freq ');

wp=2*fp/f;

ws=2*fs/f;

num=-20*log10(sqrt(rp*rs))

dem=14.6*(fs-fp)/f;

n=ceil(num/dem);

n1=n+1;

if(rem(n,2)~=0)

n1=n;

n=n-1;

end

c=input('enter your choice of window function 1. re ctangular 2.

triangular 3.kaiser: \ n ');

if(c==1)

y=rectwin(n1);

disp('Rectangular window filter response');

end

if (c==2)

y=triang(n1);

disp('Triangular window filter response');

end

if(c==3)

y=kaiser(n1);

disp('kaiser window filter response');

end

%LPF



rp=input('enter passband ripple');


fp=input('enter passband freq');

fs=input('enter stopband freq');

f=input('enter sampling freq ');

20*log10(sqrt(rp*rs)) -13;


n ');

disp('Rectangular window filter response');

window filter response');

disp('kaiser window filter response');




45

b=fir1(n,wp,y);

[h,o]=freqz(b,1,256);

m=20*log10(abs(h));

subplot(2,2,1);plot(o/pi,m);

title('LPF');

ylabel('Gain in dB-- >');

xlabel('(a) Normalized freq

%HPF

b=fir1(n,wp,'high',y);

[h,o]=freqz(b,1,256);

m=20*log10(abs(h));


title('HPF');


xlabel('(b) Normalized frequency

%BPF

wn=[wp ws];

b=fir1(n,wn,y);

[h,o]=freqz(b,1,256);

m=20*log10(abs(h));


title('BPF');


xlabel('(c) Normalized frequency

%BSF

b=fir1(n,wn,'stop',y);

[h,o]=freqz(b,1,256);

m=20*log10(abs(h));


title('BSF');


xlabel('(d) Normalized frequency



>');

xlabel('(a) Normalized freq uency-->');


>');

xlabel('(b) Normalized frequency -->');


>');

xlabel('(c) Normalized frequency -->');


>');

xlabel('(d) Normalized frequency -->');


46



47

5. To verify IIR filters.

THEORY:

The IIR filter can realize both the poles and zeroes of a system because it has a rational transfer

function, described by polynomials in z in both the numerator

The difference equation for such a system is described by the following:

M and N are order of the two polynomials. bk and ak are the filter coefficients. This filter

Coefficients are generated using FDS (Filter Design software or

filters can be expanded as infinite impulse response filters. In designing IIR filters, cutoff frequencies of

the filters should be mentioned. The order of the filter can be estimated using butter worth polynomial.

That’s why the filters are named as butter worth filters. Filter coefficients can be found and the response

can be plotted.

Program

#include<stdio.h> #include<math.h> int i,w,wc,c,N; float H[100]; float mul(float, int); void main() {

printf("\ n enter orderscanf("%d",&N); printf("\ n enter the cutoff freq ");scanf("%d",&wc); printf("\ n enter the choice for IIR filter 1. LPF 2.HPF ");



function, described by polynomials in z in both the numerator and the denominator:

The difference equation for such a system is described by the following:


Coefficients are generated using FDS (Filter Design software or Digital Filter design package). IIR



’s why the filters are named as butter worth filters. Filter coefficients can be found and the response

n enter order of filter ");

n enter the cutoff freq ");

n enter the choice for IIR filter 1. LPF 2.HPF ");




Digital Filter design package). IIR



’s why the filters are named as butter worth filters. Filter coefficients can be found and the response

n enter the choice for IIR filter 1. LPF 2.HPF ");

48

scanf("%d",&c); switch(c)

{ case 1: for(w=0;w<100;w++)

{ H[w]=1/sqrt(1+mul((w/(float)wc),2*N));printf("H[%d]=%f\ n",w,H[w]);

} break; case 2: for(w=0;w<=100;w++)

{ H[w]=1/sqrt(1+mul((float)wc/w,2*N));printf("H[%d]=%f\ n",w,H[w]);

} break;

} }

float mul(float a,int x){

for(i=0;i<x-1;i++) a*=a; return(a);

}


H[w]=1/sqrt(1+mul((w/(float)wc),2*N)); n",w,H[w]);

for(w=0;w<=100;w++)

H[w]=1/sqrt(1+mul((float)wc/w,2*N)); n",w,H[w]);

float mul(float a,int x)


49


50

Matlab PROGRAM:

% % MATLAB program for IIR filters LPF & HPF design

clc;

clear all;

close all;

disp('enter the IIR filter design specifications');

rp=input('enter the passband ripple');


wp=input('enter the passband freq');

ws=input('enter the stopband freq

fs=input('enter the sampling freq');

w1=2*wp/fs;w2=2*ws/fs;

[n,wn]=buttord(w1,w2,rp,rs,'s');

c=input('enter choice of filter 1. LPF 2. HPF

if(c==1)

disp('Frequency response of IIR LPF is:');

[b,a]=butter(n,wn,'low','s');

end

if(c==2)

disp('Frequ ency response of IIR HPF is:');

[b,a]=butter(n,wn,'high','s');

end

w=0:.01:pi;

[h,om]=freqs(b,a,w);

m=20*log10(abs(h));

an=angle(h);

figure,subplot(2,1,1);plot(om/pi,m);

title('magnitude response of IIR filter is:');

xlabel('(a) Normalized freq.


subplot(2,1,2);plot(om/pi,an);

title('phase response of IIR filter is:');

xlabel('(b) Normalized freq.

ylabel('Phase in radians


IIR filters LPF & HPF design

disp('enter the IIR filter design specifications');

rp=input('enter the passband ripple');


wp=input('enter the passband freq');

ws=input('enter the stopband freq ');

fs=input('enter the sampling freq');

[n,wn]=buttord(w1,w2,rp,rs,'s');

c=input('enter choice of filter 1. LPF 2. HPF \n ');

disp('Frequency response of IIR LPF is:');

[b,a]=butter(n,wn,'low','s');

ency response of IIR HPF is:');

[b,a]=butter(n,wn,'high','s');

figure,subplot(2,1,1);plot(om/pi,m);

title('magnitude response of IIR filter is:');

xlabel('(a) Normalized freq. -->');

>');

subplot(2,1,2);plot(om/pi,an);

title('phase response of IIR filter is:');

xlabel('(b) Normalized freq. -->');

ylabel('Phase in radians -->');


51


52

6. Power spectral density

PROGRAM:

%MATLAB Program to find Power spectral densityt = 0:0.001:0.6; x = sin ( 2*pi*50*t)+sin(2*pi*120*t);y = x + 2*randn(size(t));figure, plot ( 1000*t(1:50),y(1:50))title('Signal Corrupted with Zeroxlabel('time (milliseconds)');Y = fft(y,512); %The power spectral density, a frequencies, is: Pyy = Y.* conj(Y) / 512;f = 1000*(0:256)/512; figure, plot(f,Pyy(1:257)) title('Frequency content of y');xlabel('frequency (Hz)');


%MATLAB Program to find Power spectral density

2*pi*50*t)+sin(2*pi*120*t); y = x + 2*randn(size(t));

1000*t(1:50),y(1:50)) title('Signal Corrupted with Zero -Mean Random Noise') xlabel('time (milliseconds)');

%The power spectral density, a measurement of the energy at various

Pyy = Y.* conj(Y) / 512;

title('Frequency content of y'); xlabel('frequency (Hz)');


measurement of the energy at various

53

7. SUM OF SINUSOIDAL SIGNALS

PROGRAM:

% MATLAB Program to find

clc;

clear all;

close all;

tic;

%giving linear spaces

t=0:.01:pi;

% t=linspace(0,pi,20);

%generation of sine signals

y1=sin(t);

y2=sin(3*t)/3;

y3=sin(5*t)/5;

y4=sin(7*t)/7;

y5=sin(9*t)/9;

y = sin(t) + sin(3*t)/3 + sin(5*t)/5 +

plot(t,y,t,y1,t,y2,t,y3,t,y4,t,y5);

legend('y','y1','y2','y3','y4','y5');

title('generation of sum of sinusoidal signals');gr id;

ylabel('--- > Amplitude');

xlabel('---> t');

toc;


OF SINUSOIDAL SIGNALS

% MATLAB Program to find sum of sinusoidal signals

%generation of sine signals

y = sin(t) + sin(3*t)/3 + sin(5*t)/5 + sin(7*t)/7 + sin(9*t)/9;

plot(t,y,t,y1,t,y2,t,y3,t,y4,t,y5);

legend('y','y1','y2','y3','y4','y5');

title('generation of sum of sinusoidal signals');gr id;

> Amplitude');


sin(7*t)/7 + sin(9*t)/9;

54


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