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Designer’sCompanionto verifying signal integrity

Designer’s Companion to Verifying Signal IntegrityPrimer

2 www.tektronix.com/signal_integrity

Table of Contents

Introduction and Overview ----------------------------------3 - 5

Design Project Overview 3

Measurement Steps Keep Pace with Design Steps 4

Review of Signal Integrity Concepts 5

Chapter 1 – Impedance Measurements --------------------6 - 10

The Foundation of Signal Integrity 6

Overview of Impedance Measurement Tools and Techniques 6

An Impedance Measurement Procedure and Its Conclusions 7

Setting Up and Making Connections 7

True Differential TDR Measurements 8

TDR Measurements and Results 9

Chapter 2 – ASIC Verification --------------------------------11 – 13

Ensuring Signal Integrity at the Source 11

Digital Verification Steps Range from Basic to Advanced 12

Chapter 3 – Basic Functional Verification ------------------14 – 18

Checking the “Heartbeat” of an Emerging Design 14

Verification Tools 14

Checking the Pulse of a New Design 16

Spread Spectrum Clocking and Serial ATA 17

SSC Example: The Serial ATA Clock 16

Chapter 4 – Internal Bus Compliance ----------------------19 – 23

Compliance Tests Pave the Way to Interoperability 19

Probing: Requirements for Compliance Measurements 19

Probing: Electrical Issues 19

Probing: Physical Considerations 20

Making the Connection 20

Compliance Tests Look at Signals from Many Perspectives 21

Acquisition, Then Analysis 21

Eye Diagrams:

The Cornerstone of Compliance Measurements 23

Chapter 5–Optional Validation, Fault Detection, and Debug --24 – 31

Looking at Digital Data and Analog Interactions 24

Logic Analyzer is the Right Tool for Digital Data Analysis 24

Making the Connection 25

Tracing the Error 26

Taking the Analog Perspective 27

Shortcut that Detect Signal Integrity Problems Quickly 29

iLink™ Toolset:Two Powerful Measurement Tools Team Up 31

Chapter 6 – External Bus Compliance ----------------------32 – 35

Critical Measurements Support Final Pass/Fail Testing 32

Self-Test Methods Depend on reliable Signals 32

Transmitter Tests Lay the Foundation 33

Optical Modulation Amplitude is Typical of 10 GbE Transmitter Measurements 33

Following the Standard 34

An “Approximate” Method for Estimating OMA 35

Chapter 7 – Characterization --------------------------------36

Defining and Specifying the Final Product 36

Specifications for the Designer and for the End-User 36

Chapter 8 – Summary and Conclusion----------------------37

Pre-Assembly Verification 37

Functional Verification and Troubleshooting 37

System Verification and Characterization 37


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Introduction and OverviewThis primer is intended for engineering professionals withan interest in high-performance digital system designunder real-world conditions: time constraints, costlimitations, quality requirements, and manufacturabilityconcerns.

The primer focuses on signal integrity, a key measurementissue affecting digital designs. The term “signal integrity”encompasses the analog factors that affect both theperformance and the reliability of digital designs. Assystem speeds increase, signal integrity becomes agreater challenge: it is ever more difficult to maintain cleanpulse edges, low noise and aberrations, and nominalamplitude and timing characteristics. A rigorous regime ofsignal integrity measurements can trace these problems totheir root causes.

Many designers are concerned with compliancemeasurements. Compliance with industry standardsensures interoperability among system elements, and themeasurements usually entail a series of prescribedacquisition and analysis steps. But successful compliancetesting often depends on finding and eliminating the signalintegrity problems that are a frequent cause of errors.Consequently this primer will examine not only codifiedcompliance measurements, but also the signal integrityissues that can affect them.

The design process is made up of multiple steps, eachwith its own particular signal integrity challenges andmeasurement needs. To illustrate some of the solutionsthat serve these needs, we will follow a new servermotherboard design as it proceeds from raw printedcircuit board (PCB) to finished product.

Design Project OverviewThe design is a server motherboard, illustrated in Figure 1-1*1. The performance of this motherboard, its processors, andchipsets will determine the overall data throughput of aflagship system-level product.

It is critical to maximize the data throughput, but not atthe cost of reliability. Every functional element of the newmotherboard must be validated along the way, fromimpedances on the raw circuit board to compliance testsand characterization of the completed design. Doing sowill speed development (catching problems early andminimizing rework) and enable the new product to reachthe market on time. In the highly competitive marketplacefor which the product is being developed, the majority ofthe profits will go to the product that delivers the mostperformance, soonest.

*1 The motherboard and system described in this primer are constructs created to illustrate the steps of the design process. The motherboard may includecombinations of features not commonly found within a single device. Nevertheless, each of the steps summarized in this document resolves a real-worldmeasurement challenge.

Figure 1-1. The server motherboard incorporates several industry–standard serial buses



4

The motherboard will be part of an end product designedfor customers who need a high-throughput serverimplementation. To deliver the requisite performance andreliability, the motherboard will incorporate advancedtechnologies such as PCI-Express, Serial ATA, XAUI,Gigabit Ethernet (GbE), and double data rate RAM (DDRRAM; in this case, the second-generation DDR 2).

PCI-Express replaces traditional chip-to-chip buses such as the graphics interface bus and the PCI system bus.Advanced PCI-Express implementations can provide arobust 10 Gb/s interface for the network fabric, supportingprotocols as diverse as Gigabit Ethernet, USB 2.0, 10 GbFibreChannel, and others. This motherboard designincludes a 4X PCI Express bus for graphics and a 16X PCIExpress bus for I/O.

Like many server designs, the motherboard relies on a pairof CPUs to execute instructions and move data speedily. Ahigh-speed Memory Controller Hub (MCH or “North Bridge”coordinates transactions and carries data between the DDR2 channel, the CPU pair, and other functional elements onthe board. The I/O Control Hub (IOCH or “South Bridge”)oversees transactions with external peripheral buses as wellas connections to internally-mounted PCI devices.

Multi-gigabit data rates are present on buses throughoutthe board. Unit Intervals (UI) are brief; in the low hundredsof picoseconds (ps). Many signals have risetimes below 100 ps. Data is transported both internally and externally on

differential transmission lines that must meet rigorouslyspecified industry standards. Most importantly, the board’shigh-speed operating characteristics require carefulattention to signal integrity issues.

Measurement Steps Keep Pace With Design Steps

The design project includes critical measurements at everystep. This calls for solutions that include high-performancereal-time and sampling oscilloscopes; Logic Analyzers;sophisticated probes and fixturing; and in some cases,specialized acquisition modules for TDR (time-domainreflectometry) and optical measurements. From ameasurement perspective the steps of the design processproceed as shown in Figure 1-2.

After a quick review of signal integrity definitions, we willfollow this sequence of steps to see how signal integritymeasurements play an enabling role in the development ofhigh-performance digital systems.

4

Check impedanceon PCB traces & connectors

Verify ICs will support systemspecs

Confirm signalintegrity and run eye diagramtests on outputs

Measure anddocument signal margins and limits

Check clocks, buses, enables, etc.

Performeye diagramanalysis

Run tests; detect errors; identify andtrack problems

Pre-Assembly Verification Functional Verification & Troubleshooting System Verification & Characterization

ASICVerification

Basic FunctionalVerification

Internal BusCompliance

OperationalValidation,

Fault Detection,Debug

External BusCompliance

ImpedanceMeasurements

Characterization

Figure 1-2. The steps in the motherboard design process.



Review of Signal Integrity Concepts

The notion of signal integrity*2 pertains to noise, distortionand anomalies that can impair a signal in the analogdomain. At frequencies in the gigahertz range, a host ofvariables can affect signal integrity: signal path design,impedances and loading, transmission line effects…evenpower distribution on the circuit board. It is the designer’sresponsibility to minimize such problems in the first place,and correct them when they appear.

There are two fundamental sources of signal degradation.

— Digital issues—typically timing-related. Bus contentions,setup and hold violations, metastability, and raceconditions can cause erratic signal behavior on a bus ordevice output.

— Analog issues—low-amplitude signals, slow transitiontimes, glitches, overshoot, crosstalk, and noise; thesephenomena may have their origins in circuit board designor signal termination, but there are other causes as well.

Not surprisingly, there is a high degree of interaction andinterdependence among digital and analog signal integrityissues. For example, a slow rise time on a gate input cancause the output pulse to be delayed, in turn causing a buscontention in the digital environment further downstream. Athorough solution for signal integrity measurement andtroubleshooting involves both digital and analog tools.

*2 The term “signal integrity” applies to the device under test. Another issue is “signal fidelity” which applies to the measurement equipment. Factors such as probe loading,measurement system bandwidth, and more determine signal fidelity. Meaningful signal integrity and compliance measurements require tools with good signal fidelity.



Impedance MeasurementsThe Foundation of Signal Integrity

Seasoned engineers know that signal integrity is the resultof constant vigilance during the design process. It’s all tooeasy for signal integrity problems to get compounded as adesign evolves, and to become more difficult to track down.A tiny aberration that goes unnoticed in the first prototypeboard can bring the whole system to a crashing halt whenthe board is merged with others.

Given these realities, where does signal integrity begin?Designers working on the most critical high-speedtechnologies often start their signal integrity work at the verybeginning—with the raw, unpopulated circuit board. Mosthigh-speed protocols require a 50Ω impedance; forexample PCI Express specifications call for a 50Ωtransmission line with 10Ω tolerance. Analyzingtransmission line principles is beyond the scope of thisdocument, but suffice to say that the tolerances are criticalto high-fidelity signal transmission. And less deviation isalways better.

Modern layout tools implement the applicable impedancerules for high-speed protocols, but physics, circuit boardmaterials, and human error can introduce unforeseendepartures. As a result, many developers have learned thata rigorous process of verifying impedance characteristicscan help them detect and correct problems early. Designchoices can be reconsidered, if need be, before quantityorders are placed with a vendor.

Our server motherboard layout includes many connectors.Some are edge-connector types, such as those in theupper left quadrant of the board. Others are industry-standard cable connections for buses such as 10 Gb

Ethernet CX4. A board’s complement of connectors makesup a significant part of the materials costs involved inmanufacturing the device. This simple fact prompts aconstant search for lower-cost substitutes for componentssuch as the PCI Express connectors. What impact mightthese proposed substitutes have on the high-speed signalsthat pass through them? Impedance measurements canhelp us decide whether the low-cost connectors will do the job.

The impedance measurement process will verify the tracesand their vias, pads, and lands. At the same time, it willdetermine the effects of two brands of PCI Expressconnectors under consideration.

Overview of Impedance Measurement Toolsand Techniques

The tool of choice for measuring impedances is a samplingoscilloscope such as the Tektronix CSA8000 or TDS8000Series equipped with the 80E04 Time DomainReflectometer (TDR) module. These are high-performancesampling oscilloscopes whose plug-in architecture enablesthem to implement both conventional sampling acquisitionand time domain reflectometry applications. The TDRmodule permits the signal transmission environment beanalyzed in the time domain, just as the signal integrity oflive signals will be analyzed in the time domain.

Time domain reflectometry measures the reflections thatresult from a signal traveling through transmissionenvironments such as circuit board traces, cables, orconnectors. The TDR instrument sends a fast step pulsethrough the medium and displays the reflections from theobserved transmission environment. Figure 2-1 is asimplified block diagram of this scheme.

6

Pre-Assembly Verification

Functional Verification &

Troubleshooting

ASICVerification



CS

A80

00 S

erie

s StepSource

80E04

DUT

Incident

Reflected

Sampler

Figure 2-1. Block diagram of a TDR acquisition setup using a TDR module



The TDR display is a voltage waveform that includes theincident step and the reflections from the transmissionmedium. The reflections increase or decrease the stepamplitude depending on whether the nature of thediscontinuity is more inductive or capacitive, respectively.

A reflection from an impedance discontinuity has rise timeequal to or—more likely—slower than that of the incidentstep. The physical spacing of any two discontinuities in thecircuit determines how closely their reflections will bepositioned relative to one another on the TDR waveform.Two neighboring discontinuities may be indistinguishable tothe measurement instrument if the distance between themamounts to less than half the system rise time.

The quality of the incident step pulse is critical, especiallywhen measuring short traces. In addition to its fast risetime,the step must be accurate in terms of amplitude and freefrom aberrations. The 80E04 TDR module’s incidentrisetime sets an industry benchmark in its class, and itsamplitude accuracy and step response aberrations arestate-of-the-art.

An Impedance Measurement Procedure andits Conclusions

The impedance measurement procedure that follows hasthree objectives:

— To detect any fundamental layout problems that arecausing the impedance of a trace, via, or pad to deviatebeyond its permissible tolerance; to find the physicallocation of such problem areas

— To compare and evaluate two brands of PCI Expressconnectors with the intent of qualifying the lessexpensive of the two for adoption into the design

— To ensure that the impedance environment is compliantwith applicable industry standards for all of the serialbuses on the motherboard, including PCI Express

Setting Up and Making Connections

Tektronix recommends calibrating the TDR beforeconducting PCB measurements. This is a process whichthe 8000 Series instruments can execute automaticallywhen equipped with software available at no charge fromTektronix. The calibration procedure, developed on behalf ofthe IPC (Association Connecting Electronics Industries), isknown as IPC-TM-650. Its intent is to ensure consistencyand a known degree of traceability in PCB impedancemeasurement results. To summarize the procedure:

— Connect the TDR module to the same fixturing—connectors, cables etc.—that will be used in the actualmeasurement procedures

— In place of the device under test, substitute a referencestandard air line or PCB coupon, and perform aconventional TDR measurement

— Save the result as a Reference waveform

The steps above are simplified for the sake of clarity (certaincalculations have been omitted), but the calibration softwarehandles these additional tasks. Once a reference trace isstored, it becomes the template against which “return”signals are compared for amplitude differences over time.

The next step is to connect the 80E04 TDR module to theDevice Under Test (DUT). Note again, the project objectivesare threefold: verifying circuit traces, comparing PCIExpress sockets, and compliance verification. The best wayto introduce the incident step to a socket is through SMAconnectors mounted on a fixture board that plugs into thesocket. The same path(s) can also conduct the step toPCB traces that branch from the socket.



The calculated differential TDR method can providevalid results in many practical situations. However, themore modern true differential TDR method has gainedbroad acceptance among designers for severalimportant reasons:

— The IPC-TM-650 impedance measurement standard(V2.5.5.7 or later) for printed circuit boards requirestrue differential measurements for appropriateprotocols

— Some protocol standards stipulate thatmeasurements be performed on powered links,which necessitates true differential signaling

— The calculations used to synthesize a differentialdisplay from non-differential signals will produceerrors if the signal contains nonlinearities. Sucherrors are extremely difficult to detect.

The Tektronix 80E04 TDR Sampling Module is a truedifferential solution. Figure 2-2 illustrates thesimultaneous (and complementary) incident pulseslaunched by the 80E04. Compare this with Figure 2-3,which depicts the serially-launched pulses of acalculation-based TDR (both illustrations represent anoscilloscope’s view of the TDR signals). If the DUTrequires powered measurements using differentialtransmission, then the serially-launched approach willnot suffice.

8

True Differential TDR Measurements

Many of today’s high-speed serial standards rely ondifferential transmission techniques usingcomplementary signals. Two “wires” or PCB tracescarry simultaneous mirror images of the signal. Thoughmore complex than the single-ended approach,differential transmission is less vulnerable to externalinfluences such as crosstalk and induced noise, andgenerates less of the same.

But differential paths require TDR measurements justas other transmission environments do. The incidentpulse must be sent down both sides of the differentialpair and the reflections measured. There are two waysthis can be done:

The “virtual” or “calculated” differential TDR method.The TDR sends out two positive-going incident stepsalternating in time, and corrects both the polarity andthe alignment before the measurement waveform isdisplayed on the oscilloscope screen.

The true differential TDR method. The TDR sends outcomplementary signals that are accurately andcorrectly aligned in time. The DUT receives a differentialstimulus signal more like those it will encounter in itsend user application, potentially producing betterinsights into the device’s real-world response. The TDRsystem does not need to manipulate the displayedstep placements.

Figure 2-2. True differential incident steps. The step and itscomplement are simultaneously launched. Figure 2-3. Serially-launched incident steps.The lower

waveform is not a true “complement” of the stepwaveform but rather a mathematical inversion.

Step

Complement

Step

Complement



Manual TDR probes and hardware positioners are alsoavailable but a dedicated SMA connection, whenpracticable, will always maintain the best signalenvironment. The threaded SMA connection providesexcellent shielding and controlled impedance. This ensuresthat the fixturing itself will have minimal impact on theoutgoing step or its returning reflections. Tektronixrecommends tightening the SMA collar with a specialwrench that applies the prescribed 5 inch-pounds (0.56Nm) of torque. This provides the tightest “seal” on the signalpath without risk of ruining the connector.

The PCI Express bus uses differential signaling. There aretwo methods of performing TDR measurements in adifferential environment (see Sidebar). The 80E04 module iscapable of true differential operation, and so will carry outthe necessary TDR measurements without the need forspecial calculations.

TDR Measurements and Results

The TDR is connected to the specific PCI Express tracethrough an SMA fixture board plugged into Socket A. Theincident step will see the effect of Sockets A and B, as wellas the vias and the Ball Grid Array (BGA) pad at the end ofthe trace. With no termination present at the BGA pad, theTDR trace will drive toward an infinite impedance.

The TDR display tells a detailed story about the impedancevariations in the signal path. Figure 2-4 is a TDR screenfrom the PCI Express measurement.

Figure 2-5 is simplified sketch of the same result. Thehorizontal scale has been compressed to depict all of theevents occurring over a fairly long trace. To see all theseevents in sufficient detail on the TDR itself, it would benecessary to expand horizontal (time) scale and scrollthrough the waveform record. The grey band across the topof the trace indicates the limits of the ±5% impedancetolerance set forth in the PCI Express standard.

The impedance display reads from left to right. The left-most events are those physically closest to the stepgenerator, the origin of the signal. Again, these arereflections produced by the elements along the signal pathwhen they receive the energy from the incident step. Aperfect path with perfect terminations would produce noreflections. But there is no such signal path in the realworld, and it is the designer’s job to understand andaccount for impedance variations.

Figure 2-4. TDR impedance measurement screenFigure 2-5. The TDR impedance display reveals how PCB features

such as connectors and vias can cause deviations inthe impedance environment.


10 www.tektronix.com/signal_integrity10

At the top of the step transition in Figure 2-5, there is amomentary overshoot caused by the step generator itself.Shortly after the waveform settles, it sees the traceimpedance, then it encounters the impedance effects of thefirst PCI Express connector—Event A in the illustration. Thisis the connector that is currently specified in the bill ofmaterials. Note that its impedance falls well within the ±5%tolerance range.

But the next aberration is clearly out of bounds. Event Bdefines the character of the second PCI Express socket inthe signal path. This is the low-cost connector beingconsidered as a substitute for the one currently designedinto the motherboard. Variations on this scale can affectsignal integrity by attenuating the signal, distorting it, oreven (if the impedance irregularity is mostly capacitive)giving it a path to adjacent traces.

Unfortunately the connector that produced Event B is notsuitable for adoption in the high-performance motherboard.Its impedance deviation disqualifies it.

Continuing down the path, we see reflections from two vias,then the normal rise in impedance when the incident stephits the open circuit at the BGA pad. If there was an ICdevice installed on the BGA site, then it would be possibleto characterize the impedance of the device pins and theirinternal bonding to the IC pads as well as the on-chipterminations. Alternatively, these measurements can beperformed on the IC device separately from the PCB.

Repeating the TDR measurement process on other tracesof interest will yield a detailed, high-confidence impedanceprofile of the raw PCB. “Up-front” work with the TDR canpreempt potential signal integrity problems after assembly.

Conclusion

The TDR measurement has met all of its objectives. Thelow-cost connector has been evaluated and disqualified,potentially saving untold headaches in later design andproduction steps. And the PCI Express layout has beenproven to meet the applicable standards for impedance.

Positive or Negative?

Even though the true differential TDR delivers an inverted(negative-going or complementary) pulse simultaneouslywith its positive counterpart, the resulting TDRimpedance display shows a seemingly uninvertedtrace—all values on the trace are positive. Why?

Consider what the display is showing: impedance inohms. It is comparable to measuring a potentiometerwith digital multimeter. You expect a range ofresistance values beginning at 0Ω and increasingpositively toward some maximum. The same is truewhen using a TDR to observe a passive element suchas a circuit board trace: the impedance is always apositive construct with the lowest possible value beingnear 0Ω. There are no negative ohms or Rho values.


ASIC VerificationEnsuring Signal Integrity at the Source

TDR measurements on the unpopulated motherboard arethe first critical step in the hardware verification process.The active devices that make the raw PCB into a servermotherboard are the next candidate for evaluation as thedesign moves ahead.

“Off-the-shelf” semiconductor devices are usually tested bytheir manufacturers, but many designers prefer to confirmthese performance claims rather than risking an entiredesign on unproven components. More importantly, earlysamples of custom devices must be verified. Short-runASIC prototypes (used to fabricate prototypes of the enduser product itself) will be tested and ultimately the devicetests might be released to production.

The verification process may include up to four types of tests:

— DC parametric—the most basic measurements to ensurethat the device provides proper logic levels under loadingand adequate current at each binary state and very lowleakage in the high-impedance “compliant” state.

— Analog functional—in mixed-signal devices, this testverifies the analog features. Again, simple digitalcommands set up the device and execute the gain andrange changes that are unique to analog components.

— Digital functional—a simple command set initializes thedevice in its various modes, then test vectors (binarydata) are applied at a low data rate. The resultingoutputs are compared with expected data.

— At-Speed functional—in effect, a digital functional test atthe device’s maximum clock and data rates.

The DC parametric and analog functional tests are beyondthe scope of this signal integrity discussion. But the digitalfunctional tests examine timing details that can impactsignal quality.

Recommended solutions for ASIC evaluation include theCSA8200 or TDS8200 sampling oscilloscopes, or a real-time oscilloscope such as the TDS7404B or TDS6804B;TLA Series Logic Analyzers (for situations requiring a deepacquisition memory for digital data); and DTG5000 DataTiming Generators (signal sources).

The issue of signal access is a challenge when testingcomplex ASIC devices. Particularly in the case of the at-speed tests, fixturing must be designed to connect—withthe least possible signal degradation—oscilloscopes andhigh-speed signal sources to a sequence of selected devicepins. Most designers also characterize the fixture itself(using a TDR as explained in the previous section) toprevent impedance-related signal distortions.

It is common practice to design fixtures with relay matricesto distribute oscilloscope inputs and signal source outputsto respective pins on the DUT. Test programmingenvironments such as National Instruments LabVIEW®

provide an expedient means to automate measurementsand control signal routing on the fixture. If properlydesigned, test programs developed for validation andevaluation can be ported to production test applicationswith minor modifications.

Pre-Assembly VerificationFunctional Verification

& Troubleshooting


ASICVerification





Digital Verification Steps Range from Basic to Advanced

“Setup” and “hold” timing values are essential specificationsfor any clocked digital device, and the heart of the ASICfunctional verification measurements. Setup time is definedas the length of time the data must be present (and in astable, valid state) before the clock edge occurs. Hold timedefines the amount of time that data state must bemaintained after the clock edge. In high-speed digitaldevices used for computing and communications, bothvalues may be as low as a few hundred picoseconds.Setup and hold violations can cause signal integrityproblems in the form of transients, edge aberrations,glitches and other intermittencies.

Figure 3-1 depicts a typical setup and hold timing diagram.In this example, the data envelope is narrower than theclock. This emphasizes the fact that when using today’shigh-speed logic, transition times and setup and holdvalues can be very brief even when the cyclical rate isrelatively slow.

There are two common approaches to evaluating the setupand hold time performance of a device (other timingparameters also can be verified using these methods):

— Low-speed tests: Depending on the requirementsforeseen in the end-user application, a fairly coarsefunctional verification procedure may be adequate. Insome cases it is not necessary to take quantitativemeasurements of the actual setup and hold values. If thedevice will tolerate a broad clock placement range, thetiming “test” may be as simple as running a low-speedfunctional data pattern, adjusting the clock edge’sposition relative to the data, and observing the results onan oscilloscope. The oscilloscope’s trigger is set to a50% level.

The device tends to become “metastable” as it exceedsits setup and hold timing limitations. Metastability is anunpredictable state in which the device output mayswitch to either “1” or “0” without regard to the logicalinput conditions. Similarly, excessive jitter may appear onthe output when setup and hold tolerances are violated.

— At-speed tests with “burst” data: The burst functionaltest exercises the device at rates approximating itsintended operational frequency. A signal source such asthe Tektronix DTG5000 Series Timing Generator candeliver a block of data to the DUT at rates much higherthan the basic functional test just explained. The processis still one of empirically finding a range of setup andhold values and specifying the system’s clock placementaccordingly.

Using the data generator to drive all of the device’sinputs, repetitive data patterns help isolate the recurringskew problems that cause repeated setup and holdviolations.

Setup

Hold

Clock

Data

Data Valid

Figure 3-1. Setup and hold timing diagram



Figure 3-2 depicts an integrated ASIC evaluation setup. Anoscilloscope works in conjunction with a TektronixDTG5000 Series signal source that addresses the devicevia an automated fixture. A relay matrix, not visible in thephoto, switches in DC and lower-speed signals forfunctional tests. Critical signal paths include impedance-controlled connection points for high-speed signals as well.Each of these is a potential test point to which theoscilloscope connects, depending on the needs of thespecific device test.

The oscilloscope may be a sampling instrument if thedevice under test has data rates in the multi-gigabit range.Alternatively, a real-time Digital Storage Oscilloscope (DSO)or Digital Phosphor Oscilloscope (DPO) can offer powerfultools such as integrated jitter measurement software and a broad selection of specialized triggering functions. Thesecapabilities are indispensable when it is necessary toscrutinize the signal’s analog characteristics over/undershoot,edge details, pulse flatness, glitches, and more.

For example, suppose a setup time violation occursoccasionally on a device that has been proven to becomfortably within specifications. The error might even bepattern-dependent, that is, it occurs only when a particular

data combination is present. The real-time oscilloscope candraw on a wealth of trigger types to isolate the problem. If aslow or distorted transition is suspected, for example, theinstrument’s Transition trigger can be set to detect the edge(either rising or falling) that is taking too long to make itsexcursion (Figure 3-3). This trigger condition can becombined with logic qualification or other timing variables.Similarly, jitter-related failures can be tracked down with theaid of jitter measurement software.

Conclusion

The ASIC evaluation step enables custom andprogrammable IC devices to be isolated from the systemenvironment and qualified for installation in the emergingmotherboard design. Moreover, it helps detect and avoidcircumstances that cause metastability, jitter, and noisewhich can cause signal integrity problems that impact othersystem elements.

Figure 3-2. ASIC measurement system and fixture Figure 3-3. The oscilloscope’s Transition trigger can be set todetect edges are are taking too long to complete theirtransition. In this example the trigger has found an edgethat takes more than 3.2 ns to switch from a high stateto low state.



Basic Functional VerificationChecking the “Heartbeat” of an Emerging Design

With PCB impedance measurements and ASIC verificationcompleted, it is time to assemble a prototype motherboardand begin “live” measurements. The next few steps in thedesign process are where the majority of functionalproblems emerge and must be solved. Many of theseproblems stem from signal integrity issues that areimpossible to detect until all of the board’s components arein place and working together.

As explained earlier, escalating data rates are at the heart ofmany signal integrity problems in today’s designs. In mostmodern bus protocols, the data rate is the basic currencyof a device’s throughput and efficiency. Raw bit ratesextend from about 1 Gb/s to 4.25 Gb/s depending on theprotocol, and multi-lane topology is often used to increasenet throughput. Some standards use a single lane; forFibreChannel 4X and Serial ATA, the data throughput isequal to the signaling rate. Multi-lane configurations scaletheir throughput in direct proportion to the number of lanesused. InfiniBand, PCI Express, and XAUI all have 4Xvariants that provide good optimization for 10 Gb/s, whileInfiniBand and PCI Express carry the concept even further.PCI Express offers up to 32 lanes (80 Gb/s) on the circuitboard and 16 lanes (40 Gb/s) at the connector. Note thatthe raw data is not the same as data transfer rate, which isexpressed in gigabytes per second (GB/s). Since datatransfer rate depends so much on processes occurring inhigher layers of the architecture, a physical-layercomparison is not useful.

Verification Tools

For the verification and troubleshooting steps in this part ofthe design process, the real-time DSO or the DPO are thetools of choice. Both types of instruments offer not only thenecessary performance (bandwidth, sample rate, etc.), butalso a wealth of triggering choices, probing options,application-specific software packages, and more. Mostimportantly, these real-time platforms make it easy to probea series of test points and reliably acquire waveformsranging from power supply noise to multi-GHz datastreams. Automated setup routines find, scale, and displaythe signal, while cursors and built-in automatedmeasurements simplify analysis.

The DSO is ideal for low- or high-repetition-rate signals withfast edges or narrow pulse widths. The DSO also excels atcapturing single-shot events and transients, and it is thebest solution for multi-channel acquisition at highbandwidths and sample rates. For the motherboard designproject, Tektronix’ TDS6000B Series DSOs are anappropriate solution.

The DPO is the right tool for digital troubleshooting, forfinding intermittent signals, and for many types of eyediagram and mask testing. The DPO’s extraordinarywaveform capture rate overlays sweep after sweep ofinformation more quickly than any other oscilloscope,presenting frequency-of-occurrence details—in color—withunmatched clarity. The Tektronix TDS7000 Seriesexemplifies a DPO solution that meets the exacting needsof digital system design applications.

In any high-speed measurement, the choice of probes iscritical. The oscilloscope and the probe work together as ameasurement system. If possible the probe should providethe same bandwidth as the oscilloscope itself. In addition toits absolute bandwidth rating, the probe should have theleast possible loading impact on the signal. Many serialbuses require differential signal paths which are best servedby true differential probes.

Functional Verification & Troubleshooting

Pre-AssemblyVerification


ASIC Verification




Ideally the measurement system bandwidth, including thatof the probe, should be at least three times (3X) thefrequency of the signals to be observed. That equates toabout 7.5 GHz for the 2.5 Gb/s data rates used on the newmotherboard. The probe most suitable for this application isthe Tektronix P7380 probe (Figure 4-1), an 8 GHz truedifferential probe whose risetime, only 35 ps (20% to 80%)meets the needs of fast serial signals. Its ultra-low loadingand diversity of attachment methods ensure fast, positiveconnection with minimal effect on signals. The tiny probe tipmakes it easy to reach into narrowly-spaced traces anddevice pins.

Table 4-1 lists some representative high-speed buses anddevices, showing the oscilloscope and probe combinationsthat match their technical requirements.

The oscilloscopes and probes described here will be usedin all of the design verification and compliance steps to follow.

Protocol/Bit Rate Oscilloscope Probe

(per lane)

• PCI Express • TDS6000B with • P7350SMA/P7380SMA

2.5 Gb/s opt. RTE, PCE

• Serial ATA II • TDS7704B with • P7380SMA

3.0 Gb/s TDSJIT3 (opt. JT3),

Serial ATA Test SW

• Serial RapidIO • TDS7704B with • P7260, P7240,

3.125 Gb/s TDSJIT3 (opt. JT3) P7330, P7350

• Infiniband • TDS6000B with • P7350SMA/P7380SMA

2.5 Gb/s opt. RTE, IBA

• IEEE 1394 (Firewire) • TDS7704B with • P7260, P7240,

3.2 Gb/s TDSJIT3 (opt. JT3) P7330, P7350

• 10 GbE XAUI • TDS6804B with opt RTE, • P7380SMA, P7260

3.125 Gb/s TDSJIT3 (opt. JT3)

• FibreChannel • TDS7704B with opt. RTE, • P7380SMA, P7260

2.125 Gb/s (2X) SM, TDSJIT3 (opt. JT3)

4.25 Gb/s (4X) • CSA/TDS8200, 80A03,

80E02/3/4, A0A05

• USB 2.0 • TDS7404B with opt. USB • P7260, P6248, P6247,

480 Mb/s P6245 (3), TCA-BNC,

TCP202

Figure 4-1. Differential Probe (foreground shows handheld tip assembly)

Table 4-1. Summary of high-speed protocols and measurementsolutions



Checking the Pulse of a New Design

The motherboard prototype is assembled. The board haspassed its visual inspection for common hardwareproblems such as solder bridges and misplacedcomponents. The system BIOS chip is installed. Externalpower supplies are connected and powered up.Subsequent steps in the process will track down code-leveloperational problems and their sources, but a preliminaryseries of checks must confirm the presence, timing, andintegrity of the basic signals that support the board’sfunctionality.

In the past, the “heartbeat” checks on prototype deviceswere straightforward. But all that changed when high-speedtransmission became the norm, and serial buses introducedchallenges such as encoded signaling and embeddedclocks.

With an embedded clock, there is no clock trace to probe.The clock signal is woven into the data stream, and specialmeasurement tools are required to extract the clockinformation. Some oscilloscopes such as the TektronixTDS6000B or TDS7000B Series have clock extractionfeatures built in. These features can be supplemented withpowerful software tools to automate measurements onspecific serial protocols, or to measure jitter attributes.

The Tektronix TDSJIT3 jitter measurement toolset is avaluable asset when working with Spread Spectrum Clock(SSC) technology. SSC minimizes radiated electromagneticinterference (EMI), and is gaining favor as a solution thatcan forestall problems during EMI compliance testing.Because SSC is new to many digital system designers, itmerits special attention during the prototype checkout.

Embedded SSC resists conventional measurementapproaches. Yet it is essential to ensure that the embeddedSSC clock is present and operating within specifications.

SSC Example: The Serial ATA Clock

Spread spectrum clocking intentionally varies the frequencyof the clock signal to distribute its energy over manyfrequencies. In contrast, jitter can be defined as anunintended timing variation. But the same tool, the TektronixTDS Series application package known as TDSJIT3, candistinguish either type. We can take advantage of thiscapability to observe the embedded spread spectrum clockand confirm that its characteristics and transitions (Off -Onand On-Off) comply with industry standards.

TDSJIT3 software provides a comprehensive set ofmeasurements for jitter parameters. These terms includecycle-to-cycle jitter, time interval error (TIE), and more. TheTDSJIT3 feature best suited for our SSC measurement isthe Time Trend plot. This plot displays the jitter value versustime to reveal repeating patterns such as modulation,various periodic frequency components, and… spreadspectrum frequency variations.

The object of this example is to evaluate the SSCfunctionality on a Serial ATA II (SATA II) bus. The embeddedclock runs at 1.5 GHz and varies by less than 3% over a33.3us interval. To capture the signal, we will use the P7380differential probe’s variable-spacing tip to probe near theSATA connector.

Ten cycles of the 33 kHz modulation frequency on the 1.5Gb/s data must be captured. The Tektronix TDS6804Boscilloscope will perform the acquisition. It is among thefew available solutions that can capture the necessary 330uS of signal data at its full 20 GS/s sample rate.

Once the signal data is acquired, TDSJIT3 establishes areference clock from the data signal. The result is a jitter-free clock with the same mean frequency and phase as thedata. Then TDSJIT3 automatically plots the changes in therecovered clock period.



fnom

(1-δ)fnom

0.5/fm 1/f

Spread Spectrum Clocking and Serial ATA

In most parts of the world, electronic products soldcommercially must meet radiated emissions limits.High-frequency digital operations, particularly clocksignals, tend to emit energy that can leave the “box”and act like stray RF signals in the surroundingenvironment. These signals can cause trouble in otherequipment ranging from cellular phones to heartpacemakers.

Radiated emissions from the clock signal can bereduced by modulating the clock frequency using atechnique known as Spread Spectrum Clocking (SSC).Just a tiny amount of modulation—as low as a fewpicoseconds—is all that is necessary to minimizeemission problems. Many serial buses, notably PCIExpress and Serial ATA, rely on SSC techniques tocontrol radiation.

The characteristics of the SSC implementation areprecisely spelled out in industry specifications. Rangesand tolerances are critical, since the clock affects everytransaction on the bus. For Serial ATA (SATA) forexample, standard V1.0a outlines a group of SSCrequirements, among them:

— When SSC is employed, all device timings (includingjitter, skew, clock period, output rise/fall times, etc.)must meet the existing non-SSC specifications

— The minimum Unit Interval (UI) time is 666.43 ps; themaximum is 670.12 ps

— The preferred modulation method is “down-spreading;” adjusting the spread technique topreclude modulation above the nominal frequency.

— For triangular modulation, the clock frequencydeviation must be down-spread and shifted no morethan 0.5% from the nominal frequency; that is,+0%/-0.5%.

— The modulation frequency of the SSC must be inthe range of 30-33 KHz

Figure 4-2 depicts the triangular SSC modulationprofile defined in the SATA I V1.0a specification. Here,fnom is the nominal clock frequency (without SSC), fmis the modulation frequency, and δ is the modulationamount. The horizontal axis expresses time.

To understand how the SSC modulation operates onthe clock frequency, see Figure 4-3. For the sake ofclarity, this scenario shows the clock periodunchanging for several cycles. Interval T1 is the sameas T2, T3, etc. up to the point at which the modulationenvelope begins to turn upward on the graph. Then theclock period begins to get longer with each successivecycle. Mid-way through the excursion, the period is Tn,that is, some value greater than T1, T2, and so on.Eventually the degree of modulation peaks and beginsto turn down, following the modulation profile justexplained.

The small amount of SSC modulation is virtuallyimpossible to observe in real time with a conventionaloscilloscope measurement. To analyze the behavior ofan SSC-modulated signal, it is necessary to captureand store at least ten cycles’ worth of modulationactivity, recover the embedded clock, then plot thechange in the clock period over time. The analysisfeatures in the latest TDSJIT3 toolset are indispensablefor this task.

Clock Signal

Clo

ck P

erio

d

Time

T1 T2 Tn

Figure 4-2. Modulation profile of a SATA spread spectrumclocking scheme

Figure 4-3. The SSC clock period increases in proportion tothe modulation amount (dotted line).



Figure 4-4 depicts a TDSJIT3 record showing the SSCclock modulation profile observed on the SATA bus. Notethat this is not a waveform! It is a plot showing frequencydeviation in the signal mapped over the allowable range ofunit interval tolerances. The baseline value is the minimumUI: 666.4 ps. The peak excursion approaches—but doesnot exceed—the maximum UI, that is, 670.1 ps. The periodof the 1.5 GHz clock is changing by less than 4ps. TDSJIT3has extracted the needed information from a complex, fast-changing signal.

In Figure 4-4, the modulation profile accurately follows theguideline for a down-spread clock signal. This confirms that1) the SSC implementation is applying modulation correctlyand within specifications, and 2) the transition betweenstates (Off-to-On in this case) is clean and free ofaberrations. Note the similarity between this plot and Figure4-2, the profile taken from the SATA V1.0a specification. Asecond acquisition is required to capture the On-to-Offtransition.

Design or layout errors can have a radical impact on theperformance of the SSC implementation. Fortunately, thesetoo can be captured with TDSJIT3. Figure 4-5 illustrates aspread spectrum clock signal that has a large transient atthe beginning of the Off-to-On transition. Moreover, the

modulation amount is well below the range allowed in thespecification (this may be a deliberate choice). The transientalone is enough to disturb operations on the SATA bus. Theaberration may have its origins in the SSC design itself, or itmay be an artifact of other system behaviors such asground bounce or crosstalk. The low amplitude of themodulation implies a flaw in the SSC design. In any event, aproblem in the modulation profile has been identified by theTDSJIT3 application, and the problem must be resolvedbefore proceeding with the compliance and functionalevaluation steps to come.

Conclusion

The TDSJIT3 jitter analysis application has confirmed thatthe embedded SSC is functioning correctly. Othermeasurements, performed on key control signal lines usingconventional point-to-point probing, prove that themotherboard is ready to proceed with further operationaland compliance testing.

Until recently, heartbeat checks consisted of little more thanverifying the presence of a clock signal. Today we mustextricate the clock from high-speed data and examine itsstatic and dynamic (modulation) behavior. Fortunately, thisincreased complexity has been met by tools that rely on built-in application expertise to deliver results quickly and accurately.

Figure 4-5. This spread-spectrum modulation profile traces theeffect of a transient.

Figure 4-4. Modulation profile for a spread-spectrum clock. Thevertical axis represents the amount of modulation being applied.



Internal Bus ComplianceCompliance Tests Pave the Way to Interoperability

With the server motherboard assembled and its powersupplies and clocks verified, internal buses such as SATA IIare the next order of business. These devices must bechecked not only for functionality but also for theircompliance with applicable industry standards. It is the onlyway to ensure interoperability with the other subsystemsthat will reside within the server. When a hard disk drivearray, for example, is integrated with the motherboard, wewant to be as confident as possible that the motherboard isdelivering signals with the proper characteristics. Signalintegrity plays a key role, affecting the eye diagrammeasurements that are the basis of most compliance tests.In addition, some signal integrity factors (for example, jitter)may have their origins on the motherboard and must becontrolled at their source.

Like the other measurement steps in the motherboarddevelopment process, verifying compliance on the board’sinternal serial buses requires rigorous probing, acquisition,and analysis methods. The compliance tests in this sectionwill focus on the Serial ATA II bus, which is the transmissionchannel to the externally-mounted hard drives serving themotherboard.

Probing Requirements for ComplianceMeasurements

Every measurement begins with a reliable contact to thedevice under test, and compliance measurements are noexception. High-performance oscilloscopes suitable forcompliance work can be outfitted with a range of probetypes. These include differential probes, various high-impedance FET probes, and various modular “browsing”formats with adapters for diverse contact situations. Notonly electrical requirements, but also physical realities, guidethe choice of a probe for the internal bus compliance tests.

Probing: Electrical Issues

Most serial buses transmit signals differentially, thereforecompliance tests must capture signals differentially. Oneapproach is to use a pair of single-ended probes feedingtwo oscilloscope inputs, then process the incoming signalswith a math operation. Most oscilloscopes can do this.However this method consumes two inputs, meaning that afour-channel oscilloscope can monitor only two activesignals (two differential pairs) at a time. In addition, the mathoperation precludes some types of measurements and eyediagrams.

In contrast, a true differential probe combines the twobranches of the differential signal outside the oscilloscope,delivering one single-ended signal per probe to theacquisition system. Skew problems are minimized and theinstrument’s full channel count is available.

Other electrical considerations include bandwidth, ofcourse; like the oscilloscope itself, the probe’s bandwidthand edge response (risetime) must meet the needs of theDUT. As a rule of thumb, the measurement systembandwidth should be at least 1.8 times the data rate that ofthe device being observed, equivalent to 3.6 times thefundamental frequency of data in the non-return to zeroformat. The low-voltage differential signaling (LVDS), CurrentMode Logic (CML), and Positive Emitter Coupled Logic(PECL) signals common in many serial buses require a low-capacitance, low loading probe. Both DC resistance andAC impedance must be maximized in order to provide astable, very low current burden on the signal.








Probing: Physical Considerations

The choice of probes is also affected by the physicalaccessibility the signals of interest.

In high-speed designs such as our motherboard, it iscommon practice to route critical signals to impedance-controlled coaxial test points, usually SMA high-frequencyconnectors, for the most positive connection toinstrumentation. This is particularly useful during prototypedevelopment. A probe designed to mate directly to suchtest points without intervening tips or jumpers is thepreferred solution for this application. An example of thisapproach is the Tektronix P7380SMA probe, an 8 GHz toolaimed at high-speed serial measurements and other digitalsignal applications. The P7380SMA is commonly used inapplications which can afford to dedicate PCB real estate totest connectors.

In contrast, when the signal is available only on the pins ofa fine-pitch surface-mount device (SMD) or on a via in themidst of densely packed traces, a probe with very small,flexible contact points is best for the job. An example is theTektronix P7380 probe (Figure 5-1), which uses a tinypassive probe tip element, separate from the probe’sinternal amplifier circuit, to extend the usable reach of theprobe. Its distributed attenuator topology preserves high-frequency signal fidelity and edge response characteristics.

Making the Connection

On our motherboard, the SATA II bus goes to the edge ofthe PCB, where a connector meets the cable that carriesthe signals to a hard disk drive. Following the processexplained earlier in this document, both the PCB signal pathand the connector have been pre-screened with a TDR.The connector provides an ideal access point for ourcompliance measurements.

A simple “extender” makes it possible to connect theoscilloscope to the signal path via the motherboard’s SATAII connector. The extender is a small PCB mounted with apair of SMA connectors. Each SMA connector brings outone side of the differential signal. The extender plugsdirectly into the SATA II connector using the pinout specifiedin the applicable industry standard. Figure 5-2 depicts sucha fixture in a typical compliance measurement setting.

When the P7380SMA differential probe is connected to thefixture, the whole apparatus appears as a properlyterminated load for the signal. This ensures an optimal,controlled environment for compliance tests. Moreover, theconnection is positive and stable, a requirement when thetest plan includes multiple measurements performedsequentially.

20

Figure 5-1. This P7380 differential probe includes adapters that aidaccess to hard-to-reach PCB features. Some types ofleads can be soldered down for the most secure contact

Figure 5-2. The P7380SMA probe connects to the SATA busthrough an extender plugged into the device’s output connector



Some probes, notably the P7380SMA, provide the flexibilityof an adjustable termination voltage. The terminationvoltage can be adjusted to match the input signal commonmode voltage for minimum DC loading on the input signal.In addition the voltage can also to varied to stress-test theinput signal driver during the evaluation process.

Compliance Tests Look at Signals from ManyPerspectives

All serial standards include amplitude, timing, jitter, and eyediagram measurements within their compliance testingspecifications. Of course, standards differ from one to thenext, and not all measurements are required for compliancewith every standard. Following is an overview of some keycompliance measurements.

— Amplitude tests ensure that the signal has enoughamplitude tolerance to do its job under worst caseconditions

— Differential Voltage tests confirm that a specific minimumdifferential voltage will arrive at the receiver under worst-case media conditions (maximum loss). This ensuresproper data transfer.

— Common Mode Voltage Measurements detect anycommon mode imbalances and noise, and help locatecrosstalk and noise effects that may be coupling into oneside of the differential pair and not the other.

— Waveform Eye Height tests characterize the data eyeopening in the amplitude domain. It is measured at the.5 Unit Interval (UI) point, where the UI timing reference isdefined by the recovered clock.

— Timing Measurements detect aberrations and signaldegradation that arise from distributed capacitance,crosstalk, and other causes that affect signal integrity.

— Unit Interval and Bit Rate measurements look atvariations in the embedded clock frequency over a largenumber of consecutive cycles.

— Rise/Fall Time measurements confirm that the transitiontimes are within acceptable limits. Edges that are toofast can cause EMI issues, while those that are too slowrise can cause data errors.

— Waveform Eye Width measurements can verify thegeneral “health” of the signal if accompanied bystatistical details about the number of edges used in themeasurement.

— Jitter measurements to determine factors such asrandom jitter, deterministic jitter, and total jitter (at aspecific Bit Error Rate) are required in many serial busspecifications.

This is a partial list of compliance measurements. Fullcompliance tests may include 50 individual parameters ormore, though many of these are extracted from the basiceye diagram acquisition.

Acquisition, Then Analysis

With today’s tools, the actual measurements might just bethe easiest part of compliance testing. A case in point is theTDS RT-Eye™ compliance measurement package, whichtransforms a host TDS Series oscilloscope into a full-featured automated compliance tester. Once the hardwareconnections to the DUT are in place and the basic testrequirements selected from a menu, the eye diagramportion of the compliance test procedure becomes a “one-button” operation. This is the procedure we will follow forthe compliance tests on the motherboard project.

The application’s first step toward creating an eye diagramis recovering the clock from the serial bit stream. Methodsrange from Phase Lock Loop (PLL) recovery tooversampling; the Serial ATA II standard calls for the PLLmethod. TDS RT-Eye™ package, a general-purposetoolset, can be equipped with a Serial ATA module that ispreconfigured with this clock extraction scheme. Theapplication’s flexible software-based clock recoveryapproach enables it to meet the needs of a wide range ofstandards and their variants.



The measurement application automatically sets up thetrigger points, waveform scaling, and performs the clockextraction. TDSRT-Eye™ “knows” about details of thespecific standard: spread spectrum clocking, pre/de-emphasis, and other variables that affect the acquisition.These would be very complex to program into theoscilloscope manually.

Serial ATA II requires that compliance-related jittermeasurements be performed on a specified number ofconsecutive (contiguous) bits. This requirement can only besatisfied by a real-time oscilloscope; a sampling instrumentwith its equivalent-time acquisition can not capture thenecessary consecutive cycles except with special repeatingtest patterns designed for the purpose.

The TDSRT-Eye™ application software deals with the setupand acquisition. The tool derives eye diagrams and variousindustry-specified jitter parameters from a single real -timewaveform acquisition. In critical applications, additionalconfidence can be gained by accumulating statistics overmultiple acquisitions.

To perform real time jitter measurements such as RandomJitter (RJ), Deterministic Jitter (DJ), and Total Jitter (TJ) at a10-12 bit error rate (one part per trillion), a jitter test patternlength must be specified. This is a decision left to the user,who may have proprietary guidelines to meet in addition toindustry compliance specifications. Popular jitter testpatterns include TS1, CJTPAT, CSPAT, CRPAT, and more;some measurement packages offer these as an integralpart of the toolset.

The TDSRT-Eye™ application is known for its versatilesoftware clock recovery algorithm. It is equally at home witha PLL methodology or phase interpolation, to name just twoexamples. It encompasses many serial standards, andimportantly, it can adapt to evolutionary changes in thosestandards. As part of the TDSRT-Eye™ analysis application,the software clock recovery algorithm is designed tosupport post-acquisition analysis and reporting.

But what if there is a need for troubleshooting the bus,probing and observing waveforms in real time? Softwareclock recovery is less suitable for this purpose. “Touch-down” probing applications are better served by a hardwarePLL clock recovery architecture such as that built into theOption SM toolset for TDS Series oscilloscopes. With thisfeature, each time the probe contacts the signal, the clock

recovery is less flexible than its software counterpart, it isthe right solution for fast debug work.

Figure 5-3 presents the results of the SATA II compliancetest. The eye diagram appears to be well within the masktolerances, and the quantitative measurements listed in theResults Summary table confirm that. The measurementapplication has compared its actual acquired values withthe limits drawn from the published SATA II standard Theseterms reside within the application. All of the relevantparameters have passed the compliance test.

The Serial ATA II bus is just one of several serial buses onthe motherboard, but the compliance test procedures for allof them are similar. When TDSRT-EyeTM has checked all thebuses for compliance, the device is ready to move on to thefunctional testing and debug step.

Conclusion

Compliance testing is not optional—it is mandated underindustry standards and expected by end-users. Eyediagrams are the most important tool for most compliancetests. Smart automated software tools integrated into high-performance oscilloscopes minimize the burden of eyediagram measurements. They provide easily-documentedproof of compliance and can reveal hidden problems due tonoise, jitter, aberrations, and other signal integrity issues.

22

Figure 5-3. Serial ATA II compliance measurement as displayed bythe automated TDSRT-Eye measurement package.



Eye Diagrams: The Cornerstone ofCompliance Measurements

The eye diagram has become the definitive tool forvalidation and compliance testing of digitally-transmitted signals. It is a display, typically viewed onan oscilloscope, that quickly reveals impairments in ahigh-speed digital signal.

The eye diagram is built up by overlaying the waveformtraces from many successive unit intervals (UI). Eyediagrams display serial data with respect to a clockrecovered from the data signal using either hardware orsoftware tools. In the illustration shown here, the clockwas recovered by a hardware-based “Golden PLL.”The diagram displays all possible transitions (edges),positive-going and negative-going, and both datastates in a single window. The result is an image that(using some imagination) resembles an eye, as shownin Figure 5-4.

In an ideal world, each new trace would line upperfectly on top of those that came before it. In the realworld, signal integrity factors such as noise and jittercause the composite trace to “blur” as it accumulates

The blue regions in Figure 5-4 have special significance.They are the violation zones used as mask boundariesduring compliance testing. The blue polygon in thecenter defines the area in which the eye is widest. Thisencompasses the range of safe decision points forextracting the data content (the binary state) from thedemodulated signal. The upper and lower blue barsdefine the signal’s amplitude limits.

If a signal peak penetrates the upper bar, for instance,it is considered a “mask hit” that presumably will causethe compliance test to fail (some standards maytolerate a small number of mask hits). More commonlynoise, distortion, transients, or jitter cause the traces tothicken. The eye opening “shrinks,” touching the innerblue polygon. This too is a compliance failure, since itreveals an intrusion into the area reserved forevaluating the state of the data bit.

The eye diagram’s compelling advantage is that itenables a quick visual assessment of the signal’squality. The information-rich display looks like it mightbe a challenge to set up and acquire. But moderndigitizing oscilloscopes such as those in the TektronixTDS family can be optioned with tools that expeditethe complex clock recovery, triggering, and scalingautomatically, then perform quantitative measurementson the data. With these software and hardwarefacilities, the eye diagram measurement has become a“one-button” operation.

Figure 5-4. Eye diagram. The blue areas are the mask violation zones.


z


Operational Validation, Fault Detection, and DebugLooking at Digital Data and AnalogInteractions

Everything is in readiness: clocks checked, ASICs verified,compliance proven. Now begins the operational validationstep, the first look at the integrated features of themotherboard. For the first time we will see whether thesystem will accept, transfer, process, and store informationas intended. The proof of the design lies in its ability tohandle instructions and deliver the expected response.

A design as complex as a server motherboard is almostcertain to encounter some errors during development.These may include incorrectly placed components, logicdesign problems, improper terminations, and more. A buschannel or memory signal whose analog characteristics—risetime, amplitude—are flawed can cause an error in ahigh-level system instruction. Conversely, fast-changingdigital switching on a bus can impact the analog behaviorof signals on nearby traces. The engineer is left with thechallenge of detecting and correcting issues like these inthe least possible time.

It is a matter of quickly identifying the real cause of theproblem. Analog or digital? It means choosing tools andtroubleshooting methods that address both domains. Thefavored solution for such challenges is a pairing of familiarinstruments: a high-bandwidth DSO or DPO and a LogicAnalyzer. The DSO is the best tool for observing individualevents such as glitches, as well as distortions, transitiontimes and critical setup and hold timing values. The logicanalyzer captures logic signals in their elemental form—binary values with associated timing information—as they

move through the system. Capturing the interaction betweenthe two domains is the key to efficient troubleshooting.

Some modern solutions, notably the Tektronix Series LogicAnalyzers and the TDS Series DPOs include features tointegrate the two instruments, sharing triggers and time-correlated displays. Figure 6-1 diagrams this approach. Inthis chapter we will see how these instruments, workingtogether, can drill down to low-level design problems.

Logic Analyzer is the Right Tool for DigitalData Analysis

The Logic Analyzer is indispensable for digital signalvalidation and troubleshooting. Equipped with accessoriesranging from probes and fixturing to bus support packagesand software disassemblers, the Logic Analyzer capturesinformation on a bus and displays both timing diagramsand state information. It can trigger on a particular dataword or an error such as a setup and hold violation.Alternatively it can receive an external trigger and recordsynchronized cycle-by-cycle state data.


System Verification & Characterization





TLA Series Logic Analyzer

Integrated Digital-Analog Probe

Communication Bus

Trigger Bus

Analog Signals

TLA Series Logic Analyzer

TDS Series OscilloscopeiViewTM

iCaptureTM

Figure 6-1. The iLink™ toolset includes the iCapture™ acquisitionfeature, which allows the logic analyzer to acquire bothdigital and analog signals simultaneously through asingle probe; and the iView™ integrated analog digitaldisplay capability, which brings time-correlated analogwaveforms to the logic analyzer screen.



Making the Connection

It is common practice to design in dedicated testinstrument connectors on high-performance digital PCBs.Our motherboard includes pads designed for the TektronixP6980 compression probe. The P6980 dispenses withcostly on-board test connectors, mating instead to thecircuit boards pads via cSpring (cLGA) connections (Figure6-2). Equally important, it is designed to deliver selectedanalog signals to an oscilloscope connected to the logicanalyzer via the TLA iCapture™ multiplexer. At the sametime, it drives digital signals to the Logic Analyzer.

With the motherboard powered up and running, the LogicAnalyzer acquires data from the test points. Typically thisdata takes the form of hexadecimal machine code, or itmay be correlated to the high-level instructions that createdthe code. Alternatively, the Logic Analyzers “timing” modedisplays binary waveform representations. In any event,data accumulates in the Logic Analyzers memory, whichmay be as deep as 256.

In the example application, assume that two separatebuses—“A3,” a four-bit bus, and “A2,” an eight-bit bus—must be verified. A logic analyzer probe is connected to thetest points as shown in Figure 6-2. Initially the two busesseem to be transferring data just as the motherboarddesign models predicted.

But after a few cycles of operation, errors begin to appearon the A3 bus. A value that should be “8” shows up as a“0” not just once, but repeatedly. It is not a “stuck bit” ormisrouted signal; that would cause the same error to occurcontinuously. The erratic nature of the problem impliessome intermittent event is being mistaken for a legitimatedata bit, altering the value of the hexadecimal results. Therepeating nature of the problem points toward a glitch thatis caused by an error in the layout or assembly of theprototype motherboard. And the hexadecimal value, 8instead of 0, implies a problem in the most significant bit ofthe A3 bus (Note: the logic analyzer detects errors on otherbuses, but this discussion will focus on a particular issueaffecting A3 for the sake of clarity).

What are the circumstances under which the A3 bus errorappears?

Figure 6-2. The connectorless 32-channel probe conducts bothdigital and analog signals to the logic analyzer.Theunused PCB test pads next to the probe accept asecond probe.



Tracing the Error

The true nature of the error begins to reveal itself after anacquisition with the logic analyzer’s glitch capture triggerand display, which activates when it detects glitches, thenflags their location in the timing display. The Logic Analyzerdefines a “glitch” as an occurrence of more than one signaltransition between sample points. Figure 6-3 depicts theresulting display on a TLA Series Logic Analyzer.

Note that there are two types of “waveforms” displayed inFigure 6-3. Each of the two busses, A2 and A3, issummarized with a bus waveform that reflects the wordvalue on the respective bus. Bus waveforms provide an at-a-glance indication of the state of many individualsignals, saving time when troubleshooting. In addition thedisplay can be configured to break out each individualsignal line and again flag the glitch locations.

In Figure 6-3, the period between clocks is 4.00 ns. In TLASeries Logic Analyzers, the MagniVu™ acquisition capturesthe signal values at 125 ps intervals, and this informationcan be displayed as a separate, high-resolution view of anysignal. This feature acquires the high-resolution data at thesame time as the main timing data, through the sameprobe.

Figure 6-4 illustrates the display with the MagniVu™acquisition traces added. Here, both the 125 ps clock ticksand the more detailed view of signal A3-3 are shown alongwith the bus waveform views. The signal shows a brieftransition in the latter half of the cycle. Since we alreadyknow that the cycle is producing an incorrect bus value, this transition is likely the cause of the error. But what iscausing the invalid transition?

Figure 6-3. The LA has triggered on the glitch and flagged the individual glitch locations.



Taking the Analog Perspective

Frequently, digital signal aberrations arise from analog signalintegrity problems. The iLink™ toolset shown earlier (Figure6-1) makes it easy to explore the analog characteristics ofdigital anomalies. The TLA iCapture™ multiplexer deliversany four signals from the P6980 probe to an attached TDSSeries oscilloscope via an analog multiplexer inside theLogic Analyzer. Because it provides a path for both analogand digital signals, the probe eliminates double-probing andthe associated double-loading of the device signals.Another feature of the iLink™ toolset, iView™measurements, displays the resulting time-correlated digitaland analog waveforms on the logic analyzer screen.

Figure 6-5 shows the TLA Series display that results whenanalog signal A3(3) is aligned onscreen with its digitalequivalent. It is a picture that tells the whole story: at theexact moment of the digital glitch, the analog signal’samplitude is degraded in the area of the logic threshold. Itapparently dips below the threshold voltage for an instant,creating a momentary “low,” or logic 0 level. Then itincreases just enough to cross above the threshold andreturn to the “high” or logic 1 level before switching to logic0 again at the cycle boundary.

This analog behavior is the origin of the glitch, and for theerror in the hexadecimal output on the bus. The instability issuch that it does not affect every falling edge the sameway; many pulses pass without errors. Of course, it will benecessary to review the design models determine when thevalid edge should occur; before or after the unstable portionof the waveform in this bus cycle.

Figure 6-4. The logic analyzer’s MagniVuTM acquisition display reveals a glitch in the A3(3) signal



The experienced engineer will recognize clues in thisdistorted waveform. A degraded logic level such as this isusually the result of a reflection coming back from animproperly terminated transmission line. In the case of ourmotherboard, the signal’s fast edges encountered a missingtermination resistor at the signal’s destination. The result isan erratic but damaging erosion of the falling edge.

To summarize, troubleshooting with the logicanalyzer/oscilloscope combination is a matter of proceedingfrom a high-level, global view to a zoomed-in closeup ofindividual signals using the four signal formats available onan instrument equipped with the iLink™ toolset:

— The bus waveform gives an at-a-glance indication ofproblems occurring somewhere on the bus.

— The deep timing waveform reveals exactly which signalline is involved.

— The high-resolution MagniVu™ timing waveformpinpoints the time placement of the error to a resolutionof 125 ps.

— The analog waveform, provided by the DSO connectedvia the iCapture™ multiplexer and the iLink™ toolset,captures the specific analog characteristics of the signal,revealing potential causes.

Figure 6-5. iViewTM measurements show the analog behavior underlying the digital glitch on A3(3)



A Shortcut that Detects Signal IntegrityProblems Quickly

There is an additional troubleshooting tool available to logicanalyzers equipped with the iLink™ toolset: iVerify™analysis, which bring analog eye diagram analysis to thelogic analyzer screen.

The eye diagram is a visual tool to observe the data validwindow and general signal integrity on clocked buses. It isa required compliance testing tool for many of today’sbuses, particularly serial types, but any signal line can beviewed as an eye diagram.

iVerify™ analysis speeds troubleshooting by incorporatingup to hundreds of eye diagrams into one view thatencompasses the leading and trailing edges of bothpositive-going and negative-going pulses.

Figure 6-6 depicts the result. Here, 12 (twelve) signals—theentire A3 and A2 buses—are superimposed. The benefit of“twelve at once” is clear—And is easy extended in a worldof 32-bit and 64-bit buses, every shortcut helps. Any groupof signals currently connected to the P6980 probe can beselected.

Because an eye diagram presents all possible logictransitions in a single view, it can also provide a fastassessment of a signal’s health. It reveals analog problemssuch as slow risetimes, transients, attenuated levels, andmore. Some engineers start their evaluation by looking atfirst at the eye diagrams, then track down any aberrations.

Figure 6-6. iVerify™ analysis uses the eye diagram format to display multiply signals at once.


The eye in Figure 6-6 reveals an anomaly in the signal—athin blue line whose blue color indicates a relativelyinfrequent transition. Yet it proves that at least one of thetwelve signals has an edge that is outside the normal range.A mask feature helps locate the specific signal causing theproblem. By drawing the mask in such a way that theoffending edge penetrates the mask area, the relevantsignal can be isolated, highlighted and brought to the frontlayer of the image. The result is shown in Figure 6-7, inwhich the flawed signal has been brought to the front andhighlighted in white.

In this example the aberrant edge indicates a problem onthe A3 (0) signal. The origin of the problem is crosstalk—theedge change is being induced by signals on an adjacenttrace on the motherboard.

Conclusion

The functional verification and troubleshooting phase of theserver motherboard project has detected and resolvedseveral signal integrity-related problems. The logic analyzeris the first line of defense when testing digital functionality.However, digital problems can stem from analog signalissues, including edge degradation due to impropertermination or crosstalk as demonstrated here. By teamingthe logic analyzer with an oscilloscope and evaluating time-correlated digital and analog signals on the same screen,problems affecting either domain are easy to solve.

With its full digital feature set verified, the servermotherboard is ready to move on to its final complianceand interoperability tests.


Figure 6-7. The iVerifyTM analysis tool brings the errant waveform to the front and highlights it for easy evaluation.



iLink™ Toolset: Two PowerfulMeasurement Tools Team Up

Although Logic Analyzers and oscilloscopes have longbeen the tools of choice for digital troubleshooting, notevery designer has seen the dramatic benefits thatcome with integrating these two key instruments.

Logic Analyzers speed up debugging and verificationby wading through the digital information stream totrigger on circuit faults and capture related events.Oscilloscopes peer behind digital timing diagrams andshow the raw analog waveforms, quickly revealingsignal integrity problems.

Several Tektronix Logic Analyzer models offer theiLink™ toolset, a Logic Analyzer/oscilloscopeintegration package that is unique in the industry. TheiLink™ toolset joins the power of Tektronix TLA SeriesLogic Analyzers—memory depths to 256, MagniVu™acquisition with 125 ps resolution and advanced statemachine-based triggering—to selected TDS Seriesoscilloscope models.

A powerful set of iLink™ toolset features brings time-correlated digital and analog signals to the logicanalyzer display. While the Logic Analyzer acquires anddisplays a signal in digital form, the attached TDSSeries oscilloscope captures the same signal in itsanalog form and displays it on the Logic Analyzerscreen. Seeing these two views simultaneously makesit easy to see, for example, how a timing problem inthe digital domain was a result of a glitch in the analogrealm.

The iLink™ Toolset is a comprehensive packagedesigned to speed problem detection andtroubleshooting:

— iCapture™ multiplexing provides simultaneous digitaland analog acquisition through a single logicanalyzer probe

— iView™ display delivers time-correlated, integratedlogic analyzer and oscilloscope measurements onthe logic analyzer display

— iVerify™ analysis offers multi-channel bus analysisand validation testing using oscilloscope-generatedeye diagrams



External Bus ComplianceCritical Measurements Support FinalPass/Fail Testing

We have gone to great lengths to prevent signal integrityproblems on the motherboard where possible, and solvethem where necessary. Now it is time to ensure that themotherboard’s “deliverables”—valid signals for externalsubsystems—are compliant with standards. Notsurprisingly, some of the recommended compliancemeasurements are in effect tests for signal integrity.

The motherboard’s 10 Gigabit Ethernet (10 GbE) opticaloutput is one of its most prominent high-speed serialfeatures. The port is a XENPAK module that transfers datafrom a XAUI bus carrying four differential 3.125 Gb/s signals(one quad in each direction). Looking at the transmitterside, the XENPAK module converts the XAUI electricalsignals received from the I/O Controller Hub (IOCH) to anoptical 10GbE signal for transmission. The specific opticalunit used in our design is a commercially-purchasedmodule that mates to a standard receptacle on themotherboard. The module is designed to meet the IEEE802.3ae standard for 10 GbE standard.

Compliance tests range from relatively simple loopback

exercises to thorough eye diagram analysis and specialized

parametric measurements. The more demanding,

oscilloscope-based eye measurement offer some

challenges not seen earlier in the development process.

Most importantly, data rates may exceed the bandwidth

limits of real-time oscilloscopes and their automated

compliance tools. The best solution for signal integrity and

eye diagram analysis in this situation is a full-featured

sampling oscilloscope such as the Tektronix CSA8200 or

TDS8200.

Self-Test Methods Depend on Reliable Signals

Loopback tests are a form of self-test employed by manytypes of external buses, notably 10 GbE. The loopbackmethod is simple: send a specific known data pattern outthrough the transmitter, physically connect the transmitteroutput back to the receiver input, and ensure that thereceiver is capturing the same information that was sent. Itmay be necessary to include an optical attenuator in theloop to reduce the signal level coming into the receiver or toadd “stress” to the test. The setup, including the attenuator,is depicted in Figure 7-1.

10 GbEAttenuator

Transmit Receive


TroubleshootingSystem Verification & Characterization




Characterization

Figure 7-1. The loopback test uses its own transmitted data toanalyze receiver performance. Note the attenuator onthe Receive side. Some receivers cannot directly acceptthe levels sent by their own transmitters, therefore theattenuator steps down the level as needed.



The intelligence to generate and compare the pattern maybe built into the bus module, the IOCH, or even the CPUitself. Many digital system manufacturers are choosing thelatter approach, since it permits the most comprehensivepatterns as well as the most “automated” loopback testing.

The loopback approach is widely accepted for receivertesting. It eliminates the need for costly bit error rate testers(BERTs) and associated tools, while providing results thatcorrelate well with real-world operations.

Like most self-tests on this type of equipment, loopbacktests start with the assumption that the transmitter is ableto provide the correct signals. Unless the transmitter sectionhas been thoroughly evaluated for functionality andcompliance, it may have signal integrity problems of itsown. Unfortunately these may be overlooked due to theshort loopback connection. Yet they can cause failures inthe system environment.

Consequently, loopback receiver testing may bemeaningless unless it starts from the vantage point of a“known-good” transmitter. Oscilloscope-basedmeasurements are a proven method to evaluate transmitterperformance and signal integrity.

Transmitter Tests Lay the Foundation

The IEEE 802.3ae standard specifies a host of compliancemeasurements, including eye diagram tests and quantitativemeasurements on key power parameters. There are severalsteps in the compliance test but for the sake of clarity wewill examine one crucial measurement known as OpticalModulation Amplitude to show how the procedure can becompleted quickly and easily. Once the compliance step isdone, the loopback tests can be performed confidently inthe knowledge that the transmitter is sending valid signals.

Optical Modulation Amplitude is Typical of 10GbE Transmitter Measurements

Most designers of high-bandwidth Ethernet equipment areaccustomed to measuring two critical entities forcompliance: Extinction Ratio and Average Optical Power(AOP). 10 GbE introduces a new measurement term,Optical Modulation Amplitude (OMA), that supplants AOPand supplements Extinction Ratio. Both AOP and OMA areexpressed in dBm, that is decibels relative to 1mW. Theabsolute OMA value is simply the High (Binary 1) powerlevel minus the Low (Binary 0) power level on a squarewave signal. The formula for OMA expressed in dBm is asfollows:

There are two methods for deriving the OMA parameter.The first is a “recommended” approach that is actually thebinding requirement of the standard. The second is an“approximate” method that is useful for estimation but doesnot fully satisfy the standard. The approximate method isused when it is necessary to determine OMA in thepresence of live traffic.

But live traffic is not a problem during the design process,and our motherboard must be proven compliant with theIEEE 802.3ae standard. Therefore we will pursue therecommended approach for the OMA measurement.

OMAdBm

= 10 log( )High–Low

1mW

The measurement solution for this application will be aCSA8200 sampling oscilloscope equipped with an 80C08Coptical module. The module includes the built-in clockrecovery capability required for the 10 GbE environment.The pairing of the sampling mainframe with the 80C08Cmodule enables key 10 GbE compliance tests to beperformed automatically (there are also comparablesampling modules designed for purely electrical standards,and for standards encompassing both optical and electricalfunctionalities. Connecting the optical signal to the DUT isvery simple: a conventional patch cable connects theoscilloscope’s optical input to the output of the XENPAKmodule.

Following the Standard

The IEEE 802.3ae standard puts forth some very specificguidelines for the OMA measurement. It requires a squarewave signal of a frequency ranging from one-fourth to one-eleventh the bit rate of the 10 GbE signal. This isaccomplished by concatenating from four to elevenconsecutive ones followed by the same number ofconsecutive zeros. To ensure the most reliable clock

recovery, the one-fourth frequency is recommended. Asexplained earlier, the capability to generate a signal with theappropriate duty cycle and frequency is often embedded inthe output module itself, or within the firmware supportingeither the I/O Control Hub (IOCH) or the CPU. If no suchprovisions are made, it will be necessary to manuallyprogram the IOCH to create the signal; or the “approximatemethod” (explained below) may be used. This alternativemethod works with the eye diagram of any data or randompattern.

Figure 7-2 is adapted from the IEEE 802.3ae specification.It illustrates the exact measurement points for the OMAparameter using the recommended measurement method.Just one cycle iteration is shown here, although the signal iscontinuous. Essentially, the power (amplitude) is capturedduring the middle 20% portion of the four consecutive highand the four consecutive low binary states. This should bethe most stable portion of the power waveform.



Figure 7-2. OMA measurement requirements, as shown in the IEEE802.3ae specification.

Figure 7-3. Results of OMA measurement. This screen depicts apassing, compliant waveform.


With the CSA8200, the OMA test itself is a matter ofselecting the OMA measurement from a menu and pressingone button. The oscilloscope takes care of the clockrecovery, positions the measurement windows, acquires theinstantaneous power values, and displays the result as aquantitative figure. To place the measurement windows, theoscilloscope first finds the midpoint of the positive-goingand negative-going edges to determine the actual pulseand cycle width. Then, knowing that the signal is a squarewave, the instrument centers the windows accordingly.

The outcome of the acquisition taken from ourmotherboard’s XENPAK 10 GbE module is shown in Figure7-3. Note that the screen layout is effectively the same asthat depicted in the standard, though more cycles areshown. The display makes it easy to confirm that themeasurement occurred during the middle 20% of the topand bottom of the pulse sequence for four consecutive 1sby four consecutive Os, as specified.

The OMA measurement is the first step toward proving thatthe 10 GbE transmitter is compliant with the standard andfree of signal integrity problems. Subsequent mask tests willproduce information about the signal’s noise, jitter,aberrations, and rise/fall time. If these values are compliant,then the transmitter is for our purposes a “known-good”element. Now the loopback test can be performed with theassurance that any errors that may appear are arising fromthe receiver.


An “Approximate” Method for Estimating OMA

The IEEE 802.3ae specification offers an alternative means of measuring OMA. It is intended to provide a useableapproximation when the square wave pattern isnotavailable, and it allows the OMA measurement to beperformed even when traffic is present. For engineers who feel the square-wave pattern is not representative of real-world operating conditions, this “approximate”approach can be used to confirm results derived usingthe recommended method.

The CSA8200 oscilloscope runs the eye diagram inFigure 7-4 automatically when invoked from the frontpanel. It determines the High and Low levels by derivingthe mean value of the histograms at the top andbottom, respectively, of the eye diagram—directly aboveand below the crossing point rather than in the center20%. From this information it calculates the appropriatemeasurement points and captures an OMA value. Usingthe eye diagram crossing point in this way is veryunusual in the field of eye diagram analysis, but theresults are very close to those achieved with therecommended (offline) measurement method.

Figure 7-4. OMA measurement using the “approximate”method. This approach allows testing in thepresence of live traffic but does not qualify as a fullcompliance test.



CharacterizationDefining and Specifying the Final Product

The motherboard is complete, verified for compliance andfunctionality. Problems arising from signal integrity and otherissues have been tracked down and resolved but moreimportantly, many potential problems have been forestalledby a thorough test plan that began with the raw PCB.

The final step is to characterize the product and determineits performance margins, limits, and tolerances. Theinformation becomes the basis of data sheets andpromotional materials.

In many cases these parameters must be tested over arange of temperature, humidity, altitude, vibration, andmore. Power consumption is usually considered, andbattery life is a factor in many types of products. Thedevice’s resistance to electromagnetic interference (EMI), as well as its own tendency to radiate EMI, must beevaluated and documented.

Much of the same equipment used in the earlier designprocess steps—real-time and sampling oscilloscopes, high-bandwidth probes, and specialized measurement and analysis software—is used to explore the limits of our finished product, the motherboard. By this point in the process, signal integrity problems should not be anissue unless external effects (loading, EMI, and so forth)cause deviations.

Characterization may include detailed stress testing. In this process, the device is subjected to variations in supply voltage, for example, to evaluate its ability tofunction normally under less-than-ideal circumstances.Another approach is to drive deliberately flawed signals into the input. Impairments may include marginalamplitudes, slow risetimes, and aberrations such asovershoot. An arbitrary waveform generator (AWG) such as the Tektronix AWG710B is the preferred tool to producethese symptoms.


TroubleshootingSystem Verification & Characterization




Characterization


Specifications for the Designer and for the End-User

Most high-performance electronic products have twospecification levels:

— Published specifications guaranteed to the end-user.These appear in the product manuals, brochures, etc. A device such as the motherboard, whose functionalconnections to other equipment must comply withindustry standards, will have a set of specificationsaffirming that compliance. There may be additionalparameters such as clock frequencies that haveconcretely specified values and tolerances.

— Non-Published specifications intended to support thedesign process and provide guardbands above thepublished specifications. Guardbands are margins thatensure normal production units will fall within thepublished specifications.

Both sets of specifications are usually summarized in an Engineering Specification that acts as a guidelinethroughout the development project. A final round ofmeasurements can confirm that the full range ofspecifications, both published and non-published, havebeen met. Depending on the type of device involved, these measurements might include parameters such assetup-and-hold and other timing tolerances; pulseamplitudes and risetimes; clock frequency stability; noisecharacteristics; jitter; certain impedance limits, and more. All of these measurements are well within the capability of the instruments already discussed in this primer.




Summary and ConclusionOver the course of the design process for the motherboard,we have relied on critical measurements to evaluatecomponents, to detect and solve signal integrity-relatedproblems, and to perform compliance tests. We have usedan array of measurement tools and procedures:

Pre-Assembly Verification

— Impedance Measurements: Used the samplingoscilloscope with TDR module to check the impedancesof PCB traces and connectors, eventually concludingthat a proposed low-cost connector might cause signalintegrity problems in the final design.

— ASIC Verification: Used the sampling oscilloscope anddigital timing generator (signal source) to verify prototypeASICs and confirm that specifications such asSetup/Hold timing are within tolerances.

Functional Verification and Troubleshooting

— Basic Functional Verification: Used the real-timeoscilloscope and high-speed SMA probing tools tocheck the board’s clock signals for aberration-freeperformance; detected and analyzed a signal integrityissue (a glitch) in the spread-spectrum clock.

— Internal Bus Compliance: Used the real-time oscilloscopewith automated eye diagram analysis software toperform internal compliance tests on Serial ATA andother on-board buses.

— Operational Validation, Fault Detection, Debug: Used alogic analyzer to monitor functional tests to verify thatlogic operations proceed correctly; detected a signalintegrity problem using the real-time oscilloscopeconnected to the logic analyzer utilizing the iLink™toolset.

System Verification and Characterization

— External Bus Compliance: Used a sampling oscilloscopeand optical acquisition module to verify signal integrity on10 GbE transmitter signals prior to eye diagramcompliance testing.

— Characterization: Described the use of real-time andsampling oscilloscopes to characterize performancelimits, define margins, and generate information forpublication.

In this primer, we have demonstrated the importance ofbeing alert for signal integrity problems during the designprocess. Glitches, anomalies, and impairments can emergeat virtually any point along the way, and must be eliminatedbefore proceeding to the next step. We have shown howsignal integrity problems can be quickly solved with the aidof automated acquisition and analysis tools in conjunctionwith state-of-the-art Oscilloscopes, Logic Analyzers, andSignal Sources.

38

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Copyright © 2004, Tektronix, Inc. All rights reserved. Tektronix products are covered by U.S. and foreignpatents, issued and pending. Information in this publication supersedes that in all previously publishedmaterial. Specification and price change privileges reserved. TEKTRONIX and TEK are registeredtrademarks of Tektronix, Inc. All other trade names referenced are the service marks, trademarks orregistered trademarks of their respective companies.11/04 DOR/WOW 55W-17671-0

For Further InformationTektronix maintains a comprehensive, constantly expanding collection ofapplication notes, technical briefs and other resources to help engineersworking on the cutting edge of technology. Please visit www.tektronix.com

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