timing diagram
TRANSCRIPT
![Page 1: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/1.jpg)
TIMING DIAGRAM
Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a graphical format. The execution time is represented in T-states.
Instruction Cycle: The time required to execute an instruction is called
instruction cycle.
Machine Cycle: The time required to access the memory or input/output
devices is called machine cycle.
T-State: The machine cycle and instruction cycle takes
multiple clock periods. A portion of an operation carried out in one system
clock period is called as T-state.
![Page 2: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/2.jpg)
INSTRUCTION CYCLE Instruction Cycle
M1 M2 M3 M4 M5
T1 T2 T3 T4 T5 T6
Mn –Machine Cycle
Tn –T State
![Page 3: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/3.jpg)
MACHINE CYCLES OF 8085
The 8085 microprocessor has 5 (seven) basic machine cycles. They are Opcode fetch cycle (4T) Oprand fetch Cycle(3T) Memory read cycle (3 T) Memory write cycle (3 T) I/O read cycle (3 T) I/O write cycle (3 T) Interrupt acknoledge cycle Idle machine cycle
![Page 4: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/4.jpg)
OPCODE FETCH MACHINE CYCLE OF 8085 Each instruction of the processor has one byte opcode. The opcodes are stored in memory. So, the
processor executes the opcode fetch machine cycle to fetch the opcode from memory.
Hence, every instruction starts with opcode fetch machine cycle.
The time taken by the processor to execute the opcode fetch cycle is 4T.
In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor.
![Page 5: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/5.jpg)
EXAMPLE: INSTRUCTION FETCH OPERATION
![Page 6: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/6.jpg)
OPCODE FETCH MACHINE CYCLE OF 8085
Instruction (opcode) reaches the instruction decoder now !
It takes four clock cycles to get one instruction into the CPU.
![Page 7: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/7.jpg)
STATUS SIGNAL
Machine Cycle
IO/ M
S1 S2
Opcade fetch 0 1 1
Memory read 0 1 0
Memory write
0 0 1
I/O read 1 1 0
I/O write 1 0 1
Interrupt Acknowledge
1 1 1
Bus Ideal 0 0 0
![Page 8: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/8.jpg)
INSTRUCTIONS THAT REQUIRE T5 , T6 STATE
Instruction Operation performed
CALL Stack pointer is decremented by 1
CALL conditionalPUSH RP
Stack pointer is decremented by 1
DCX RP Regester pair decremented by 1
INX RP Regester pair incremented by 1
PCHL HL pair trancfered to PC
SPHL HL pair trancfered to SP
RET conditional The condition of flags checked
![Page 9: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/9.jpg)
MEMORY READ MACHINE CYCLE OF 8085 The memory read machine cycle is
executed by the processor to read a data byte from memory.
The processor takes 3T states to execute this cycle.
The instructions which have more than one byte word size will use the machine cycle after the opcode fetch machine cycle.
![Page 10: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/10.jpg)
MEMORY READ/OPERAND FETCH MACHINE CYCLE OF 8085
![Page 11: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/11.jpg)
MEMORY WRITE MACHINE CYCLE OF 8085
The memory write machine cycle is executed by the processor to write a data byte in a memory location.
The processor takes, 3T states to execute this machine cycle.
![Page 12: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/12.jpg)
MEMORY WRITE MACHINE CYCLE OF 8085
![Page 13: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/13.jpg)
I/O READ CYCLE OF 8085 The I/O Read cycle is executed by the
processor to read a data byte from I/O port or from the peripheral, which is I/O, mapped in the system.
The processor takes 3T states to execute this machine cycle.
The IN instruction uses this machine cycle during the execution.
![Page 14: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/14.jpg)
I/O READ CYCLE OF 8085
![Page 15: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/15.jpg)
I/O WRITE CYCLE OF 8085
![Page 16: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/16.jpg)
TIMING DIAGRAM OF MOV R1,R2
![Page 17: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/17.jpg)
INSTRUCTIONS HAVING SIMILAR TIMING DIAGRAM
ALL MOV R1,R2 ALL ADD R
ALL ADC R CMA,CMC,STC
ALL CMP R ALL INR R
ALL DCR R ALL ORA R,ANA R,XRA R
ALL ROTATE INSTRUCTIONS
ALL SUB R
ALL SBB R RIM,SIM
DAA EI,DI
NOP XCHG
![Page 18: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/18.jpg)
TIMING DIAGRAM OF MVI A,32 H
![Page 19: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/19.jpg)
19
Execution of an Instruction
Put the first memory location on the address bus (2000 h)
![Page 20: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/20.jpg)
20
Execution of an Instruction
Get the instruction (opcode) byte from memory
![Page 21: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/21.jpg)
21
Execution of an Instruction
Interpret the instruction:
Wait for the data byte !
![Page 22: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/22.jpg)
22
Execution of an Instruction
Put the next memory location on the address bus (2001 h)
![Page 23: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/23.jpg)
23
Execution of an Instruction
Get the data byte from the memory
Put into accumulator
![Page 24: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/24.jpg)
24
Execution of an Instruction
How long does it take to execute this two-byte instruction (op-code) ?
It is quite possible to accurately predict the time that is required to run each instruction, and to run the entire program !
![Page 25: Timing Diagram](https://reader038.vdocuments.us/reader038/viewer/2022102422/546ae659b4af9fe2178b4966/html5/thumbnails/25.jpg)
INSTRUCTIONS HAVING SIMILAR TIMING DIAGRAM
ADI DATA ANI DATA
ACI DATA ORI DATA
SUI DATA XRI DATA
SBI DATA MVI R,DATA