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System Simulation 2
Objectives
After completing this module, you will be able to:• Describe the functionality of SimGen• Describe the integration of SimGen within XPS• Describe the simulation process• Describe what SmartModel™ Libraries are and how to use them
System Simulation 4
Simulation Generator
Hardware Platform Generation
Library Generation
Embedded SoftwareDevelopment
ISETools
IP Library or User Repository
MSS
LibGen
.a
Compiler (GCC)
.o
Linker (GCC)
ELF
MHS
PlatGenDrivers,
MDDMPD, PAO
PCoreHDL System and
Wrapper VHDsystem.BMM
Synthesis (XST)
NGC
NGDBuildUCF
NGD
MAP
NCD, PCF
PAR
NCD
BitGensystem.BIT
BitInit
download.BIT
iMPACT
system_BD.BMM
SimGen
BehavioralVHD Model
SimGen
StructuralVHD Model
SimGen
TimingVHD Model
Simulation
IP Models ISE ModelsTestbenchStimulus
CompEDKLib CompXLib
ApplicationSource.c, .h, .s
EDK Tool Flow
download.CMD
EDK SWLibraries
SimGen
• The Simulation Model Generation tool (SimGen) generates and configures various simulation models for the specified hardware
• SimGen will generate simulation models by using a Microprocessor Hardware Specification (MHS) file
• SimGen searches for input files in the following directories located in the project directory – <project_directory>/hdl/
• system_name.[vhd|v]• peripheral_wrapper.[vhd|v]
– <project_directory>/implementation/ (if any of the peripherals are black-box)• peripheral_wrapper.ngc• system_name.ngc• system_name.ncd
SimGen
• SimGen produces• <peripheral_wrapper>.
[vhd|v] ***• <system_name>.[vhd|v]• <system_name>.do• <system_name>_sim.bm
m• <system_name>.sdf **
SimGen Generated Directories
project_directory
simulation directory
<Sim_model>*
* <Sim_model> = behavioral/structural/timing** <system_name>.sdf in timing simulation*** <peripheral_wrapper>.[vhd\v] in behavioral or structural simulation
Memory Initialization• To initialize memory in the
simulation models created by SimGen, you need:– The compiled executable
• executable.elf – The simulation hardware model
generated by executing SimGen• system.vhd or system.v
– The BMM file generated by PlatGen • <project_directory>/implementation directory
• Data2MEM uses these files and generates a system_init.vhd file that contains block memory initialization content
Data2MEM
system_init.[vhd|v]
system.bmm executable.elf
system.[vhd|v]
System Simulation 8
Memory Initialization
• The system.bmm file is created by the PlatGen tool and carries block memory related information (see next slide)– Number of block memories– Address range for each set of block memory– Data indexing for each block memory in a set
• The executable.elf file is generated by the compiler and carries data variables and code
• The system.vhd file is generated by the SimGen tool and carries a hardware model of the system
• The Data2MEM program uses the above mentioned files, extracts data code information, and generates a system_init.vhd file that contains block memory initialization content
Simulation Libraries: XILINX• UNISIM library
– Used for behavioral simulation and contains default unit delays– Includes all of the Xilinx Unified Library components that are inferred by most
popular synthesis tools• SIMPRIM library
– Used for structural and timing simulation– Includes all of the Xilinx Primitives Library components that are used by Xilinx
implementation tools• XilinxCoreLib library
– Contains pre-optimized modules to take advantage of architectural resources– Library models are used for behavioral simulation– May be used for your own defined IPs
• Structural and timing simulation models generated by SimGen instantiate the SIMPRIM library components
Simulation Libraries: EDK
• EDK library– Used for behavioral simulation– Contains models of all the EDK IP components– PPC 405 processor models are not available for the ModelSim XE simulator – VHDL and Verilog support– Must be compiled for the target simulator– Compile the EDK library using GUI from XPS (see next slide)
• Library can also be compiled using the following command (Xilinx does not recommend)
• compedklib [ -h ] [ -o output-dir-name ] [ -lp repository-dir-name ] [ -X compxlib-output-dir-name ] [ -E compedklib-output-dir-name ]
System Simulation 12
Compiling Simulation Libraries
• With XPS project open:– Select Project Project Options– Click the HDL and Simulation tab– In the Simulation Libraries Path
area, select the EDK and Xilinx® libraries to compile
– Click Compile
• If XPS project is not open:– Options Compile Simulation
Libraries
Integration within XPS
• Invoke ise project using Project Navigator
• Add system_i.xmp as a source to the project
• Make sure that Sources view is set for Synthesis/Implementation
• Select system_i in Sources window and double-click Manage Processor Design to invoke XPS
Start ISE and XPSStart ISE and XPS1
Integration within XPS
• Specify simulation parameters by selecting Project Project Options– HDL and Simulation tab
• HDL• Simulator Compile Script• Simulation Libraries Path
– EDK Library– XILINX Library
• Simulation Models
Set up library paths using Project Options
Set up library paths using Project Options
2
Integration within XPS
• Generate the simulation models– Generation of
simulation models:Simulation Generate Simulation HDL Files
Generate the Simulation ModelGenerate the Simulation Model3
Use within the Project Navigator
• VHDL– Project New Source VHDL Testbench – Project Add Source; add the testbench to the
project
• Verilog– Project New Source Verilog Test Fixture – Project Add Source, add the testbench to the
project
Create/Add testbench fileCreate/Add testbench file4
Use within the Project Navigator
• VHDL– You must copy over the <project_file>.do simulation file– Testbench.vhd must be added to the .do file– Testbench.vhd must include a configuration statement to load the RAM
initialization strings included in <project_file>_init.vhd
• Verilog– You must copy over the <project_file>.do simulation file– Testbench.v must be added to the .do file– Testbench.v must include a #include statement to load the RAM
initialization strings included in <project_file>_init.v
• Alternatively, write your own .do script
Copy .do files to theProjNav directory
Copy .do files to theProjNav directory
5
System Simulation 19
Invoking ModelSim Simulator
• In Sources for window, select Behavioral Simulation view
• In Sources window, select testbench
• In Processes window, double-click on Simulate Behavioral Model
Run ModelSim SimulatorRun ModelSim Simulator6
System Simulation 21
SmartModel Libraries
• SmartModel Libraries are compiled simulation models that represent integrated circuits and system buses as black boxes.
• SmartModel Libraries: – Accept an input stimulus and respond with an appropriate output behavior– Provide improved performance over gate-level models– Protect proprietary designs– Can be used with any simulation tool that supports the SWIFT™ Interface
System Simulation 23
Running a Simulation Using SmartModels
• The SWIFT interface provides access to SmartModel Libraries• Changes required in the modelsim.ini:
– Resolution = ps– Comment out the "PathSeparator" = / using “;”– Veriuser = $MODEL_TECH/libswiftpli.dll (SWIFT Interface) – Uncomment the following lines for the appropriate OS
• libsm = $MODEL_TECH/libsm.dll• libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
• set MODELSIM=<path_to_modelsim.ini_script>\modelsim.ini• Instantiate the appropriate MGT or PowerPC processor
primitive
System Simulation 24
Supported Simulators and Platforms
• Solaris Operating System (2.8, 2.9)– Mentor Graphics ModelSim SE simulator (6.0 and newer)– Cadence NC-Verilog simulator– Cadence Verilog-XL simulator– Synopsys VCS simulator
• Windows 2000 (SP2) or Windows XP– Mentor Graphics ModelSim SE simulator (6.0 and newer)
• Linux (7.2)– Mentor Graphics ModelSim SE simulator (6.0 and newer)
System Simulation 25
Solution Records
• 14597: 6.1i/5.2i/5.1i SmartModel/SWIFT Interface - How do I use the MGT and PPC SmartModels in NC-Verilog, Verilog-XL, and Synopsys VCS?
• 14019: 6.1i/5.2i/5.1i SmartModel/SWIFT Interface - How do I use the MGT and PPC SmartModels in ModelSim?
• 14181: Virtex-II Pro - What are the SWIFT Interface, Smart Model, VMC, and VhMC? What of these does Xilinx deliver?
• 14596: 6.1i SmartModels - What simulators support SmartModel simulation?
• 14365: Virtex-II Pro PowerPC - What is the difference between Bus Functional Model (BFM) and Smart Model (SWIFT interface) simulation?
System Simulation 27
Review Question
• Which three items are required to initialize memory in the simulation models created by SimGen?
System Simulation 28
Answer
• Which three items are required to initialize memory in the simulation models created by SimGen?– The compiled executable generated with the
appropriate gcc compiler or assembler, from corresponding C or assembly source code
– The simulation model generated by executing SimGen– The BMM file generated by PlatGen