thesis outline - uic engineeringajohar/thesis outline.pdf · 12/16/02 ©amanjyot singh johar, msrc,...

12/16/02©Amanjyot Singh Johar, MSRC, Department of Electrical and Computer

EngineeringUniversity of Illinois at Chicago

Thesis Outline

Charge Pump based monolithic DC-DC converter with adaptive controller for battery powered micro-electronic devices



Value Proposition

Oscillator-less design for dynamic switching regulation Unique start-up circuitry to ensure a faster responseNovel mixed signal design as opposed to conventional analog circuits



Targeted Applications

Battery powered micro-electronic devicesn Wireless communication devicesn Portable computing devicesn Medical electronic devicesGeneral purpose auxiliary power supplies in products requiring multiple voltage levels



Targeted Specifications

Input Voltage 1.5V to 2.2VOutput Voltage 2.5V to 3.2VOutput Current 40-100mATargeted Efficiency 90%Switching Frequency > 1 MHzTunable Output VoltageFly Capacitance 8uFLoad Capacitance 15uF



Technology Summary

Inductor-less design leads to lower noiseHigher efficiency due to single stage operationTightly regulated output voltage from an available battery sourceSmaller size and lower cost



Charge Pump Circuit

VbattCfly

Rlo

ad

Cloa

d

S1S2

S3

S4

Vcfly Vcload

Control SignalsController

Circuit



Main Functional BlocksSwitching MatrixBand-gap Voltage ReferenceHigh Resolution ComparatorMultiplexer2 bit ADCProgrammable Logic ArrayFinite State Machine based Timing GeneratorsOperational AmplifiersStart-up Circuit Buffers and Inverters



Control Circuit Structure

Oscillator-less control logicn Saves battery power when device is non

operationaln No EMI due to the oscillator

Dynamic response towards charging and discharging of fly and load capacitorsStart-up from low input voltagesControlled delays to avoid unnecessary switching



Controller Circuit Design

ADC Reference Selector

Vout

Vref1

Vref2

Vref1

Vref2

Vcfly

Comparator

Comparator

Timing Generator Switching Signals

S0

S1

User Inputs

Choice of Reference Voltages



Timing Generator

S0 = 0

S1 = 0

S0 = 1

S1 = 1

S0 = 0

S1 = 1

S0 = 1

S1 = 0

A

DC

B

S1 = 1

S1 = 0

S1 = 1

S1 = 0

S0 =

1

S0 =

0

S0 =

1

S0 =

0

•Timing Generator modeled as a 4 state Finite State Machine

•Changes in input to the machine are modeled as changes in the state of the machine

•No oscillator based component required for the control

•Circuit state sensed automatically and control signals generated



Comparison

Prior Artn Oscillator Based controln Switching frequencies of

100-250 KHzn Low voltage operation

disabledn Huge Capacitor sizes

required (220uF to 2200uF)

n Efficiency = 60-70%

Proposed Model (Mirage)n No oscillator required for

controln State based control of

switchingn Switching frequency

anticipated > 1MHzn Capable of starting up at

low voltagesn Smaller capacitors

required (8uF and 15uF)n Efficiency >80%



Improvement

Q-chipn Operating Frequency

= 4KHzn Huge Capacitors ~

20uF and 200uF n Oscillator-less control

based on comparator logic

Miragen Operating Frequency

anticipated > 1MHzn Smaller Capacitors ~

8uF and 15uFn Oscillator-less control

based on the finite state of the system

n User programmable variable output voltage



Parallel Operation

Vbatt

Cfly

Rlo

adC

loa

d

S1S2

S3

S4

Vcfly Vcload

Control SignalsController Circuit

Cfly

Rlo

adC

loa

d

S1S2

S3

S4

Vcfly Vcload

Control SignalsController Circuit

thesis outline - uic engineeringajohar/thesis outline.pdf · 12/16/02 ©amanjyot singh johar, msrc,...

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