thesis draft

DESIGN OF LOADLESS 4T-SRAM CELL IN

28 nm FDSOI AND 28 nm BULK

TECHNOLOGY FOR LOW-POWER & LOW-

AREA APPLICATION

A Thesis submitted in partial fulfillment of the requirement for the award of

the degree of

Master Of Technology

in

VLSI System And Technology

By

N SHIVARAM VENKATESH

ELECTRONICS AND COMMUNICATION ENGINEERING

SHIV NADAR UNIVERSITY

DADRI, UTTAR PRADESH-201314

MAY, 2014

Copyright Shiv Nadar University (SNU), Dadri, Uttar Pradesh, 2014

BONAFIDE CERTIFICATE Certified that N Shivaram Venkatesh has been carried out the research work

presented in this thesis entitled Design of Loadless 4T-SRAM Cell in 28 nm

FDSOI and 28 nm Bulk Technology for Low-Power & Low-Area

Application for the award of Master of Technology from Shiv Nadar

University, Uttar Pradesh under my supervision. This work has been carried

out by Student himself/herself and the contents of the thesis do not form the

basis for the award of any other degree to the candidate or to anybody else.

Dr G Naveen Babu

Assistant Professor

Department of Electrical Engineering

Shiv Nadar University

Uttar Pradesh, India

Dr Atul Vir Singh

Assistant Professor

Department of Electrical Engineering

Shiv Nadar University


Mr Bedanta Choudhury

Senior Manager

Department of Technology Research

and Development

STMicroelectronics


DECLARATION BY THE SCHOLAR

I hereby declare that the work reported in the Master of Technology thesis entitled

Design of Loadless 4T-SRAM Cell in 28 nm FDSOI and 28 nm Bulk

Technology for Low-Power & Low-Area Application submitted at Shiv

Nadar University, Dadri, Uttar Pradesh, is an authentic record of my work

carried out under the supervision of Dr. G Naveen Babu and Dr. Atul Vir

Singh. I have not submitted this work elsewhere for any other degree or diploma. I am

fully responsible for the contents of my thesis.

(Signature of Scholar)

N Shivaram Venkatesh

Department of Electronics & Communication Engineering

Shiv Nadar University, Uttar Pradesh

09-May-2014

I

ACKNOWLEDGEMENTS

Foremost, I would like to thank my mentors and supervisors, Mr. Bedanta Choudhury

at STMicroelectronics. and Dr. G Naveen Babu and Dr. Atul Vir Singh at Shiv Nadar

University, without whom I would not have done my thesis.

Dr. G Naveen Babu and Dr. Atul Vir Singh not only supervised my thesis, they agreed

to do so from Shiv Nadar University while I was in STMicroelectronics for the entire duration

of my work. I would like to thank them for being patient, having faith in me and providing me

with vital guidance all the time. Mr. Bedanta Choudhury shared a lot of his expertise and

insight with me refusing to accept anything less than the best I could do. His enthusiasm and

inspiration was always there when I needed it.

I wish to thank Mr. A Lourts Deepak and Mr. Vaibhav Anand Srivastava of

STMicroelectronics for patiently answering all my questions and for the endless discussions

which helped me out of many a tight-spot I encountered while working on this thesis.

I am tempted to individually thank all of my friends, but the list will be too long and

from fear of leaving someone out, I will simply say thank you all very much.

I would like to thank STMicroelectronics, Noida for giving for internship in the

organisation. This is great learning experience for me.

I cannot finish without saying how grateful I am thankful to Ms.Kheyali Ghose Roy,

Ms.Aditi Malik and Ms.Swaitlekha Majumdar for making me laugh when I was stressed out

and for the incredible amount of patience they had with me. Lastly and most importantly, I

would like to thank my parents whose faith in me sometimes borders on craziness and without

which I would not be studying for a Masters degree.

DECEMBER, 09 2013.

II

ABSTRACT

The aim of the project is to design an 4T SRAM cell for Low-Power and Low-Area

application while maintaining the competitive performance. The design of the cell is carried

out in Bulk and FDSOI technology. The metrics considered here are Static Noise Margin,

Write Margin, On-Current and Off-Current. The evaluation of the above metrics is carried out

using Cadence and Mentor tools. Firstly, to show the better performance of loadless 4T-

SRAM, a comparison study is done with 6T-SRAM both designed in 28 nm Bulk

Technology. The evaluations are performed on the basis of same metrics for 4T-SRAM and

6T-SRAM. Post the simulation, it is observed that 4T-SRAM is a better solution for the low-

power application in comparison to its counterpart of 6T variant in 28 nm Bulk Technology

variant. Secondly, after the above mentioned work a detailed study on FDSOI technology was

carried out and the 4T-SRAM was designed using FDSOI technology.

Key Words

STATIC RANDOM ACCESS MEMORY (SRAM), SIX-TRANSISTOR (6T-), FOUR TRANSISTOR (4T-), CELL

RATIO (CR), STATIC NOISE MARGIN (SNM), WRITE NOISE MARGIN (WNM), FULLY-DEPLETED

SILICON ON INSULATOR (FDSOI)

III

TABLE OF CONTENTS Page

Number

CHAPTER 1: INTRODUCTION TO MEMORY DESIGN

1.1 INTRODUCTION 1

1.2 CLASSIFICATION OF MEMORY ORGANIZATION 1

CHAPTER 2: RANDOM ACCESS MEMORIES

2.1 BASIC FUNDAMENTALS 5

2.2 DYNAMIC RANDOM ACCESS MEMORY 6

2.3 STATIC RANDOM ACCESS MEMORY 8

CHAPTER 3: DESIGN OF STATIC RANDOM ACCESS MEMORY

3.1 INTRODUCTION 11

3.2 SIX TRANSISTOR (6T)- STATIC RANDOM ACCESS MEMORY 11

3.2.1 READ OPERATION 12

3.2.2 WRITE OPERATION 13

3.3 SIX TRANSISTOR (4T)- STATIC RANDOM ACCESS MEMORY 15

3.3.1 READAND WRITE OPERATION 16

CHAPTER 4: METRICS TO EVALUATE STATIC RANDOM ACCESS

MEMORY

4.1 INTRODUCTION 17

4.2 STATIC NOISE MARGIN 17

4.3 WRITE NOISE MARGIN 18

4.4 ON-CURRENT 19

4.5 OFF-CURRENT 19

4.6 DATA RETENTION VOLTAGE 19

CHAPTER 5: FULLY-DEPLETED SILICON ON INSULATOR DEVICES

5.1 INTRODUCTION 20

5.2 BASIC FEATURES OF FDSOI DEVICES 20

5.3 MODES OF OPERATION: FDSOI DEVICES 22

5.4 CHARACTERISTICS OF FDSOI MOSFETS 25

CHAPTER 6: MATHEMATICAL ANALYSIS OF SRAM CELL

IV

6.1 ANALYTICAL SNM EXPRESSION FOR A 6T SRAM CELL 31

6.2 ANALYTICAL SNM EXPRESSION FOR A LOADLESS 4T SRAM CELL 33

6.3 ANALYTICAL SNM EXPRESSION FOR A PROPOSED LOADLESS 4T

SRAM CELL

35

CHAPTER 7: RESULTS

7.1 SPECTRE SETUP FOR SRAM CELL DESIGNED IN 28 nm BULK

TECHNOLOGY

38

7.2 SPECTRE SETUP FOR SRAM CELL DESIGNED IN 28 nm FDSOI

TECHNOLOGY & SIMULATION GRAPH USING ELDO SIMULATOR

41

7.3 SIMULATED OUTPUT 42

7.3.1 ANALYSIS FOR STATIC NOISE MARGIN FOR PROPOSED 4T-

SRAM DESIGNED IN 28 nm BULK TECHNOLOGY

42

7.3.2 ANALYSIS FOR WRITE NOISE MARGIN FOR PROPOSED 4T-

SRAM DESIGNED IN 28 nm BULK TECHNOLOGY

47

7.3.3 OTHER METRICS ANALYSIS FOR PPROPOSED 4T-SRAM

DESIGNED IN 28 nm BULK TECHNOLOGY

48

7.3.4 ANALYSIS FOR STATIC NOISE MARGIN FOR 6T-SRAM


48

7.3.5 ANALYSIS FOR WRITE NOISE MARGIN FOR 6T-SRAM


49

7.3.6 OTHER METRICS ANALYSIS FOR 6T-SRAM DESIGNED IN 28

nm BULK TECHNOLOGY

50

7.3.7 ANALYSIS FOR STATIC NOISE MARGIN FOR PROPOSED 4T-

SRAM DESIGNED IN 28 nm FDSOI TECHNOLOGY

50

7.3.8 ANALYSIS FOR WRITE NOISE MARGIN FOR PROPOSED 4T-

SRAM DESIGNED IN 28 nm FDSOI TECHNOLOGY

52

7.3.9 OTHER METRICS ANALYSIS FOR PROPOSED 4T-SRAM

DESIGNED IN 28 nm FDSOI TECHNOLOGY

54

7.3.10 ANALYSIS FOR STATIC NOISE MARGIN FOR

CONVENTIONAL 4T-SRAM DESIGNED IN 28 nm FDSOI

TECHNOLOGY

54

7.3.11 ANALYSIS FOR WRITE NOISE MARGIN FOR

CONVENTIONAL 4T-SRAM DESIGNED IN 28 nm FDSOI

55

V

TECHNOLOGY

7.3.12 OTHER METRICS ANALYSIS FOR CONVENTIONAL 4T-SRAM

DESIGNED IN 28 nm FDSOI TECHNOLOGY

56

CONCLUSION 57

FUTURE WORK 58

REFERENCE 59

VI

LIST OF TABLES

TABLE

NUMBER

CAPTIONS PAGE

NUMBER

1.1 CMOS Memory Subclasses 4

7.1 Cell Ratio Modulation, VDC = 1.0 V 42




7.5 Supply Voltage Modulation PD= 120 nm, PG= 120nm and CR=1 44

7.6 Supply Voltage Modulation PD= 180 nm, PG= 120nm and

CR=1.5

45



CR=2.5

46


7.10 Pull-Up Ratio Modulation, VDC = 1.3 V 47

7.11 Supply Voltage Modulation, PD= 120 nm, PG= 120nm and CR=1 47

7.12 On Current and Off-Current of 4T-SRAM 48

7.13 Read Access and Write Access Time of 4T-SRAM 48


7.15 Supply Voltage Modulation PD= 300 nm, PG= 150nm and CR=2

in various Process Corners

49

7.16 Pull-Up Ratio Modulation, VDC = 1.3 V and PD=225 nm 49



7.19 Cell Ratio Modulation, Vdc= 0.8 V 50





VII


7.25 Pull-Up Ratio Modulation, Vdc = 1.0 V 52

7.26 Supply Voltage Modulation, Process Corner = TT 52

7.27 Supply Voltage Modulation, Process Corner = FF 53

7.28 Supply Voltage Modulation, Process Corner = FS 53

7.29 Supply Voltage Modulation, Process Corner = SF 53

7.30 Supply Voltage Modulation, Process Corner = SS 53



7.33 Supply Voltage Modulation, CR=1 54

7.34 Cell Ratio Modulation 55

7.35 Pull-Up Ratio Modulation 55



VIII

LIST OF FIGURES FIGURE

NUMBER CAPTIONS PAGE

NUMBER 1.1 Memory Classification by Technology 2

1.2 Memory Classification by Data Form 2

1.3 Memory Classification by Mechanism 2

1.4 Semiconductor memory technology branches 3

2.1 Basic RAM architecture 5

2.2 64 Mbit Fast Page Mode DRAM Device (4096 x 1024 x 16) 8

2.3 Functional Diagram of SRAM 10

3.1 6T- SRAM Cell 12

3.2 4T- SRAM Cell 15

5.1 Drain junction capacitance of SOI MOSFET 21

5.2 Drain junction capacitance of SOI MOSFET 23

5.3 Cross section of PDSOI MOSFET and its energy band-diagram 23

5.4 Dependence of Body Thickness and Impurity Concentration of

Body in an FDSOI MOSFETs.

25

5.5 Drain current-voltage characteristics of (a) FD-SOI and (b) PD-

SOI nMOSFETs. (From J. P. Colinge, IEEE Press 1998.)

26

5.6 Subthreshold characteristics of FD-SOI, PD-SOI, and bulk-Si

MOSFETs.

27

6.1 A six-transistor full CMOS SRAM cell in a read-accessed mode 31

6.2 Equivalent circuit of a 4T loadless SRAM half-cell 34

6.3 Equivalent circuit of Proposed 4T loadless SRAM half-cell 36

7.1 4T-SRAM Cell Setup in Cadence Vituoso Environment 38

7.2 4T-SRAM Cell : Simulation for SNM Curve 38

7.3 4T-SRAM Cell : Simulation for WNM Curve 39


7.5 6T-SRAM Cell : Simulation for SNM Curve 40

7.6 6T-SRAM Cell : Simulation for WNM Curve 40


IX

designed in 28 nm FDSOI Technology

7.8 Proposed 4T-SRAM Cell Setup in Cadence Vituoso

Environment designed in 28 nm FDSOI Technology

41





7.13 Supply Voltage Modulation, PD= 120 nm, PG= 120nm and

CR=1

44

7.14 Supply Voltage Modulation ,PD= 180 nm, PG= 120nm and

CR=1.5

45


CR=2

45


CR=2.5

46


CR=3

46

7.18 Pull-Up Ratio Modulation, VDC = 1.3 V 47


CR=1

47


CR=2

48


CR=2 in various Process Corners

49

7.22 Pull-Up Ratio Modulation, VDC = 1.3 V and PD=225 nm 50

7.23 Supply Voltage and Cell Ratio Modulation Vs SNM 52

7.24 Supply Voltage and Pull Ratio Modulation Vs WNM 54

7.25 Supply Voltage Modulation, CR=1 55

7.26 Cell Ratio Modulation, Vdc = 1V 55

7.27 Pull-Up Ratio Modulation 56

X

LIST OF ACRONYMS & ABBREVIATIONS

(Alphabetically) BL BIT LINE

BLB BIT LINE BAR

BOX BODY OXIDE

CMOS COMPLIMENTARY MOSFET

CR CELL RATIO

DIBL DRAIN INDUCED BARRIER LOWERING

DRAM DYNAMIC READ ONLY MEMORY

FDSOI FULLY DEPLETED SILICON ON INSULATOR

LSI LARGE SCALE INTEGRATION

PD PULL-DOWN RATIO

PDSOI PARTIALLY DEPLETED SILICON ON INSULATOR

PU PULL-UP RATIO

PVT PROCESS VOLTAGE TEMPERATURE

RPM ROTATION PER MINUTE

SNM STATIC NOISE MARGIN

SOC SYSTEM ON CHIP

SOI SILICON ON INSULATOR

SRAM STATIC RANDOM ACCESS MEMORY

WL WORD LINE

WNM WRITE NOISE MARGIN

6T SIX TRANSISTOR

4T FOUR TRANSISTOR

1

CHAPTER 1 INTRODUCTION TO MEMORY DESIGN

1.1 INTRODUCTION

The semiconductor IC which are much used in humongous quantity are the CMOS memories

and are available with various features in different variants. CMOS memories, in a strict

sense, are all of those data storage devices which are fabricated with a complementary metal-

oxide semiconductor (CMOS) technology. In technical practice, however, the term CMOS

Memory designates a class of data storage devices which are fabricated with CMOS

technology, store and process data in digital form and use no moving mechanical parts to

facilitate memory operations. This specific meaning of the term CMOS Memory results

from the historical development, application and design of semiconductor data storage

devices.

The data storage devices are classified in various aspects, but in general grouped by (1)

fabrication technology of the storage medium, (2) data form, and (3) mechanism of the access

to stored data. From the variety of technologies which may be applied to create data storage

devices, the semiconductor integrated circuit technology, and within that, the CMOS

technology has emerged as the dominant technology in fabrication of system-internal

memories, while magnetic and optical technologies gained supermacy in production of

auxiliary memories for mass data storage[1]. The dominance of the CMOS memories in

computing, data processing and telecommunication system has arisen from the capability of

CMOS technologies to combine high packing density, fast operation, low power

consumption, environmental tolerance and easy down-scaling of feature sizes. This

combination of features provided by CMOS memories has been unmatched by memories of

semiconductor memories, so far, have been cost prohibitive in the majority of commercial

mass data storage devices. Nevertheless, the design of mass storage devices, which operate in

space, military and industrial environments can require the use of CMOS memories, because

of their good environment tolerance [4]-[9].

1.2 CLAASIFICATION OF MEMORY ORGANIZATION

Historically, system requirement in data form, performance, environmental tolerance and

packing density, have dictated the use of digital signals in CMOS memories. With the

evolution of the CMOS memory technology, data storage in digital form has become

dominant and self-evident without any extra statement, and the alternative analog data storage

2

is distinguished by using the expression CMOS analog memory. Similarly, because all

CMOS memories operate without mechanically moving parts, an added word for mechanical

classification would be redundant. A plethora of subclasses indicates the great diversity of

CMOS memories, and includes classification by (1) basic operation mode, (2) storage mode,

(3) data access mode, (4) storage cell operation, (5) storage capacity, (6) organization, (7)

performance, (8) environment tolerance, (9) radiation hardness, (10) read effect, (11)

architecture, (12) logic system, (13) power supply, (14) storage media, (15) application, (16)

system operation and by numerous other facets of the memory technology [2] [14].

Fig 1.1 : Memory Classification by Technology

Fig 1.2 : Memory Classification by Data Form

Fig 1.3 : Memory Classification by Mechanism

3

Fig 1.4 : Semiconductor memory technology branches

The vast majority of CMOS memories are designed to allow write and read and, in a much

less quantity, read-only basic operation modes. In mask-programmed read-only memories the

data contents cannot be reprogrammed by the user. User-programmable memories can also

be, and are, made by comining programmable nonvolatile memory cells with CMOS

fabrication technologies. During the advancement of the memory technology, nevertheless,

user-programmable nonvolatile memories emerged as a separate main class of memory

technology that has its own specific subclasses, circuits and architectures. Therefore, the

circuits and architectures of the user-programmable nonvolatile memories are discussed

independently from the write-read and the mask-programmed read-only CMOS memories

elsewhere in other research works[2]-[14].

In CMOS memory technology the classification by access mode and by storage cell operation

is of importance, because these two categories can incorporate the circuits and architectures of

all other subclasses of CMOS memories. Consistently with the categories, this work provides

a general introduction to the CMOS random access memory architecture and, then, it presents

the dynamic, static and fixed type of memory cells and the other component circuits which are

specific to CMOS memories.

CMOS memory integrated circuits are characterized, most commonly and most superficially,

by memory-capacity per chip in bits and by access time in seconds or by data-repetition rate

in Hetzs[15]-[16], [18].

4

Table 1.1 : CMOS Memory Subclasses

1 Basic Operation Mode Wrire-Read, Read-Only, User Programmable

2 Storage Mode Volatile, Nonvolatile

3 Access Mode Random, Serial, Content-Addressable

4 Storage Cell Operation Dynamic, Static, Fixed, Programmable

5 Storage Capacity Number of Bits or Storage Cells in a Memory Chip

6 Organization (Number of Words) x (Number of Bits in a Word)

7 Performance High Speed, Low-Power, High-Reliability

8 Environmental Tolerance Commercial, Space, Radiation, Military, High-Temperature

9 Radiation Hardness Nonhardened, Tolerant, Hardened

10 Read Effect Destructive, Nondestructive

11 Architecture Linear, Hierarchical

12 Logic System Binary, Ternary, Quaternary, Other

13 Power Supply Stabilized, Battery, Photocell, Other

14 Storage Media Semiconductor, Dielectric, Ferroelectric, Magnetic

15 Application Mainframe, Cash, Buffer, Scratch-Pad, Auxiliary

16 System Operation Synchronous, Asynchronous

5

CHAPTER 2 : RANDOM ACCESS MEMORIES

2.1 BASIC FUNDAMENTALS

In random access memories the memory cells are identified by addresses, and the access to

any memory cells any address requires approximately the same period of time. A basic

CMOS random access memory (RAM) consists of a (1) memory cell array, or matrix, or core,

(2) sensing and writing circuit, (3) row, or word address decoder, (4) column, or bit address

decoder, and an (5) operation control circuit.

Fig 2.1 : Basic RAM architecture

Generally, the operation of a write-read RAM may be divide into three major segments : (1)

access, (2) read/write, and (3) input/output [3]. The access segment starts with the appearance

of an address code on the inputs of the decoders. The N-in/2N out row decoder selects a

single wordline out of the 2N

wordlines of the memory-cell array. In an array of 2N

x 2N

memory cells, this wordlines renders the data input/output terminals of 2N

cells to 2N

bitlines

and an N-in/2N out column decoder selects S number of bitlines. S is also the number of the

sense and write amplifier, and S may be between one and 2N. In the second read/write

operation segment, the sense and write amplifiers read, rewrite or alter the data content of the

6

selected memory cells [5]. During the input/output time segment, the sensed or altered data

content of the memory cells are transferred through datalines to logic circuits, and to one or

more output buffer circuits. The output buffer is either combined or seperated from the input

buffer [6]. A data input is timed so that the write data reaches the sense and write amplifiers

before the sense operation commenses. Of courses, no write can be performed in read-only

memories. Every memory operation, e.g., write, read, standby, enable, data-in, data-out, etc.,

is goverened by RAM internal control circuits.

Most frequently, CMOS RAMs are categorized by the operation of the storage cells into four

categories : (1) dynamic RAMs (DRAMs), (2) static RAMs (SRAMs), (3) fixed program or

mask-programmed read-only memories (ROMs), and (4) user-programmable read-only

memories (PROMs). The following sections introduce the architecture of CMOS DRAMs,

SRAMs, and ROMs. CMOS PROM architectures are not discussed here, as stated

beforehand, because PROMs have emerged as a distinct and extensive class of memories, and

their architectures are developed to accomodate and exploit the unique properties of the

nonvolatile memory cells [7]-[8].

2.2 DYNAMIC RANDOM ACCESS MEMORY (DRAM)

Computer system performance is increasingly limited by the performance of DRAM based

memory systems due to the fact that the rate of DRAM memory system performance increase

has lagged the rate of processor performance increase in the past thirty years. One reason that

DRAM memory system performance has consistently lagged processor performance is that

DRAM memory systems typically consist of one or more chips that are designed and

manufactured separately from the processor, and the performance of the interconnected multi-

chip DRAM memory system is difficult to scale to achieve higher datarate and lower access

latency. One apparent solution to the problem of access latencies introduced by system level

interconnects between processors and memory systems are to integrate the memory system

with the processor onto the same silicon die. However, in the case of the integrated memory

system, the size of the silicon die limits the storage capacity of the memory system, and that

capacity cannot be configured by the end user as needed for different operating environments.

Moreover, the die area used by the memory system could have been used by performance

enhancing features or more processor cores. In essence, the integration of processor and

memory system onto the same silicon die is currently a viable solution for only a limited

subset of high performance systems. As a result, high performance processors are keeping

7

silicon die area for use by logic transistors, and memory transistors for main memory are still

constructed separately from the processor chip. For example, high performance processors

such as Intels Itanium and Pentium processors, AMDs Opteron processor, and IBMs

Power5 processors are all moving toward multi-core designs or already contain multiple

processor cores per chip, and the study of the memory system as a separate entity will

continue to have great relevance for the foreseeable future [1].

A second reason that the rate of increase of DRAM memory system performance has lagged

the rate of increase of processor performance is that while high performance processors are

specialized parts and typically command high price premiums, standard DRAM devices are

commodity items that can be freely purchased from multiple vendors. The commodity nature

of standard DRAM devices means that DRAM device manufacturers are extraordinarily

sensitive to manufacturing costs, and only features that provide substantial performance

benefits for minimal cost increments are considered in each new generation of standard

DRAM devices. However, there is great difficulty in the determination of performance impact

for different performance enhancing features proposed for each new generation of DRAM

devices, and that difficulty arises from the fact DRAM memory system performance depends

on a large number of independent variables such as workload characteristics of memory

access rate and request sequence, memory system architecture, and memory system

configuration [1]. As a result, system architects and design engineers will often disagree as to

the impact of various performance enhancing features, since that performance impact depends

on the configuration of specific systems.

Presently, DRAM device datarates are increasing with each new generation of DRAM

devices at the rate of 100% every three years, and DRAM row cycle times are decreasing at a

rate of approximately 7%per year. The collective trends are increasing the ratio of row cycle

times to the duration of data bursts on the data bus. As a result, to maintain a given utilization

rate of memory system bandwidth, more requests must be issued to the DRAM memory

system in parallel for each successive generation of higher data rate DRAM devices.

Collectively, these trends form the larger picture that while DRAM based memory system

performance are increasingly limiting system performance, it is becoming more difficult to

maintain efficiency in each successive generations of higher data rate DRAM devices [4].

Moreover, system architects and design engineers often disagree as to the desirability of

various proposed DRAM device and system enhancements designed to increase DRAM

memory system performance [14]. With these considerations forming the background, the

8

work in this dissertation is devoted to the creation of a common basis that system architects

and design engineers can use to quantify the impact of various proposed performance

enhancing features in modern DRAM devices, subjected to different workloads, system

architecture and system configurations.

Fig 2.2 : 64 Mbit Fast Page Mode DRAM Device (4096 x 1024 x 16)

2.3 STATIC RANDOM ACCESS MEMORY (SRAM)

Random access memories which retain their data content as long as electric power is supplied

to the memory device, and do not need any rewrite or refresh operation, are called static

random access memories or SRAMs [1]. CMOS SRAMs feature very fast write and read

operations, can be designed to have extremely low standby power consumption and to operate

in radiation hardened and other severe environments.

9

The excellent speed and power performances, and the great environmental tolerances of

CMOS SRAMs are obtained by compromises in costs per bit. High costs per bit. High costs

per bits are consequences of the large slicon areas required to implement static memory cells.

A typical CMOS SRAM cell includes four transistors, or two transistors with two resistors, to

accomodate a positive feedback circuit for data hold, and one or two complementary inverters

provides a stable data storage, and facilites high speed write and read operations. The data

readout is non-destructive, and a single sense amplifier per memory cell array or block is

sufficient to carry out read operations.

SRAM architectures and operations are very similar to that of the generic RAM, but an

SRAM architecture comprises also row and column address registers, data input-output

control and buffer circuits, and a power down control circuit, in addition to the constituent

parts of the generic RAM. The operation of the SRAM starts with the detection of an address

change in the address register. An address change activates the SRAM circuits, the internal

timing circuit generates the control clocks, and the decoders select a single memory cell. At

write, the memory cell recieves a new datum from the data input buffers ; at read, the sense

amplifier detects and amplifies the cell signal and transfers the datum to the output buffer.

Data input/output and write/read are controlled by output enable OE and write enable WE

signals. A chip enable signal allows for convinient applications in clocked systems, and

system power consumption may be saved by the use of the power down signal PD. The power

down circuit controls the transition between the active and standby modes. In active mode, the

entire SRAM is powered by the full supply voltage ; in standby mode, only the memory cells

get a reduced supply voltage. In some designs, the memory-internal timing circuit remains

powered and operational also during power down [16].

10

Fig 2.2 : Functonal Diagram of SRAM

11

CHAPTER 3: DESIGN OF STATIC RANDOM ACCESS

MEMORY (SRAM)

3.1 INTRODUCTION

An SRAM cell is the key SRAM component storing binary information. A typical SRAM cell

uses two cross- coupled inverters forming a latch and access transistors. Access transistors

enable access to the cell during read and write operations and provide cell isolation during the

not-accessed state. An SRAM cell is designed to provide non-destructive read access, write

capability and data storage (or data retention) for as long as cell is powered.

We will discuss design and analysis aspects of a six-transistor (6T) CMOS SRAM cell and a

loadless 4T SRAM cell. We will describe their advantages and disadvantages.

In general, the cell design must strike a balance between cell area, robustness, speed, leakage

and yield. Cell size minimization is one of the most important design objectives. A smaller

cell allows the number of bits per unit area to be increased and thus, decreases cost per bit.

Reduced cell area can indirectly improve the speed and power consumption due to the

reduction of the associated cell capacitances. Smaller cells result in a smaller array area and

hence smaller bit line and word line capacitances, which in turn helps to improve the access

speed performance. Reducing the transistor dimensions is the most effective means to achieve

a smaller cell area.

However, the transistor dimensions cannot be reduced indefinitely without compromising the

other parameters. For instance, smaller transistors can compromise the cell stability. Often,

performance and stability objectives restrict arbitrary reduction in cell transistor sizes.

Similarly, cell area can be traded off for special features such as an improved radiation

hardening or multi-port cell access [19].

3.2 SIX TRANSISTOR (6T)- STATIC RANDOM ACCESS MEMORY

The mainstream six-transistor (6T) CMOS SRAM cell is shown in the below figure. Similarly

to one of the implementations of an SR latch, it consists of six transistors. Four transistors

(Q1Q4) comprise cross-coupled CMOS inverters and two NMOS transistors Q5 and Q6

provide read and write access to the cell. Upon the activation of the word line, the access

transistors connect the two internal nodes of the cell to the true (BL) and the complementary

(BLB) bit lines. A 6T CMOS SRAM cell is the most popular SRAM cell due to its superior

robustness, low power and low-voltage operation. Therefore, we will discuss its operation and

12

design in greater detail. An SRAM cell must be designed such that it provides a non-

destructive read operation and a reliable write operation. These two requirements impose

contradicting requirements on SRAM cell transistor sizing. SRAM cell transistor ratios that

must be observed for successful read and write operations are discussed in the following

sections [29].

Fig 3.1 6T- SRAM Cell

3.2.1 READ OPERATION

Prior to initiating a read operation, the bit lines are precharged to VDD. The read operation is

initiated by enabling the word line (WL) and connecting the precharged bit lines, BL and

BLB, to the internal nodes of the cell. Upon read access, the bit line voltage VBL remains at

the precharge level. The complementary bit line voltage VBLB is discharged through transistors

Q1 and Q5 connected in series. Effectively, transistors Q1 and Q5 form a voltage divider whose

13

output is now no longer at zero volt and is connected to the input of inverter Q2Q4. Sizing of

Q1 and Q5 should ensure that inverter Q2Q4 does not switch causing a destructive read. In

other words, 0+V should be less than the switching threshold of inverter Q2Q4 plus some

safety margin or Noise Margin.

Ignoring the short-channel and body effects, the maximum allowed value 0+V of the node

storing logic 0 during read access can be expressed as:

= +

2 1 + + 2 2

(3.1)

Where CR () is the cell ratio defined as

=1/15/5

Since the cell is fully symmetrical, the CR is the same for Q2 and Q6. Typically, in order to

ensure a non-destructive read and an adequate noise margin, CR must be greater than one and

can be varied depending on the target application of the cell from approximately 1 to 2.5.

Larger CRs provide higher read current Iread (and hence the speed) and improved stability at

the expense of larger cell area. Smaller CRs ensure a more compact cell with moderate speed

and stability. Leakage through the access transistors should be minimized to ensure robust

read operation and to reduce the leakage power.

A preferred sizing solution can be to use a minimum-width access transistors with a slightly

larger than the minimal length channel and a larger than minimal width with a minimal length

driver transistors [20]-[22].

Once the complementary bit line discharges to a certain VBLB =VDD V voltage level

sufficient for reliable sensing by the sense amplifier, the sense amplifier is enabled and

amplifies the small differential voltage between the bit lines to the full-swing CMOS level

output signal.

3.2.2 WRITE OPERATION

The write operation is similar to a reset operation of an SR latch. One of the bit lines, BL in,

is driven from precharged value (VDD) to the ground potential by a write driver through

transistor Q6. If transistors Q4 and Q6 are properly sized, then the cell is flipped and its data is

14

effectively overwritten. A statistical measure of SRAM cell write ability is defined as write

margin. Write margin is defined as the minimum bit line voltage required flipping the state of

an SRAM cell [23]. The write margin value and variation is a function of the cell design,

SRAM array size and process variation. A cell is considered not writeable if the worst-case

write margin becomes lower than the ground potential.

Note that the write operation is applied to the node storing a 1. This is necessitated by the

non-destructive read constraint that ensures that a 0 node does not exceed the switching

threshold of inverter Q2Q4. The function of the pull-up transistors is only to maintain the

high level on the 1 storage node and prevent its discharge by the off-state leakage current of

the driver transistor during data retention and to provide the low-to-high transition during

overwriting [23]-[25].

Assuming that the switching will not start before 1 node is below VTH Q1, a simplified over-

write condition can be expressed as:

"1" = VDD VTHn VDD VTHn 2 2

p

n

PR VDD VTHp VDSATp VDSATp

2

2

(3.2)

where the pull-up ratio of the cell, PR, is defined as:

=4/46/6

The V1 requirement is normally met using minimal-sized access and pull-up transistors only

due to / ratio. The exact maximum allowed PR is defined by the VTHn process option and

by the switching threshold of inverter Q1Q3. Normally, to minimize the cell area and hence,

increase the packing density, the sizes of the pull-up and access transistors are chosen to be

minimal and approximately the same. However, stronger access transistors and/or weaker

pull-up transistors may be needed to ensure a robust write operation under the worst process

conditions e.g., in the fast PMOS and slow NMOS process skew corner. On the other hand, a

relatively strong pull-up PMOS also benefits the read stability due to the increased P/N ratio

of the back-to-back inverters (Q3Q1 and Q4Q2) of the cells latch. The read stability of an

SRAM cell on one hand and the write ability of the cell on the other hand are conflicting

15

design requirements. It is getting increasingly more difficult to balance these requirements by

conventional transistor sizing and VTH optimization as the design window becomes

increasingly narrower [23] with the technology scaling. Despite the larger number of

transistors compared to the other discussed cells, 6T CMOS SRAM cells offer superior

stability and packing density provided the same performance and environmental tolerance.

3.3 FOUR TRANSISTOR (4T) STATIC RANDOM ACCESS MEMORY

The basic idea of the loadless 4T-SRAM was proposed in 1987. This was the first report of a

4T-SRAM fabricated in a CMOS logic process, but it described mainly a specialized circuit to

hold the cell data. In this field, concepts on layout or fabrication technology have not been

discussed to reduce the area of the 4T-SRAM cell until another loadless 4T-SRAM cell was

introduced by Noda. A pair of PMOS transfer transistors is used to store and retain full-swing

signals in the cell without a refresh cycle. The memory cell size is 35% smaller than a 6T cell

using the same design rule with CMOS 0.18 micron technology. This cell can remain stable at

1.8 V with its cell ratio of 1.0. However the threshold voltage difference between NMOSFET

and PMOSFET has to be controlled from 0.2 to 0.4 V, which causes barriers to the

applications of this technique. Here, a loadless 4T SRAM cell uses NMOS transistors as

access transistors. In addition, the bitlines are precharged to ground instead of VDD. The goal

of introducing this loadless 4T cell is to achieve a smaller cell size than conventional 4T-cell,

with the same stability and the same compatibility with CMOS logic processes as 6TSRAM

cells [17].

Fig 3.2 4T- SRAM Cell

16

3.3.1 READ AND WRITE OPERATION

Firstly the write operation of the cell is described as follows. In order to store a logic 1 to

the cell, BL is charged to VDD and BL is charged to ground and vice-verse for storing a logic

0. Then the wordline voltage is switched to VDD to turn ON the NMOS access transistors.

When the access transistors are turned on, the values of the bitlines are written into Q and Q.

The node that is storing the logic 1 will not go to full VDD because of a voltage drop across

the NMOS access transistor. After the write operation the wordline voltage is reset to ground

to turn off the NMOS access transistors. The node with the logic1 stored will be pulled

up to full VDD through the PMOS driver transistors [26]-[27].

The read operation of the cell is different from that of the 6T transistors. To read from the cell

the bitlines are charged to ground instead of VDD and the wordline voltage is set to VDD to

turn on the NMOS access transistors. The node with logic 1 stored will pull the voltage on

the corresponding bitline up to a high (not VDD because of the voltage drop across the NMOS

access transistor) voltage level. The other bitline is pulled to ground. The sense amplifier will

detect which bitline is at a high voltage and which bitline is at ground. If the cell was storing a

logic 0 the voltage level of BL will be lower than BL so the sense amplifier will output a

logic 0. If the cell was storing logic 1 then the voltage level of BL will be higher than BL

then the sense amplifier will output a logic 1 [28].

17

CHAPTER 4: METRICS TO EVALUATE STATIC RANDOM

ACCESS MEMORY

4.1 INTRODUCTION

During the recent past CMOS IC technologies have been constantly scaled down aggressively

and thus entering in the nanometer regime recently. Among the wide variety of circuit

applications, integrated memories and specially SRAM cell layout has been significantly

improved. It is well known that critical dimension (CD) reduction entails an increase in

physical parameters variation, which among other effects has a direct impact on SRAM cell

stability. Polysilicon and diffusion CD together with implant variations are the main causes of

mismatch in SRAM cells. Current System on Chip (SoC) trends result in a significant

percentage of the total die area being dedicated to memory blocks, thus making SRAM

parameter variations dominate the overall circuit parameter characteristics, including leakage,

process variation effects, etc. Therefore, a deep knowledge and analysis about the stability of

the SRAM cells and the impact of physical parameters variation is becoming a must in

modern CMOS designs. The stability and robustness of a given SRAM cell is usually

evaluated analyzing both its dynamic and static behaviour during the typical operations: write,

read and hold periods. The metrics considered here for the design are: (1) Static Noise Margin

(SNM), (2) Write Noise Margin (WNM), (3) On-Current, (4) Off-Current and (5) Data

Retention Voltage [36].

4.2 STATIC NOISE MARGIN

The stability and robustness of a given SRAM cell is usually evaluated analyzing both its

dynamic and static behavior during the typical operations: write, read and hold periods.

According to this, the memory cell stability can be estimated from the Static Noise Margin

analysis. SNM is defined as the minimum DC noise voltage needed to flip the cell state, and

is used to quantify the stability of a SRAM cell using a static approach. A significant effort

has been devoted to explore the impact of process variations, temperature, etc., using the

SNM as a metric. In this paper we present a detailed analysis about 6T SRAM cells static

stability during read, and compare the differences between SNM during hold- and readmode.

The read-mode is usually identified as the cell weakest mode. SNM is a key performance

factor during hold and read operations, and its value changes significantly depending on the

18

specific operation mode. It has been shown that during read the SNM takes its lowest value

and the cell is in its weakest state. The worst-case SNM is when the wordline is settled high

and both bit-lines are still pre-charged high. While in this situation, the SRAM cell internal

node being low will be pulled up through the access transistor degrading significantly the

SNM during the read operation [37].

SNM Increases with Increase in Cell Ration.

SNM Increases with Increase in Supply Voltage.

SNM Decreases with Increase in Word Line Voltage

SNM Increases with Decrease in Bit Line Voltages.

4.3 WRITE NOISE MARGIN

Write margin is the measure of the ability to write data into the SRAM cell. Write margin

voltage is the maximum noise voltage present at bit lines during successful write operation.

When noise voltages exceeds the write margin voltage, then write failure occurs. In this

section, we introduce static approach for measuring write margin. The most common static

approach uses SNM as a criterion.

For a successful write, only one cross point should be found on the butterfly curves,

indicating that the cell is mono-stable. WSNM for writing 1 is the width of the smallest

square that can be embedded between the lower-right half of the curves. WSNM for writing

0 can be obtained from a similar simulation. The final WSNM for the cell is the minimum

of the margin for writing 0 and writing 1. A cell with lower WSNM has poorer write

ability.

The function of the SRAM write driver is to quickly discharge one of the bit lines from the

precharge level to below the write margin of the SRAM cell. Normally, the write driver is

enabled by the Write Enable (WE) signal and drives the bit line using full-swing discharge

from the precharge level to ground. The order in which the word line is enabled and the write

drivers are activated is not crucial for the correct write operation.

A write operation is possible in the region where the bit line voltage is at or below a voltage

point where the SNM becomes a zero. This voltage region is sometimes called the write

margin [37].

19

The write margin is an important design parameter as it defines the writeability of the cell.

A balance between the cell stability (SNM), the writeability, the cell area and the access speed

must be found, such that the cell has a sufficient stability margin while it still can be reliably

written into.

The function of the SRAM write driver is to quickly discharge one of the bit lines from the

precharge level to below the write margin of the SRAM cell. Normally, the write driver is

enabled by the Write Enable (WE) signal and drives the bit line using full-swing discharge

from the precharge level to ground. The order in which the word line is enabled and the write

drivers are activated is not crucial for the correct write operation [36].

4.4 ON-CURRENT

On-Current is defined as bit line current when word line goes to high. From the On-current,

the power consumption of the cell can be calculated.

4.5 OFF-CURRENT

Off-Current is defined as supply current when word line is low. It is also called us Leakage

current.

Scaling the threshold voltages of the devices down along with the supply voltage

exponentially increases the standby leakage current (Ioff ) of the circuit. The growing leakage

currents and the power, which is wasted for dissipation of the generated heat is limiting the

practical power supply scaling. Process variations together with low-VTH devices can

significantly increase the absolute leakage magnitude. The die-to-die and intra-die parameter

variations are also worsening with technology scaling. These variations affect the maximum

clock frequency and leakage power distributions. The variation effects are more pronounced

at low supply voltages (VDD) [36].

4.6 DATA RETENTION VOLTAGE

It is defined as Minimum power supply voltage required to retain node data as it is in standby

mode. As VDD scale down to DRV, the VTC of internal inverters degrade to such a level that

SNM of SRAM cell reduced to zero. If supply voltage is further scale down below DRV, then

stored data may be lost.

20

CHAPTER 5 FULLY-DEPLETED SILICON ON INSULATOR

DEVICES

5.1 INTRODUCTION

As the technology advances, the power consumption of the devices and its reduction plays a

key role in making the technology efficient. The basic Bulk devices have limitations in

nanotechnology devices. The most common issue which Bulk device faces are carrier

mobility reduction because of impurity scattering, increasing gate tunnelling current,

increasing leakage at junction etc. The above mentioned effects are the reason for non-

scalable devices at DSM. Because of above facts the operating voltages are to be set higher

rather than to be set low to achieve required speed and performance. The available cooling

systems for the electronic devices are getting failed due to the exceeding heat generated by

the integrated devices than the predicted values. Though the above mentioned problems are

quite dominant, yet Ubiquitous Environment is getting advanced day by day. The best

examples of the Smart Technologies are mobile phones, advanced graphic games, PDAs etc.

The lesser power consumption by these devices, more the battery life.

Silicon-on-Insulator technology offers low capacitance, in turn enabling higher speed of

operation. That is, with the reduced power supply, same speed of operation can be carried

out. Good radiation hardness, to withstand soaring temperatures and to withstand high

voltages is some of added advantages of SOI technology. SOI MOSFETs are classified into

two types: (i) Partially Depleted SOI and (ii) Fully Depleted SOI.

With Silicon-on-Insulator (SOI) technology, the formation of MOSFETs with thin top Si

layer separated from the Si Body by an insulating film. In FDSOI devices the entire body

region is depleted while the channel formation. The above reason bags the merits and adds

more advantage such as better performance at low power supply voltages etc to FDSOI

technology [38]-[43].

5.2 BASIC FEATURES OF FDSOI DEVICES

SOI CMOS devices are formed in a thin top Si layer separated from the substrate by an

insulating film. An insulator is also used to completely isolate nMOSFET and pMOSFET

from each other. As a result, a CMOS structure fabricated on an SOI substrate exhibits better

characteristics in some respects than one built on an SOI substrate exhibits better

21

characteristics in some respects than one built on an SOI substrate exhibits better

characteristics in some respects than one built on a conventional bulk-Si substrate, such as a

lower parasitic capacitance, no latch-up problems, a lower junction leakage current, and

higher immunity to soft errors. The low parasitic capacitance, which is related to high-speed

and low-power operation, is discussed below.

In order for signals to propagate inside an LSI, the MOSFETs have to charge and discharge a

load capacitance consisting of the drain junction capacitance, gate capacitance, and

interconnection capacitance. Among them, the drain junction capacitance is about one order

of magnitude smaller in an SOI MOSFET than in device made on a bulk-Si substrate.

The drain junction capacitance of an SOI MOSFET can be broken down into the vertical

junction capacitance (CJV) between the drain and the substrate, and the lateral junction

capacitance (CJL) between the side wall of the drain and the body. CJV can be further

decomposed into the series connection of the capacitance (CJVB) of the buried oxide (BOX,

silicon oxide film with a permittivity 1/3 that of Si) and the capacitance (CJVD) of the

depletion layer that extends beneath the BOX. The thickness of the body region is typically

no more than 0.10.2 m in SOI substrates for CMOS circuits, and the area of the drain-body

junction is very small [40]-[46].

Fig 5.1 Drain junction capacitance of SOI MOSFET

22

As a result, CJL is small. When an SOI nMOSFET is fabricated on a p-type substrate, the

drain layer is made n+ type so that a potential difference remains, even when the drain voltage

is zero, due to the difference between the Fermi levels of the drain layer and the substrate;

and a depletion layer thus forms underneath the BOX. During circuit operation, even though

the potential of the drain layer changes from zero to the supply voltage, a depletion layer

forms underneath the BOX at either potential.

For an SOI pMOSFET fabricated on a p-type substrate, the drain layer is p+ type. So, the

substrate side comes very close to the flat band condition when the drain voltage is zero.

Consequently, no depletion layer forms underneath the BOX. However, a depletion layer

starts to grow when a slight positive voltage is applied to the drain. During circuit operation,

the drain layer of a pMOSFET changes from 0 V to the positive supply voltage; and a

depletion layer usually forms underneath the BOX. Accordingly, the effect of the drain

junction capacitance in pMOSFETs is similar to that in nMOSFETs.

So, one of the key characteristics of SOI CMOS structures is that they have a smaller junction

capacitance than bulk-Si CMOS structures; and the difference becomes more pronounced as

the supply voltage drops. We will now consider the extent to which the smaller junction

capacitance affects overall LSI performance [42]-[50].

5.3 MODES OF OPERATION: FDSOI DEVICES

SOI MOSFETs have two modes of operation: fully-depleted (FD) and partially-depleted

(PD). The difference between them is described below with reference TO an nMOSFET as

example. In an FD-SOI device, the entire body region is depleted in both the ON and

OFF states. This results from the fact that an FD-SOI device generally has a thinner body

region than a PD-SOI device. For example, the body region is about 100200 nm thick in a

PD-SOI device, but at most about 50 nm thick in an FD-SOI device [43].

In contrast to an FD-SOI device, a PD-SOI device has an undepleted neutral region at the

bottom of the body region. This difference results in a different potential distribution inside

the body region. In an FD-SOI device, the entire body region has a potential gradient in the

depth direction; and the gate field extends right into the BOX. In a PD-SOI device, the

influence of the gate field stops inside the body region; and there is a neutral region with no

potential gradient at the bottom of the body region. Accordingly, the potential difference

between the top and bottom of the body region is larger in a PD-SOI device; and the potential

barrier to holes between the source and body near the bottom of the body region is higher.

23

Fig 5.2: Cross section of FDSOI MOSFET and its energy band-diagram

Fig 5.3: Cross section of PDSOI MOSFET and its energy band-diagram

This difference in the barrier height for holes leads to a difference in the number of holes that

accumulate in the body region. Holes are generated by impact ionization near the drain.

During the operation of an nMOSFET, when channel electrons pass through the high-

electrical-field region near the drain, they gain energy from the field and jump to higher

energy levels. The high-energy electrons collide with valence electrons and generate more

electrons and holes (impact ionization). The electrons flow into the drain, and the holes flow

toward the source via the bottom of the body region. When this happens, more holes

accumulate at the bottom of the body region in a PD-SOI than in an FD-SOI device because a

PD-SOI device has a higher potential barrier. This leads to a large difference between the

floating-body effects (described below) of the two types of devices, such as the kink in the

drain current-voltage characteristics and the stability of the dynamic characteristics [48].

As a way of presenting an overview of the structural parameters used to design FD-SOI

MOSFETs, Fig 5.4 shows the results of simple calculations to determine the proper

relationship among the impurity concentration (NA), the maximum thickness (TB) of the body

region, and the threshold voltage (Vth). TB and Vth are given by

= 20 2

1/2

24

= + 2 +

Where

=

ln

KSi is the relative permittivity of silicon, 0 is the permittivity of a vacuum, q is the charge on

an electron, VFB is the flat band voltage, COX is the capacitance of the gate oxide film, k is

Boltzmanns constant, T is the absolute temperature, and ni is the intrinsic impurity

concentration. TB is taken to be the width of the channel depletion layer when a threshold

voltage is applied (with a surface potential of 2F). To make an FD-SOI device, the channel

depletion layer must just reach the BOX, thus depleting the entire body region, which means

that the thickness of the body region must be no larger than TB. That is, TB is the maximum

thickness. More precisely, in an FD-SOI MOSFET the body region must remain fully

depleted over the range of gate voltages from 0 V up to the threshold voltage. Accordingly,

since the body must be fully depleted at a surface potential of approximately F and not 2 F,

TB should be thought of as a rough estimate of the maximum allowable thickness of the body

region of an FD-SOI MOSFET [49].

The threshold voltage actually depends on the drain voltage, that is, it decreases with drain

voltage due to parasitic bipolar effects in FD-SOI devices, as described below. The threshold

voltages are thus the values at low drain voltages.

Under these assumptions, to obtain an FD-SOI MOSFET with a 5-nm-thick gate oxide film

and a threshold voltage of 0.30.4 V, for example, the thickness of the body region must be at

most 5060 nm.

PD-SOI devices exhibit none of the advantages of FD-SOI MOSFETs described below (kink-

free drain current-voltage characteristics, steep subthreshold characteristics, stability with

regard to dynamic floating-body effects, etc.); and their characteristics are basically the same

as those of bulk-Si MOSFETs. However, they do have the advantages of SOI structures (low

parasitic capacitance, excellent latch-up immunity, low junction leakage current, high

immunity to soft errors). To obtain a low junction capacitance, which is an important reason

for using SOI technology, the source and drain layers must either extend all the way down to

the BOX or come very close to doing so. However, unlike in FD-SOI devices, the channel

25

depletion layer must not be allowed to reach the BOX. So, the body region of a PD-SOI

device must be at least 100 nm thick [42]-[49].

Fig 5.4 Dependence of Body Thickness and Impurity Concentration of Body in an FDSOI

MOSFETs.

5.4 CHARACTERISTICS OF FDSOI MOSFETS

(a) Kink in Drain Current-Voltage Characteristics

PD-SOI devices exhibit what is called a kink , which is a sharp rise in drain current as the

drain voltage increases at a fixed gate voltage. Electrons flowing in the channel are

accelerated and jump to higher energies in the high-electrical-field region near the drain,

thereby generating large numbers of electrons and holes by impact ionization. The electrons

flow towards the drain, and the holes flow towards the source along the bottom of the body

region. Since there is a potential barrier to holes at the source end, the holes begin to

accumulate in the body region. As more and more accumulate, the body potential increases

and the barrier height decreases, which allows more holes to flow out to the source across the

barrier. Consequently, the number of holes that can accumulate in the body region is such

that the number flowing out to the source balances the number generated by impact

ionization.

26

(a) (b)

Fig 5.5 Drain current-voltage characteristics of (a) FD-SOI and (b) PD-SOI nMOSFETs.

(From J. P. Colinge, IEEE Press 1998.)

Since a PD-SOI device has a higher potential barrier to holes than an FD-SOI device does, it

allows more holes accumulate in the body region. When a large number of holes accumulate

there, the potential of the body region rises to a positive value; and this bias effect causes the

threshold voltage of a MOSFET to drop, thereby increasing the drain current. As a result, as

shown in Fig 5.5, acute impact ionization takes place as the drain voltage increases, causing a

kink to appear in the drain current-voltage characteristics. Thus, the kink effect in PD-SOI

MOSFETs originates from the change in the body potential.

One feature of FD-SOI devices is that they do not exhibit this sort of kink. In an FD-SOI

device, the potential barrier to holes at the source end is small, even deep within the body

region, because the body region is depleted all the way down to the bottom. As a result, there

is little accumulation of holes in this region; so a kink cannot appear. Since there is no need

to resort to a body terminal to eliminate kink, FD-SOI devices have the advantage of being

smaller than PD-SOI devices with a body terminal, and can thus be integrated into LSIs at

higher densities. They make it easier to design layout patterns, and they make it possible to

draw upon existing resources for circuit design and layout design that have previously been

developed for devices fabricated on a bulk-Si substrate [40]-[46].

(b) Steep Subthreshold Slope in FDSOI-MOSFETs

An important feature of FD-SOI MOSFETs is their steep subthreshold characteristic. The

subthreshold swing of an FD-SOI device is close to 60 mV/dec at room temperature, which is

the limiting value for MOSFETs. The subthreshold characteristics are the drain current vs.

27

gate voltage (ID vs.VG) characteristics at gate voltages below the threshold voltage. In this

region, the drain current increases exponentially with gate voltage because it is proportional

to the number of carriers with enough thermal energy to cross the potential barrier between

the source and channel, as shown in the formula

= exp

where is a constant of proportionality and B is the barrier potential. B can be written in

terms of the built-in potential (Vbi) of the source-channel p-n junction and the channel surface

potential (S) as follows:

=

As the gradient of log(ID) vs. VG in the subthreshold region becomes steeper, the drain

leakage current (off current) at VG = 0 becomes smaller. In addition, for a given off current, a

steeper gradient allows the threshold voltage to be made smaller. Producing high-speed LSIs

with a low power dissipation requires the use of MOSFETs with a low threshold voltage and

a small off current, which in turn requires a steep gradient. The gradient is expressed as the

subthreshold swing, S, which is defined to be the change in gate voltage needed to change the

drain current by one decade in the subthreshold region, as shown by the following formula.

(S is given in units of mV/dec.). S becomes smaller as the rate at which the channel surface

potential changes with gate voltage become larger, resulting in steeper subthreshold

characteristics.

Fig .6 shows typical subthreshold characteristics of FD-SOI and bulk-Si MOSFETs (and PD-

SOI MOSFETs). As mentioned at the outset, FD-SOI devices have steeper subthreshold

characteristics than bulk or PD-SOI devices, with S being close to the limiting value. To put

it another way, for a given change in gate voltage, the channel surface potential changes more

in an FD-SOI device than in bulk or PD-SOI devices. The reason for this is explained below

[40]-[46].

Fig 5.6 Subthreshold characteristics of FD-SOI, PD-SOI, and bulk-Si MOSFETs.

28

(c) Dynamic Floating-Body Effects

Since an SOI device is fully isolated, the body potential is not fixed and changes for a variety

of reasons. The effects brought about by these changes are referred to collectively as floating-

body effects. In particular, dynamic floating-body effects that occur when a device is

operating in a circuit can give rise to complex behaviour. The main causes of changes in body

potential are impact ionization and majority carrier redistribution in the body region, which

occur as the gate and drain switch between high and low levels [45].

(i) Effect of Impact Ionization

For the nMOSFET, some of the holes generated by impact ionization in the high-electric-

field region near the drain accumulate in the body region and raise the body potential to a

positive value. Since the number of accumulated holes depends on the time constants of hole

creation and annihilation, the device exhibits complex behaviour when operating dynamically

in an LSI.

As the drain voltage increases, the holes pile up faster in the body region and the threshold

voltage drops at a faster rate, causing the increase in drain current to take place sooner. In this

way, differences in the number of holes generated during the operation of a PD-SOI device

give rise to differences in the rate at which holes accumulate in the body region, which

appear as differences in the transient characteristics. On the other hand, no such transient

characteristics are observed in FD-SOI devices. Thus, at voltages for which impact ionization

occurs, a PD-SOI MOSFET will exhibit complex behaviour that depends on the pulse

conditions, while an FD-SOI MOSFET will function stably. This difference arises because

the entire body region of an FD-SOI device is depleted, which makes the potential barrier to

holes between the source and body region smaller than in a PD-SOI device, thereby allowing

fewer holes to accumulate in the body region.

As described above, a PD-SOI device exhibits pronounced dynamic floating-body effects

associated with impact ionization. To suppress these effects, the device must be provided

with an extra terminal to fix the body potential by extracting holes. In contrast, an FD-SOI

device can be said to be stabilized against dynamic floating-body effects, and thus has no

need of a body terminal [40]-[46].

(ii) Effects of Majority Carrier Redistribution

When the gate voltage changes from the low to the high level, the channel depletion layer

grows wider, driving away the holes (majority carriers) that it encounters along the way. The

holes accumulate at the bottom of the body region and raise the body potential to a positive

29

value. Since the source junction is forward-biased, the holes then flow out towards the

source. Next, when the gate returns to the low level, holes are needed to make the channel

depletion layer narrower so that a neutral region can form. But since the holes have already

flowed out, there is a shortage, which creates a negative body potential that causes holes to be

supplied from the source as a reverse-biased junction current. In this way, the body potential

varies due to the surplus or shortage of holes in the body region arising from the outflow and

supply of holes at the source junction and the expulsion and restoration of holes due to the

growth and contraction of the channel depletion layer. In addition, since similar phenomena

are associated with the growth and contraction of the drain depletion layer as the drain

changes between high and low levels, the body potential of devices operating in an LSI

exhibits complex behaviour. The phenomena associated with majority carrier redistribution

only cause problems in PD-SOI MOSFETs; while in principle, they do not even occur in FD-

SOI devices because the entire body region is always depleted [43]-[45].

(d) Parasitic Bipolar Effects in FDSOI MOSFETs

A major part of the appeal of FD-SOI MOSFETs is that they suppress the kink in the drain

current-voltage characteristics without using a body terminal. But although a kink does not

appear, the devices are still susceptible to a kind of floating-body effect known as parasitic

bipolar effects. These effects occur when the source, body, and drain of MOSFETs act as the

emitter, base, and collector of parasitic transistors in which the base current consists of

majority carriers produced by impact ionization. Since the body region is more depleted in

FD- than in PD-SOI devices, the injection efficiency of the emitter of the parasitic bipolar

transistors is higher, which makes these effects more likely to occur. When they do occur,

they have a number of consequences, such as a reduction in the breakdown voltage between

the source and drain, abnormally steep subthreshold characteristics beyond the theoretical

limit, a larger off current, and a smaller threshold voltage [49]-[52].

Suppressing parasitic bipolar effects in FD-SOI devices entails:

Suppressing the generation of majority carriers by impact ionization

Reducing the injection efficiency of the emitter of parasitic bipolar transistors.

Lowering the transport efficiency with which minority carriers injected into the base

are conveyed to the collector.

Techniques that are reported to be effective include introducing electron-hole recombination

centers near the source by Ar ion implantation, and using SiGe for the source region to

30

reduce the potential barrier to holes between the source and body. In both techniques, holes

(for an nMOSFET) are extracted from the body region to prevent the potential there from

becoming positive and to reduce the emitter injection efficiency [47].

(e) Self-Heating Effects

We have seen the beneficial effects that the buried insulating film underneath an SOI

MOSFET has on the electrical characteristics. However, the thermal properties must also be

considered. The thermal conductivity of the silicon oxide film typically used for the buried

insulator is 1.4 Wm1

K1

, which is two orders of magnitude smaller than that of Si

(140 Wm1

K1

). As a result, the Joule heat generated by the drain current cannot easily

escape through the BOX and the substrate. This gives rise to self-heating, which raises the

channel temperature.

A large amount of Joule heat is generated in the saturation region, where the drain voltage

and current are both large; and the resulting increase in temperature reduces the drain current

by lowering the carrier mobility, and may lead to the appearance of a differential negative

resistance in the drain current-voltage characteristics. Accordingly, different drain current-

voltage characteristics may be obtained when measuring the steady-state drain current with a

DC supply, and when measuring the drain current with a pulse supply, which causes less

heating and is thus less likely to induce self-heating, even under the same drain and gate bias

conditions.

The Joule heat generated in the channel is dissipated by the interconnections via the contacts

on the source and drain layer, and via the gate oxide film and gate electrode. Consequently,

considering the ease with which Joule heat is dissipated, the increase in channel temperature

caused by self-heating is governed by the structural parameters of the device, such as the

thickness of the SOI layer, the distance between the channel and the source/drain contacts,

and the thickness of the BOX [45]-[52].

31

CHAPTER 6: MATHEMATICAL ANALYSIS OF SRAM CELL

6.1 ANALYTICAL SNM EXPRESSION FOR A 6T SRAM CELL

Employing the same long-channel MOS current equations for the circuit in Fig .1 and

assuming that transistors Q1 and Q4 are saturated and transistors Q2 and Q5 are in the linear

mode:

Fig 6.1 A six-transistor full CMOS SRAM cell in a read-accessed mode

1 2 =

2

5(5 0.55)

(6.1)

4 2 = 22(2 0.52)

(6.2)

Where of NMOS transistor in the cell is assumed of PMOS transistor and

= / , = / .

The Kirchhoff equations for the 6T SRAM cell are [53]:

1 = + 2

5 = 2

5 = 2

4 = 2

Thus,

32

2 + 2 =

2 ( 22 + 2)

2 2 = 22 2 0.52

Where =

Eliminating 2 and 2 from the above equation yields a fourth-degree equation.

Assuming local linearity of the transfer characteristic on inverter Q2Q4 around its operating

point where Q2 is in the linear region, it can be simplified as [53]:

2 = 0 2

Where

=

+ 1

=

+ 1

+ 1

1 + +

0 = + 1 +

1 + +

After eliminating VDS2 from the above equation and simplification, we get:

2 1 + 2 +

2 + 2

+ + +

2 = 0

Where

= 2

= 0 + + 1

Similarly to the derivation in the double-root stability criterion was applied to obtain the

SNM:

6 = 1

+ 1

2 + 1 + 1

1 +

( + 1)

2

1 + +

1 + 2 +

2

(6.3)

33

6.2 ANALYTICAL SNM EXPRESSION FOR A LOADLESS 4T SRAM

CELL

Shockleys MOSFET model, represented by Equation 3.37 was used to analytically calculate

circuit parameters for long-channel transistors. However, the Shockley model is increasingly

inaccurate in describing the behaviour of the modern short-channel transistors. Short-channel

effects, such as the carrier velocity saturation, must be taken into account for accurate

analytical characterization of sub-micron MOSFETs.

In scaled-down transistors, Shockleys square-law dependence does not hold. The shift of

VDSAT and discrepancies in the saturation region called for the Alpha-Power Law (APL)

proposed in. Drain current in the APL is then proportional to (VGS VTH) , where is the

velocity saturation index. While in the Shockley model = 2, the measured values can

range from one to two. The APL model is defined as [54]:

=

0,

/2 , < 0

, 0

Where

=0

0 /2

(6.4)

=0

(6.5)

Assuming that both inverters comprising a four-transistor loadless SRAM cell are equivalent,

we used the following equivalent circuits to derive the SNM expression. Since we are

interested in the worst-case SNM, we will consider the cell in the read-accessed mode, i.e.

with the activated word line. In the case of a four-transistor loadless SRAM cell, which is

using PMOS transistors as both the access and the load, the read-accessed mode corresponds

to VWL = 0, i.e. when the gate of Q4 is grounded. Since many of the parameters in the APL

model are technology-dependent, we will differentiate between n and p transistors as well as

between the linear and saturated modes of the transistors. For instance, the velocity saturation

index , the threshold voltage VTH and the saturation voltage VD0 will vary with the transistor

type and operating mode.

Analytically Static Noise Margin of the SRAM cell is found out and verified from the VTC

curve. The Noise Margins are found out graphically, which would be represented by the sides

34

of the rectangle drawn between the two VTCs of the half-cells. For analytical calculations,

we can express the SNM of a loadless four-transistor SRAM cell as the diagonal of the

rectangle with the sides equal to NMH and NML. The final expression can be presented as:

Fig 6.2 Equivalent circuit of a 4T loadless SRAM half-cell

4 = 2 +

2

Where,

=

=

From the Analysis carried out, the following results were obtained:

=

/2

(6.6)

We define as the point where

= 1, thus

=

1

1

1

2(1 ( )) + ( )

(6.7)

=

( )/2

(6.8)

We define as the point where

= 1, thus

35

=

2

2

+2

2 +2 + ( )

(6.9)

Thus the Noise Margins are:

=

=

2

(

2

2

+2

2 +2 + ( ))

(6.10)

=

=

1

1

1

2 1 +

2

(6.11)

6.3 ANALYTICAL SNM EXPRESSION FOR A PROPOSED LOADLESS

4T SRAM CELL

Similar to the analysis of loadless 4T-SRAM discussed above, the analysis of 4T-SRAM

proposed is also done in similar fashion. To calculate the SNM of the 4T-SRAM, the Noise

Margin is calculated for the Half-Cells and the square root of the sum of squares of the Noise

Margin gives us the Static Noise Margin value.

4 = 2 +

2

Where,

=

=

36

Fig 6.3 Equivalent circuit of Proposed 4T loadless SRAM half-cell

From the Analysis carried out, the following results were obtained:

=

( )/2

+

(6.12)

Where

= , = ||, = , = ||

=

1 1

2 1 +

(6.13)

=

/2

(6.14)

=

2

2

+2

2 +2 +

(6.15)

37

Thus,

=

=

Therefore,

=

2

+

2

2

+

1 1

2 1 +

2

2

+2

2 +2 +

2

(6.16)

38

CHAPTER 7: RESULTS

7.1 SPECTRE SETUP FOR SRAM CELL DESIGNED IN 28 nm BULK

TECHNOLOGY

The 4T- and 6T- SRAM cell was designed in 28 nm Bulk technology and then simulated in

Cadence Spectre simulator using 28 nm Bulk Technology. The following are the snap shots:

Fig 7.1 Proposed 4T-SRAM Cell Setup in Cadence Vituoso Environment

Fig 7.2 Proposed 4T-SRAM Cell : Simulation for SNM Curve

39

Fig 7.3 Proposed 4T-SRAM Cell : Simulation for WNM Curve

Fig 7.4 6T-SRAM Cell Setup in Cadence Vituoso Environment

40

Fig 7.5 6T-SRAM Cell : Simulation for SNM Curve

Fig 7.6 6T-SRAM Cell : Simulation for WNM Curve

41

7.2 SPECTRE SETUP FOR SRAM CELL DESIGNED IN 28 nm FDSOI

TECHNOLOGY & SIMULATION GRAPH USING ELDO SIMULATOR

Fig 7.7 4T-SRAM Cell Setup in Cadence Vituoso Environment designed in 28 nm FDSOI

Technology

Fig 7.8 Proposed 4T-SRAM Cell Setup in Cadence Vituoso Environment designed in 28 nm

FDSOI Technology

42

7.3 SIMULATED OUTPUT

7.3.1 ANALYSIS FOR STATIC NOISE MARGIN FOR PROPOSED 4T-SRAM


Table 7.1: Cell Ratio Modulation, VDC = 1.0 V

Cell Ratio Pull-Down (nm) Pass-Gate (nm) SNM (mV)

1.0 120 120 230

1.5 180 120 312

2.0 240 120 360

2.5 300 120 400

3.0 360 120 440

Fig 7.9 Cell Ratio Modulation, VDC = 1.0 V



1.0 120 120 235

1.5 180 120 318

2.0 240 120 365

2.5 300 120 418

3.0 360 120 456

0

50

100

150

200

250

300

350

400

450

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Stat

ic N

ois

e M

argi

n (

)SN

M)

in m

V

Cell Ratio

Cell Ratio Vs SNM

Vdc = 1 V

43




1.0 120 120 241

1.5 180 120 325

2.0 240 120 385

2.5 300 120 440

3.0 360 120 490


0

50

100

150

200

250

300

350

400

450

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Stat

ic N

ois

e M

argi

n (

)SN

M)

in m

V

Cell Ratio

Cell Ratio Vs SNM

Vdc = 1.1 V

0

50

100

150

200

250

300

350

400

450

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Stat

ic N

ois

e M

argi

n (

)SN

M)

in m

V

Cell Ratio

Cell Ratio Vs SNM

Vdc = 1.2 V

44



1.0 120 120 260

1.5 180 120 356

2.0 240 120 426

2.5 300 120 482

3.0 360 120 518


Table 7.5: Supply Voltage Modulation PD= 120 nm, PG= 120nm and CR=1

Vsupply

(V) SNM (mV)

1.0 230

1.1 235

1.2 241

1.3 260

Fig 7.13 Supply Voltage Modulation, PD= 120 nm, PG= 120nm and CR=1

0

50

100

150

200

250

300

350

400

450

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Stat

ic N

ois

e M

argi

n (

)SN

M)

in m

V

Cell Ratio

Cell Ratio Vs SNM

Vdc = 1.3 V

225230235240245250255260265

0 0.2 0.4 0.6 0.8 1 1.2 1.4Stat

ixc

No

ise

Mar

gin

(SN

M) i

n

mV

Supply Voltage in Volts

Supply Voltage Vs SNM

CR = 1

45

Table 7.6: Supply Voltage Modulation PD= 180 nm, PG= 120nm and CR=1.5

Vsupply

(V) SNM (mV)

1.0 312

1.1 318

1.2 325

1.3 356

Fig 7.14 Supply Voltage Modulation ,PD= 180 nm, PG= 120nm and CR=1.5


Vsupply

(V) SNM (mV)

1.0 360

1.1 365

1.2 385

1.3 426


300

310

320

330

340

350

360

0 0.2 0.4 0.6 0.8 1 1.2 1.4Stat

ixc

No

ise

Mar

gin

(SN

M) i

n m

V



CR = 1.5

350

360

370

380

390

400

410

420

430

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Stat

ixc

No

ise

Mar

gin

(SN

M) i

n m

V



CR = 2

46

Table 7.8: Supply Voltage Modulation PD= 300 nm, PG= 120nm and CR=2.5

Vsupply

(V) SNM (mV)

1.0 400

1.1 418

1.2 440

1.3 482

Fig 7.16 Supply Voltage Modulation, PD= 300 nm, PG= 120nm and CR=2.5


Vsupply

(V) SNM (mV)

1.0 440

1.1 456

1.2 490

1.3 518


0

100

200

300

400

500

600

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Stat

ixc

No

ise

Mar

gin

(SN

M) i

n m

V



CR = 2.5

420

440

460

480

500

520

540

0 0.2 0.4 0.6 0.8 1 1.2 1.4Sta

tixc

No

ise

Mar

gin

(SN

M) i

n m

V



CR = 3

47

7.3.2 ANALYSIS FOR WRITE NOISE MARGIN FOR PROPOSED 4T-SRAM


Table 7.10: Pull-Up Ratio Modulation, VDC = 1.3 V

Cell Ratio Pass Gate (nm) Pull-Up (nm) WNM (mV)

1.0 120 120 521

1.1 110 120 523

1.2 100 120 534

1.3 90 120 550

1.5 80 120 579

Fig 7.18 Pull-Up Ratio Modulation, VDC = 1.3 V

Table 7.1

thesis draft

Documents

nm bulk technology

master of technology

nm fdsoi

lowpower lowarea application

tsram cell

award of master

design of loadless

degree of master