Thermal impedance testing of high-speedgate arrays

E.R. Brown, B.Tech., K. Beasley, B.Sc, and W.L. Barber, B.Sc.

Indexing terms: Integrated circuits, Reliability, Semiconductor devices and materials, Very large-scale integra-tion

Abstract: The paper describes a method for 100% testing of the thermal impedance of integrated circuits usinga temperature-sensitive parameter. The approach is applicable to automated test procedures, and results arepresented on its use in testing a high-speed gate array. Alternative methods for assessing thermal impedance arediscussed.

1 Introduction

Levels of integration in silicon technology have alreadybeen reached in certain areas where packaging imposes amajor restriction on achievable levels of integration. Onespecific constraint imposed by packaging techniques isthermal impedance. This problem is currently only acutein high-speed circuits, e.g. high-speed gate arrays, but is asignificant factor in the exploitation of VLSI technologiesin general. The reliability of a device is a function of itsjunction temperature, which in turn is dependent on thethermal impedance through the device package toambient. Such significant variations occur in manufac-turing in the attachment of a device to a package and apackage to a heatsink, that thermal impedance testingneeds to be carried out on a 100% basis.

In this paper a method for 100% testing of the thermalimpedance of a high-speed gate array is described. Themethod is based on the measurement of a temperature-sensitive parameter on the device, and is applicable toautomated test procedures. Alternative methods for assess-ing device thermal integrity are discussed, and the limi-tations and advantages of each approach are highlighted.

2 Need for good die attach

It is widely recognised that integrated circuit reliability isheavily dependent on the temperature of the device. It isperhaps less widely realised how much this temperaturecan depend on the integrity of the attachment of the chipto the package, and of any heatsink to the same package.The parameter that links attachment integrity to chip tem-perature is the thermal impedance of the interface.

Even a batch of mechanically sound die and heatsinkinterfaces can exhibit a wide range of thermal impedancefigures. For example, an uneven thickness of the epoxyused to attach the heatsink has been seen to double thethermal impedance from 10 to 20°C/W. Table 1 shows theeffect that this can have on device reliability. The relation-ship is also shown graphically in Fig. 1. 9j_hs is the thermalimpedance figure between the junction and the heatsinksurface, 7} is the junction temperature and X is the failurerate.

The results shown in Table 1 are based on calculationsusing MIL HDBK 217D [1] for a 64-pin flatpack con-taining a 450-gate ECL chip operating at 40°C and dissi-pating 4 W. The following n factors from the MIL HDBK217D reliability model are assumed:

Paper 3761G (E10, El, E3), first received 3rd September and in revised form 19thNovember 1984

The authors are with Plessey Research (Caswell) Ltd., Towcester, Northants. NN128EQ, United Kingdom

Table 1 : Effect of poor thermal impedance on reliability

deg C/W

510152025

Junctiontemperaturedeg C

6080

100120140

Failure rateFITs

230290403599922

1 FIT = 1 failure in 109 device hours

1000

750

500

a- 2 50

e) - h s

15

. d e g C / W

25

Fig. 1 Effect of poor thermal impedance on Reliability

(a) Environmental factor nE = 1(b) Quality factor nQ = 3(c) Learning factor nL = 1.

To ensure a consistent low failure rate for a given part,it is thus necessary to have confidence in a low thermalimpedance figure for not just a given design, but for everydevice manufactured.

Since reliability is becoming an increasingly importantaspect of device performance, good thermal integrityapplies to all but very-low-dissipation devices.

3 Device description

The SCD4000 is a member of a family of ECL gate arrayproducts, manufactured on a Plessey bipolar process,which have minimum gate delays of 500 ps. Device dissi-pation is customisation-dependent, typically 3.5 W. Thisrelatively high power consumption is justified by the high-speed capability. Customisations of the arrays are used inhigh-speed computing, instrumentation and transmissionsystems. A specific example of an array customisation isthe CD 1003, which is a port switch control unit for theMacrolan fibre-optic link.

1EE PROCEEDINGS, Vol. 132, Pt. G, No. 6, DECEMBER 1985 111

Because reliability is important, the package type andmounting technique used for the circuit take account ofthermal performance. Fig. 2 shows a schematic cross-section of the assembly configuration used, and Fig. 3

ceramic packagebase

heat-extractorblock boltedto caseof system

surface-mounted"onto flexible PCB

eutectic-bondedIC chip

tin-plated copper blockepoxy-bonded to package

Fig. 2 CDI003 assembly configuration

Fig. 3 The CD 1003

shows a photograph of the device. The ceramic packagehas a mass of approximately 1 g; by the attachment of acopper heat extractor, its mass is increased to 10 g. Thepertinent points of the assembly are as follows:

(a) The 64-lead flatpack used is particularly suitable,because (i) it has a metal leadframe, and thus a low leadresistance, necessary for high-speed circuits, and (ii) it has avery thin ceramic base (approximately 0.4 mm), lendingitself to rapid heat transfer away from the chip

(b) A nonfilled epoxy is used for the heatsink attach,since this allows a thinner glue-line to be obtained. Silverfillers improve the thermal conductivity of an epoxy, butlimit the minimum obtainable glue thickness

(c) Bolting the (copper) heat extractor block to the caseof the system gives the assembly an infinite heatsink.

4 Interface assessment methods

4.1 IntroductionA number of methods exist for assessing die attachment,and a few for assessing heatsink attachment. For the

SCD4000, an assessment of both is required. The followingreview of available methods highlights the advantages anddisadvantages for this particular application.

4.2 Mechanical tests—destructiveDie-bond strength testing (DBST) is recognised as a usefulquality control tool in assessing eutectic die-attach integ-rity, and can also be applied to heatsink attach. In theory,a nondestructive strength limit can be set on most DBSTmachines, but an attempt to test all devices using DBSTwould result in an unacceptable degree of mechanicaldamage. A device may pass the test, but the edges of thechip may be damaged to an extent that would affect elec-trical performance and degrade reliability.

In addition, for large chips and good attach integrity,die-attach strength does not correlate with thermal imped-ance measurements. For example, a 70% eutectic forma-tion may pass a 10 kg die-bond strength test (well in excessof the MIL STD 883 requirements), but contain sufficientvoids to severely degrade thermal impedance and hencereliability.

4.3 Mechanical measurements—nondestructiveA simple assessment of the thermal impedance of aheatsink-to-package interface can be obtained by measur-ing the thickness of the bond. The thinner the glue-line, thelower the thermal impedance. In practice, surface varia-tions in the heatsink package may be greater than thethickness of bond required. A variation in bond thicknessacross a single assembly can, however, give a good indica-tion of an uneven bond (i.e. a wedge-shaped interface).With a digital autozero micrometer, this measurement canbe quickly completed, giving at least a coarse screen ofthermal impedance.

4.4 X-rayThis well established method of observing voids inmaterials suffers from the following three major problemsin this application:

(a) The copper block is an efficient absorber of X-rays,resulting in insufficient contrast to give a clear image of theattachment interfaces

(b) The presence or absence of voids in an interface isnot an accurate measure of thermal impedance, as for thedie-bond strength test [2]

(c) While it may be possible to engineer an X-raymachine into a manufacturing inspection station, the costwould be high.

4.5 Acoustic microscopyThe concept of using a scanning acoustic beam to providean image of the interior of an object has been well knownfor some time, but commercial equipment has only recent-ly become available. As the name implies, an image of asample is built up from the reflections of an acoustic beam,which scans across the sample. This scanning and the sub-sequent signal analysis are complicated, but the techniquedoes allow hidden interfaces to be examined. The manufac-turers use 'die-attach integrity' as an example of the usesfor such an instrument, but its long scan time (of the orderof minutes for large chips) and the use of a water couplerbetween the microscope lens and the sample make thismethod unsuitable for production testing. The 'acousticscanning microscope' is a research and analytical toolwhich can provide useful information on the structure ofinterface layers, extent of voids etc.

278 IEE PROCEEDINGS, Vol. 132, Pt. G, No. 6, DECEMBER 1985

4.6 Use of temperature-sensitive parameter (TSP)Since semiconductor junctions have a well definedresponse to temperature, it is logical that any thermalanalysis makes use of this feature. For example, a testdiode could be specifically designed for such a job.However, assuming appropriate calibration is performed,any temperature-sensitive parameter can be utilised.Methods for assessment of die attach have been widelyreported [2], but the technique is used as a 'quality' ratherthan a 'reliability' screen. Purpose-built equipment is avail-able for die-attach and thermal-impedance evaluations, butthe technique can be applied on automatic test equipment(ATE). Because of long thermal time constants and thuslong test times, production testing is only usually con-sidered for die-attach, as opposed to heatsink-attachtesting.

4.7 Choice of method for SCD4000For the SCD4000, a number of economic factors were con-sidered when deciding on a method for screening ofthermal impedance. The test time for LSI devices is typi-cally a few seconds; the thermal time constant for theSCD4000 package is typically 10 minutes. Testing, which isdependent on the device reaching thermal equilibrium,would be uneconomic.

System reliability is a major requirement, the aim beingto keep field failures to as low a level as possible, prefer-ably zero. Screening costs can thus be balanced by thereduction in repair costs.

The SCD4000 is in a flatpack, which cannot be testedusing an autohandler on ATE. Test time is thus limited bythe rate of manual loading and unloading of devices,rather than actual test time.

Although the requirement is to assess the efficiency ofthe heatsink as well as the die-attach interface, these inter-faces and the intervening ceramic package back are allthin. The thermal path being considered is thus thin incomparison with many IC packages.

Taking into consideration these factors, the methodswere compared in terms of their economic factors andeffectiveness in screening out devices with poor thermalimpedance. Table 2 shows a summary of this comparison.Clearly, as a production screen, the use of a TSP is theonly sensible approach. Details of this test for theSCD4000 are now given.

Table 2: Comparison pf interface assessment methods

Method

DBSTThickness

measurementX-rayAcousticMicroscopy

TSP

Initialcost

low

lowhighhigh

very low

Test cost

high*

low?high

very low

Effectiveness for

Dieattach

poor

—poorgood

good

Heatsinkattach

poor

poor—good

good

* Assumes high drop-out rate owing to mechanical damage

5 Thermal measurement on ATE

5.1 MethodThe measurement of a temperature-sensitive parameter(TSP) enables the operating temperature of a chip inside apackage to be monitored, and hence the chip-to-ambientthermal impedance to be calculated if the power dissi-pation of the device is known. To perform a 100% thermalimpedance screen while allowing thermal equilibrium to be

obtained, however, would take typically minutes for theSCD4000 package structure under discussion. This longtest time makes a complete thermal impedance measure-ment impracticable. Thermal performance can, however,be assessed quite accurately for a previously characterisedpackage, by monitoring the TSP during warm-up.

Fig. 4 shows chip temperature above ambient against

500

Fig. 4 Heating characteristics

time for the SCD4000 package. This is divided into fourzones. In zone 1 the chip and package are warming up at asteady rate. In zone 2 the temperature remains relativelystatic. In zone 3 the temperature increases again as theheat extractor block begins to heat up. In zone 4 thermalequilibrium is reached. In Fig. 5, typical chip heating

0.05 0.5 50 5005time, s

Fig. 5 Effect of poor interface layers on heating characteristics(a) Poor die attach(b) Poor heat-extractor attach(c) Good device

curves are given for devices with poor die attach and poorheat extractor attach, compared with a good device. Aswould be expected, the poor die-attach effect can be seenafter only a short time (approximately 50 ms), whereas thepoor heat extractor effect shows significantly after about500 ms. Beyond this, the slope of the curve {dT/dt) dependson the thermal mass of the complete assembly, and is rela-tively independent of the quality of the interfaces.

By choosing an appropriate test time (greater than 500ms), it is thus possible to assess the quality of both die andheat-extractor attachments. Such a time is compatible withATE test time.

The temperature-sensitive parameter for the SCD4000 isan ECL output transistor, as shown in Fig. 6. This varieslinearly with temperature, at typically 1.4 mV/°C. Theforward voltage of this output is measured prior to func-tional and parametric tests, the device heats up during thenormal test routine, and at the end of the production elec-trical test, the TSP is remeasured, and the value comparedwith the initial value. The difference is dependent on thequality of die and heat-extractor attach.

1EE PROCEEDINGS, Vol. 132, Pt. G, No. 6, DECEMBER 1985 279

5.2 CalibrationBefore the above method can be used, 'calibration' isessential. The temperature-sensitive component must be

-2V

Fig. 6 ECL output transistor

characterised, thermal impedances must be measured andchip-heating curves plotted, to give correlation betweenthermal impedances and the intermediate measurements.Obvious sources of error are variations between devicetypes in the temperature-sensitive component being mea-sured. Experience with the SCD4000 has led the authors tobelieve that the policy of incorporating a simple diode onhigh-dissipation products, to give more predictable results,is logical. Using the device power consumption as theheating pulse means that device-to-device variations inpower supply current can affect the measured temperaturerise. This can, however, be easily corrected, since the ATEtest program already monitors supply currents as part ofthe test sequence.

5.3 ResultsFig. 7 shows a histogram of results obtained for theSCD4000 package measured using the method described.

10 12

10 -

6 8

(8 j c ) , d e g C / W

Fig. 7 Distribution of thermal impedance

Working from reliability and maximum chip-temperaturerequirements, a maximum acceptable thermal impedancefigure can be easily calculated, to give a 'pass/fail' criterion.Devices with poor thermal properties can be screened outon a 100% basis with only a negligible increase in testtime.

6 Conclusions

To guarantee high reliability for high-dissipation devices,100% assessment of the thermal impedance of the criticalinterfaces of the package and mounting methods isrequired. It has been shown that this 100% screen can beaccomplished by the addition in the ATE program of ameasurement of a temperature-sensitive parameter.

7 Acknowledgments

In addition to colleagues at Plessey Research (Caswell), theauthors wish to thank members of the Macrolan project atInternational Computers Ltd., Kidsgrove and Manchester.

8 References

1 'Reliability prediction of electronic equipment'. MIL HDBK 217D V.S.D.O.D. Notice 1, June 1983

2 PORTER, G.: 'Nondestructive die attach integrity test'. Proceedings of20th IEEE international reliability physics symposium, San Diego,California, 1982, pp. 45-46

Edmund R. Brown was born in MarketHarborough, Leicestershire, UnitedKingdom. After attending the localgrammar school, he received his B. Tech.degree in electrical and electronic engineer-ing at the University of Bradford in 1968.He then worked for Marconi Communica-tion Systems on satellite communicationsuntil 1973, when he joined PlesseyResearch (Caswell) Ltd. At Caswell he hasbeen concerned with the development of

integrated circuits, and is currently Departmental Manager forhigh-performance silicon integrated circuits.

Keith Beasley was born in Croughton,Northamptonshire, United Kingdom, andafter secondary education at MagdalenCollege School in Brackley, he graduatedin 1979 from the University College ofNorth Wales at Bangor with a B.Sc. degreein electronic engineering. Since graduatinghe has been employed at Plessey Research(Caswell) Ltd., on the quality assurance ofsilicon integrated circuits. He is currentlyresponsible for design and product assur-

ance, encompassing failure and reliability analysis of devices.

William L. Barber was born in Blakesley,Northamptonshire, United Kingdom, andafter attending Towcester Grammar Schoolhe received his B.Sc. degree in electronicengineering from Southampton Universityin 1972. Since graduating he has worked atPlessey Research (Caswell) Ltd., where hehas been concerned with the developmentof high-performance silicon integrated cir-cuits. Activities that he has beenresponsible for include the design of high-

speed digital and linear circuits, but currently he is a Senior Prin-cipal Scientist, concerned with the engineering of advanceddevices for pilot production.

280 IEE PROCEEDINGS, Vol. 132, Pt. G, No. 6, DECEMBER 1985