THE 18F2550 USB CONNECTION(001)

(Some very basic comments are included in this document, for the benefit of different user’s levels.)

THE CORE <MICROCONTROLLER> SPEED

Devices in the PIC18F2455/2550/4455/4550 family incorporate a different oscillator and microcontroller clock system than previous PIC18F devices. The addition of the USB module, with its unique requirements for a stable clock source, make it necessary to provide a separate clock source that is compliant with both USB low-speed and full-speed specifications.

The USB module must be clocked from the primary clock source; however, the microcontroller core and other peripherals can be separately clocked from the secondary or internal oscillators.

Since a 20MHz xtal setup is used in HSPLL mode, the option is restricted to the PLL Postcaler deriving the microcontroller clock from the PLL (do not confuse it with the Oscillator Postscaler <see figure 2.1 of datasheet>). This allows the USB peripheral and microcontroller to use the same oscillator input and still operate at different clock speeds.

So the core speed is defined by the CONFIG1L: CONFIGURATION REGISTER:

CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)bit 4-3 CPUDIV1:CPUDIV0: System Clock Postscaler Selection bitsFor XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes:11 = 96 MHz PLL divided by 6 to derive system clock (96MHz/6=16MHz)10 = 96 MHz PLL divided by 4 to derive system clock (96MHz/4=24MHz)01 = 96 MHz PLL divided by 3 to derive system clock (96MHz/3=32MHz)00 = 96 MHz PLL divided by 2 to derive system clock (96MHz/2=48MHz)

For any case the Tcy is equal the result divided by 4 (16MHz/4 = 4MHz; 24MHz/4 = 6MHz; 32MHz/4 = 8MHz; 48MHz/4 =12MHz)

The selection will be essentially based on the peripherals setup and some other considerations (a PLL divided by 6 to derive system clock is selected for this case, so Tcy= 4MHz)

USB CONFIGURATION

Prior to communicating over USB, the module’s associated internal and/or external hardware must be configured. Most of the configuration is performed with the UCFG register.

A “USB device not recognized” message is mostly caused by an inappropriate hardware and/or software configuration.

IMPORTANT NOTE:

The software used here is essentially based on the Assembler version of Jan Axelson’s genhid firmware for PIC18F4455. It has been modified for this project.

Four files are contained in it:

genhid.asm ENGR 2210.inc : SECTION 01 PIC ASSEMBLER MACROS: Created by

Bradley A. Minch 9/2004 to facilitate reasonably structured programming in PIC assembler. These macros were inspired and informed both by Karl Lunt’s PIC macros, described in an atricle in the July 1999 Nuts & Volts magazine, and by Myke Predko’s structured programming macros, which are described on pp. 542-546 of the second edition of Programming and Customizing PICmicro Microcontrollers. These macros provide facilities for for-next loops, repeat-until loops, select statements, and if statements.

usb_defs.inc 18f2550.lkr

The initial configuration setup is (genhid.asm):

#include <p18F2550.inc>#include “usb_defs.inc”#include “ENGR2210.inc”

__CONFIG _CONFIG1L, _PLLDIV_5_1L & _CPUDIV_OSC4_PLL6_1L & _USBDIV_2_1L__CONFIG _CONFIG1H, _FOSC_HSPLL_HS_1H & _FCMEM_OFF_1H & _IESO_OFF_1H__CONFIG _CONFIG2L, _PWRT_OFF_2L & _BOR_ON_2L & _VREGEN_ON_2L__CONFIG _CONFIG2H, _WDT_OFF_2H & _WDTPS_32768_2H__CONFIG _CONFIG3H, _MCLRE_ON_3H & _LPT1OSC_OFF_3H & _PBADEN_OFF_3H & _CCP2MX_ON_3H__CONFIG _CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _XINST_OFF_4L & _DEBUG_OFF_4L__CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L__CONFIG _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H__CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L__CONFIG _CONFIG6H, _WRTB_OFF_6H & _WRTC_OFF_6H & _WRTD_OFF_6H__CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L__CONFIG _CONFIG7H, _EBTRB_OFF_7H

In terms of register values the above configuration means (see datasheet, section 25.1- Configuration Bits):

CONFIG1L value = 3CCONFIG1H value = 0ECONFIG2L value = 3FCONFIG2H value = 1ECONFIG3H value = 81CONFIG4L value = A1CONFIG5L value = 0FCONFIG5H value = C0CONFIG6L value = 0FCONFIG6H value = E0CONFIG7L value = 0FCONFIG7H value = 40

For example:

CONFIG1L value = 3C (hex) = 0011 1100 (binary)

CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)

0 0 1 1 1 1 0 0

bit 5 USBDIV=1 = USB clock source comes from the 96 MHz PLL divided by 2: USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1)bit 4-3 CPUDIV1:CPUDIV0: System Clock Postscaler Selection bitsFor XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes:11 = 96 MHz PLL divided by 6 to derive system clock (96MHz/6=16MHz)bit 2-0 PLLDIV2:PLLDIV0= 100 = Divide by 5 (20 MHz oscillator input): PLL Prescaler Selection bits

And so much for the other registers.

So, for most of the registers it is not necessary to clear or to set the bits, nor even write a value to the register, but instead the appropriate directives are used, except when it is mandatory as in the following case where there is no specific directive found:

movlw 0x14 movwf UCFG

UCFG: USB CONFIGURATION REGISTER

0 0 0 1 0 1 0 0

bit 7 UTEYE= 0 = Eye pattern test disabled: USB Eye Pattern Test Enable bitbit 6 UOEMON= 0 = UOE signal inactive: USB OE Monitor Enable bit

bit 4 UPUEN=1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0): USB On-Chip Pull-up Enable bitbit 3 UTRDIS=0 = On-chip transceiver active: On-Chip Transceiver Disable bit bit 2 FSEN=1 = Full-speed device (pull up, internal <on chip> resistor on D+): controls transceiver edge rates; requires input clock at 48 MHz: Full-Speed Enable bit

Or, where it is necessary, to set a bit for a specific reason:

bsf UEP0, EPSTALL; set EP0 protocol stall bit to signify Request Error

UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)

bit 0 EPSTALL = 1 Endpoint n is stalled (n = 0 <UEP0>): Endpoint Stall Enable bit(1)(EPSTALL of endpoint0 =1)

The registers where no configuration is provided remain in the condition immediately after the turning on (.Value at POR).