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THE SCAN-PATH TECHNFOR TESTABLE SEQUEN

CIRCUIT DESIGN

Presented by,  Lavanyashree B 

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 NDEX

Sequential circuits

Scan path technique

Modified sequential circuit

Race less D-type flip flop

Configuration of logic card

Advantages and Disadvantages

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SEQUENTIAL CIRCUITS

 Complexity testing sequential circuits due to

feedback loops

lacement of the circuit in a kno!n state"

#iming problems in general

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SCAN PATH TECHNIQUE

 $n %&'() *ippon electric company introduced a design for testabiltechniques called +SCA* A#, "

Scan is ability to shift into or out of any state

Scan-path design is to reduce test generation complexity for circui

containing storage devices and feedback path !ith combinational l

#he philosophy is to divide conquer !ith the purpose to .

  %" Set any internal state easily

/" 0bserve any state through a distinguishing sequence

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Modied general sequential

circuit has following properties:

»  Circuit can easily be set toany desired internal state

»Circuit has distinguishing sequence

Continued..

Fig1: A sequential circu

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Continued..

1hen

  C23 *ormal mode

  C2% Shift Register 

4ses double thro! s!itch

Double #hro!-S!itch has a

contact that can be connected

to either of t!o other

contacts"

Fig2: A realization for tthrow Switch

A

C

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Continued..

Fig3: odi!ed sequenticircuit

Procedure for testing circuit is

%" Set C2% to s!itch circuit to

shift register mode

/" Check operation as shift register

 by scan in inputs )scan-outoutputs and clock 

5" Set initial state of shift register 

6" Set C23 to return to normal

mode

(" Apply test input pattern to

combinational logic7" Set C2% ting state to return to

shift register mode

'" Shift out final state !hile setting

the starting state for the next

test"

8" 9o to step 6

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Continued..

Fig 4: Raceless fli flo !it" scan at"

 Raceless #$t%e fli flo Nor&al oeration:

C/2% C%23

So data is latched to D

1hen C%2%

0utput of :% is latched

Scan in oeration:

C/23#est input is applied at

1hen C/2%

0utput of :% is latched

Scan-out

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Configuration of Logic card

•,ere flip flops are connected

as shift register 

• ;ach card has one scan path

• *ippon electric company + 

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Ad(antages and #isad(antages

Advantages.

= Design automation

= ,igh fault coverage> helpful in diagnosis

= ;asy to generate test pattern

Disadvantages.

= :arge test data volume and long test time

= Requires extra pins or gates for transformation

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THAN) *+