the rf reader adi

The RF Reader

A collection of published articleson RF from Analog Devices

www.analog.com/RF

Smart Partitioning for WiMAX Radios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

AD8368: A Broadband RF/IF VGA with 34 dB Linear-in-dB Gain Control Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Measuring the RF Power in CDMA2000 and W-CDMA High Power Amplifiers (HPAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Simulating the Effect of Blockers on Data Converter Performance in Wideband Receivers . . . . . . . . . . . . . . . . . . . . . . . . . 15

Converter Performance Approaches Software-Defined Radio Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Calibration and Temperature-Compensation Techniques Using an RMS-Responding RF Detector . . . . . . . . . . . . . . . . . . . . . 21

Improved DDS Devices Enable Advanced Comm Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

RF Standards for Short-Range Wireless Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

A Broadband I/Q Modulator for Broadband Radio Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Evaluating Linear Distortion in ADC Driver Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

IQ Modulators Advance Reconfigurable Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

How to Determine an Effective Damping Factor for a Third-Order PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Log Amps and Directional Couplers Enable VSWR Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Direct Digital Synthesis Enables Digital PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

A Direct-Conversion Transmitter for WiMAX and WiBro Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Converters for 3G Are Optimized for Cost, Size, and Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

RF Power Detection: Measuring WiMAX Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Measuring VSWR and Gain in Wireless Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Low Power Direct Digital Synthesizer Cores Enable High Level of Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

The RF ReaderA collection of published articles

on RF from Analog Devices

. . .

WWIIRREELLEESSSS TTEECCHHNNOOLLOOGGIIEESS

Figure 1 shows a block diagram of atraditional WiMAX system. An RF trans-ceiver is connected through a power am-plifier (PA) and RF switches to the anten-na on one side, and to a digital baseband(DBB) on the other. The interface be-tween the RF transceiver and the DBB iscomposed of analog signals, which canbe at intermediate frequency (IF) or base-band. Note that the ADCs and DACs inthis architecture can be discrete devices,or can be integrated on an ASIC.

In some applications, a two-chip solu-tion may have higher performance andlower cost than a single-chip solution.The key is to know how to divide thefunctions between the two chips to bestexploit both the circuit topology and theavailable manufacturing technologies.Smart partitioning does just this, allow-ing an RF system-on-a-chip (SoC) to pro-vide a complete RF-to-bits solution in-cluding all required automatic gain con-trol, transmit power control and RFcalibration loops. Including control loopson the radio front end enhances ease ofuse, provides for an easier mix-and-match capability with different DBBmodems and improves performance. The

T he need for broadband wireless ac-cess (BWA) has long been acknowl-edged as the next step in the evolu-

tion of Internet access. Unfortunately, thelack of robust technology at a competi-tive price has been a barrier to its imple-mentation. Today, though, momentum tocross the chasm is gathering—earlyadopters have endorsed the technologyin under-served rural areas of the world,while standardization efforts have re-duced costs enough that mainstreamusers can now consider WiMAX a viablealternative for broadband access with afuture promise of mobile access.

WiMAX, based on IEEE 802.16 specifi-cations, supports operation in multiple fre-quencies and multiple air standards. To en-sure interoperability between multipleWiMAX solutions, the WiMAX Forum, anindustry consortium, has developed pro-files that specify the operating frequency,bandwidths, air-interface and medium ac-cess protocols. These profiles are based ona 256-carrier orthogonal frequency divi-sion multiplexing (OFDM) air interface forfixed/nomadic operation, and scalable-OFDM-access (S-OFDMA) air interface forportable/mobile applications.

Smart Partitioningfor WiMAX Radios

NOMAN RANGWALA AND RICK MYERSAnalog Devices Inc., Norwood, MA

Reprinted with permission of MICROWAVE JOURNAL® from the November 2006 issue.©2006 Horizon House Publications, Inc.

1

accompanying reduction of real-time software control results insimpler system design. All analogand RF specific controls are inte-grated on the RF front-end IC.This is smart partitioning. Figure2 illustrates a block diagram for asystem using smart partitioning.

COST BENEFITS ENABLED BY SMART PARTITIONING

For communication systemssuch as WiMAX and BWA, con-sumer prices less than $100 areessential. In CPE equipment forasymmetric digital subscriberloop (ADSL) and 802.11g Wi-Fi($20 to $30), for example, volumesincreased dramatically as pricesdeclined. Emerging markets suchas WiMAX are also experiencingsimilar price pressures. End-userCPE prices are expected to beless than $100 by mid-2007. Toachieve these targets, chipsetpricing must fall to $20 or $25.Much lower than the current

cost, this reduction will requiresignificant improvements formarket prices to yield an accept-able profit.

Smart partitioning offers theopportunity to dramatically re-duce the total cost of a WiMAXsystem. Today’s traditional DBBsare mixed-signal ASICs, withover 90 percent of their area oc-cupied by digital gates and 5 to10 percent used for data convert-ers. The cost to manufacture sucha mixed-signal device is over 1.5times the cost of manufacturing adigital-only IC. The major con-tributors include higher waferprice (1.2 times), higher test cost(1.1 times), higher yield cost (1.1times) and larger die size (1.05times), totaling a 1.5 times in-crease in cost.

In addition to the tangible cost,there is a large opportunity costincurred. Data converters typical-ly lag behind by one generationof the process, and proven cores

for 90 nm or 65 nm are not avail-able for integration on today’sfine-line digital processes. Theopportunity cost for using a 130-nm process for the digital base-band instead of a state-of-the-art90-nm process can be up totwice. Data converters integratedon a DBB constrain the cost,keeping the IC from taking ad-vantage of Moore’s law.

EASE OF USE ENABLED BY SMART PARTITIONING

By itself, the integration ofdata converters is not sufficientfor smart partitioning. The dataconverters required for WiMAXare typically over-sampled, sohandling the raw data rate in andout of the transceiver would pre-sent implementation challenges.However, integrating decimationand interpolation filters on thetransceiver allows the interfacespeed to be reduced. The avail-ability of mature fine-line RFCMOS processes, coupled withadvances in analog and RF mod-eling capabilities, have now madeit possible to move data convert-ers and other mixed-signal blocksto the RFIC in WiMAX radio de-signs. For cost and power effi-cient implementation of the digi-tal blocks, fine-line CMOS is adefinite plus. This article exploresthe choice of digital interface andthe ease of use advantages intro-duced by simple RF drivers forreceivers and transmitters.

DIGITAL INTERFACE: CHOICES,ISSUES AND CHALLENGES

The evaluation board designand layout has a critical impacton the performance of the mixed-signal component of the DBB.The analog I/O on the referenceboard is sensitive to externalnoise, and the supply routes tothe mixed-signal portion of thedesign require high isolation.Eliminating the analog I/O mini-mizes these noise-coupling is-sues, and solves the problem ofinterfacing analog cores from dif-ferent vendors (such as RF chipand mixed-signal convertercores). For example, some ADCcores require a discrete 5 V driverop-amp to obtain specified data


Ref

PLL

ADC

LO ADC

DAC

DAC

Digital Modem/MAC

Slow SpeedControl Port

Mixed Signal is integrated ondigital ASIC or Standalone

Real Time Control Signals

Real Time Control Loops partitioned betweentwo separate chips and vendors

Memory

▲ Fig. 1 Block diagram of a traditionally partitioned WiMAX system.

Ref

PLL

ADC

LO ADC

DAC

DAC

Digital Modem/MACValidated by gatelevel simulation

Digital I/Q

Slow SpeedControl Port

Real Time Control Signals

Real Time Control Loops Integratedon RF Transciever

90/65nm digitalonly process

Memory

▲ Fig. 2 Block diagram of a WiMAX system using smart partitioning.

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sheet performance. Modems us-ing smaller processes, such as130 nm or 90 nm, must reducethe signal swing and match thecommon-mode level to that of theRFIC. These considerations re-quire valuable engineering re-sources. For systems using smartpartitioning, the boundary be-tween the transceiver and theDBB is digital, simplifying theseissues.

Two basic options for selectinga digital interface are a highspeed serial data stream usinglow voltage digital swing (LVDS)signaling, or a slower speed par-allel bit stream. Variations ofthese schemes include embedded

clock, synchronous clocking, ornibble transfers. Each approachhas its advantages and disadvan-tages.

High speed serial links (seeFigure 3) have a lower pin count,reduced switching noise due tothe differential signaling andlarger separation (between DBBand RF transceiver). However,the high speed circuit design riskis one of the biggest implementa-tion challenges. Implementationof the serializer and de-serializeris complex and requires clock re-covery circuits and other customdesign blocks that are not readilyavailable in standard digital li-braries.

The parallel bit stream ap-proach offers lower data ratesand a standard CMOS I/O, but in-creases the pin count. To reducethe pin count to a manageablenumber, the data bus can usetime duplexing to multiplex be-tween receive and transmit data.Additionally, the I/O can be sin-gle-ended if the switching andhigh frequency noise are careful-ly managed and isolated from thehighly sensitive RF circuitry. Thedesign on the DBB is straightfor-ward, and can be implementedwith a standard hardware de-scription language (HDL)-baseddesign flow.

The JEDEC Committee (JC-61),formed in 2002, was chartered tocreate an open standard for digi-tal interface, enabling smart par-titioning and multi-vendor solu-tions. The published standard,JESD96, offers the high speedLVDS approach. A proposal andbasic configuration for the paral-lel interface have also been ac-cepted. Figure 4 shows an exam-ple of a parallel interface imple-mented on Analog Devices’AD935x family of smart parti-tioned transceivers. The ADI/Q™digital I/Q interface provides thebasis of the JC-61 parallel stan-dard.

AUTONOMOUS AUTOMATICGAIN CONTROL (AGC)

In addition to ADCs and deci-mation filters, smart partitionedtransceivers also integrate the au-tomatic gain control (AGC) circuit-ry on the transceiver. The AGCadjusts the gain of the receiverpath such that the input signal tothe ADC is maximized in scenar-ios with and without interference.The AD935x receiver signal chainis illustrated in Figure 5.

Time division duplexing (TDD),the preferred system for the fu-ture, supports framed waveforms(bursts). The media access con-troller (MAC) at the base stationgenerates a downlink frame,which starts with a preamble,and follows with a frame controlheader and multiple data frames.The duration of each frame isshort (1 to 2 ms). The input powerduring the burst varies by 3 dB


Rx Clock

Tx Clock

Data Field Data Field

Data Field

Frame Boundary must be a Multiple of M(User defined variable)

Register Field

Sync

Sync

Tx Data

R/W

Modem

ProsLow Pin Count

Differential Signaling

ConsComplex ImplementationHigh Speed (≈500MHz)

RF Transceiver

Sync

Header

Header

Header

I Q I Q Control Field CS Address Data CRC P

Rx Data

PNullP

▲ Fig. 3 Digital interface — Serial interface option.

D0:D9

SYNCSYNC_VALID

TXNRXEN_AGC

ENABLE

CTRL_OUT

SPI

CLK

MACModem

AD935x

ADI/Q™ — A Digital I/Q Interface

RF FE

2

3 4

2

GPO

RXTX

AUX_DAC

10

▲ Fig. 4 Parallel interface example from the AD935x family of smart partitioned transceivers.

3

for fixed systems and 10 to 12 dBfor mobile systems.

The transceiver uses the framepreamble to lock the gain of thereceiver (see Figure 6). The pre-amble is one or two OFDM sym-bols consisting of multiple toneswhose phases are aligned to cre-ate a waveform with a smallpeak-to-average power ratio. Thetones are also distributed such

that the waveform is repetitive inthe time domain.

To detect the minimum desiredsignal, the receiver gain is set tomaximum. The in-channel re-ceived power is measured at theoutputs of the ADCs and decima-tion filters. The peak detectorsdistributed along the receiverchain and the ADCs are alsomonitored for over-ranging. If

detected, the receiver gain is re-duced depending on the type ofover-ranging. If the basebandpeak detector before filters indi-cates clipping, for example, thenthe LNA gain is stepped down.The AGC algorithm cyclesthrough these iterations and con-verges on an optimum gain set-ting. The system then freezes thegain for the remainder of theframe. For the modem to syn-chronize and correlate to the sig-nal, the receiver gain must befixed. A fast AGC lock time al-lows the modem more time tosynchronize and make accuratechannel estimates, reducing theimplementation loss and improv-ing the system performance.

Traditional systems achievethis by distributing the AGCfunction on both modem andtransceiver. The dotted line in thereceiver architecture indicatesthe functional partitioning. In thisapproach, the DBB must monitorthe gain, detect peaks and set anew gain. The algorithm is gener-ally implemented in the RF soft-ware driver. Every time the gainis changed, the transceiver mustbe recalibrated and the DC-off-sets must be removed. The RFdriver must maintain accuratetiming and must respond to in-terrupts generated from thetransceiver, making optimizationa tedious, time-consuming task.In the case of multiple vendors,each RF driver must be cus-tomized for a specific transceiver.

Preamble Preamble

TransitionGap

UplinkDownlink

Signal Detection,

AGC,AntennaSelection

CoarseFrequencyOffset and

TimingSynchronization

Channeland Fine

FrequencyOffset

Estimation

FCH

VariableGain Fixed Gain

DLBurst

2

DLBurst

n

DLBurst

1

ULBurst

1

ULBurst

2

▲ Fig. 6 The 802.16 OFDM waveform.

ENV

ELO

PE

(V)

TIME (μs)

1.0

0.8

0.6

0.4

0.2

00 10 20 30 40

Input Waveform: 802.16 OFDM Downlink

SQRT (I2 + Q2) vs. time

Gain LockedAGC Lock time < 4 μs

▲ Fig. 7 Digital I/Q receive signalmeasured at the output of the AD935x.

CP

CP

CP

CP

CP

CPPreamble Symbol 2 Symbol n Symbol n+1 Symbol n+2Symbol 1

Beam-formed Signal

TIME

Fading within a burst

Zone 1PUSC

Zone 2MIMO

3 dB

9-12 dB

INP

UT

PO

WER

▲ Fig. 8 Power variations in a burst for advanced MIMO and beam-formed signals.

LNA

Mixer

Mixer VGA

VGA

OVR

OVROut ofBand In

Band

To Modem

To Modem

LNA Gain Setting

DC Offset DAC

LPF Gain SettingVGA Gain Setting

Calibration SettingsLPF Gain SettingLNA Gain SettingVGA Gain SettingDC Offset DAC

InBandOut of

Band

ADC

ADC

LPF

LPF

PeakDetector

AGC/Offset

ControlDA

C

DA

C

▲ Fig. 5 Receiver architecture on the AD935x family of smart partitioned transceivers.


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WIRELESS TECHNOLOGIESsymbol-to-symbol AGC. Thepower variation within a burst inthis scenario is 9 to 12 dB. A typi-cal power variation versus timefor a beam-formed or space-timecoded waveform is shown in Fig-ure 8. To accommodate this pow-er step, one option is to increasethe ADC dynamic range and paythe corresponding cost of in-creasing a bit in performance.Another option is to reacquirelock on a symbol-by-symbol ba-sis. A fast AGC with short locktimes, coupled with accurate tim-ing control for starting and stop-ping the AGC loop, could enablesymbol-to-symbol AGC.

Figure 9 shows a plot of re-ceiver input vs. measured receiv-er error vector magnitude (EVM)for a WiMAX transceiver, usingsmart partitioning along with asoftware modem implementedwith Agilent VSA software. Theperformance curve exemplifiesthe ease of implementationachieved using the smart parti-tioning approach. For low inputpower, the receiver gain is auto-matically adjusted to accommo-date the small input signal; thegain is then backed off automati-cally until the EVM is limited bythe linearity of the transceiver.

TRANSMITTER POWERCONTROL

The 802.16 standard specifies aranging process that determinesthe correct output power radiatedby the terminal. This process en-sures that transmissions frommultiple terminals arrive at thebase station at the desired powerlevel (within a certain range thatcan be handled by the base sta-tion). The standard specifies a

transmit power control range of50 dB for the terminal. This willallow terminals to be distributedaround the cell site to meet theequal power criteria at the basestation.

During the ranging process,the base station requests the ter-minal to send out a ranging sig-nal. The base station will thencommand the terminal to in-crease or decrease its transmitpower. The WiMAX Forum iscurrently discussing require-ments for accuracy and numberof iterations.

In traditional architectures, ex-ternal attenuators and true rmspower detectors can be used toachieve the system specifications.Using smart partitioning, the in-tegrated ADCs and DACs offerthe transmitter the ability torapidly measure highly accurateburst output power. Figure 10shows the components of theunique transmit power controlscheme implemented on theAD935x transceiver. To utilize thepower detector, the transmittedsignal is sensed from an externalcoupler. It is then fed back to thereceiver, where it is down-con-verted to baseband. The receiveADCs digitize the signal, which isthen processed by a digital rmspower meter block. This takes ad-vantage of the half-duplex natureof the system to make an accuratemeasurement using the idle cali-brated receiver path. The detec-tor is capable of measuring pow-er on a TX burst-by-burst basis,providing the modem with near-real-time power information. Thefront-end mixer is designed to betemperature and frequency inde-pendent, and thus requires only a

In multiple instances, vendorshave struggled to achieve64QAM operation on their refer-ence designs because of thesecomplex interactions.

A transceiver using smart par-titioning integrates the completecontrol loop including monitor-ing and control algorithms on asingle device. The basic processto lock the gain remains thesame, but the responsibility forcontrol is transferred to the RFtransceiver. From the modem’sperspective, the loop is au-tonomous and does not requireany dynamic interactions. Themodem can still accurately startand stop the loop, and can stillmonitor the received signalstrength indicator (RSSI) andgain settings. All internal calibra-tions are now self-contained.

With well-managed timingconstraints, this smart partition-ing approach results in two ad-vantages: a simpler RF driver andshorter AGC locking time. Fig-ure 7 shows that the AGC locktime, when using the autono-mous AGC loop on the AD935x,is of the order of four microsec-onds for an 802.16 waveform.Further advanced techniquessuch as stronger signal detection,radar detection and interferenceback-offs can also be easily im-plemented.

Advanced systems, operatingin mobile environments with fad-ing channels, multiple antennasand beam-formed signals, re-quire new techniques such as

EVM

(dB

)

INPUT POWER LEVEL (dBm)

−20

−25

−30

−35

−40−80 −60 −40 −20 0

230025502700

MaximumSignal

MinimumSignal

▲ Fig. 9 Receiver performance of a smartpartitioned receiver implemented on theAD935x.


DAC Modulator

Decode

External AntennaInterface

LORMS

Control

txrssi

pdref

ADC

▲ Fig. 10 Smart partitioned transmitter block diagram.

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WIRELESS TECHNOLOGIESone-point factory calibration.This feature saves test time andreduces calibration complexity.

The ease of use advantage isequally applicable to the trans-mitter. The modem can vary thepower on a burst-by-burst basisby simply writing to the registerbefore the burst. The transmitpower is automatically adjustedto the open loop accuracy specifi-cation of the device. If greater ac-curacy is required, the transmitpower control loop can be initiat-ed and a correction factor can beapplied to the next burst. Othernovel techniques such as self-generated short test signals canbe transmitted before the actualburst to calibrate the device inclose loop. These techniques canbe explored as emissions require-ments and system requirementsevolve.

SUMMARYThe smart partitioning of a

WiMAX system enables the low-est system cost and reduces thedependence of real-time controlfrom the DBB. Integration of theADCs and DACs by itself is notsufficient to achieve these advan-tages. To reduce the speed of thedigital interface, decimation andinterpolation filters are also inte-grated in the transceiver. Thesestages also include the channelfilters. A large portion of the RFdriver complexity is managingthe real-time signaling betweenthe modem and transceiver toachieve fast and accurate AGCand TPC. To reduce the process-ing load on the modem, the AGCand TPC algorithm blocks are in-tegrated on the transceiver. Othersmart features can be integratedon the transceiver such as auxil-

iary ADCs and DACs, RF gener-al-purpose outputs for RF switchand PA control. The AD935x fam-ily of transceivers exemplifies theRF system-on-chip features thatcan be implemented. ■

Noman Rangwala received his bachelorof engineering degree from VictoriaJubilee Technical Institute, Mumbai, in1992, his MSc degree from the Universityof New Mexico, Albuquerque, NM, in 1994,and his MBA degree from San Diego StateUniversity, San Diego, CA, in 2000. He is amarketing manager with responsibility forWiMAX transceiver marketing within theHigh Speed Signal Processing division ofAnalog Devices Inc. (ADI). He also hasover six years of experience in IC designand development.

Richard H. “Rick” Myers received his BSdegree from Old Dominion University in1983. He is a senior applications engineerfocused on wireless applications for theHigh Speed Signal Processing division ofAnalog Devices Inc. (ADI) and is based inRaleigh, NC. Before joining ADI, he wasCDMA hardware development managerfor handsets at Ericsson in ResearchTriangle Park, NC, and principal electricalengineer of RF and receivers at E-Systems(Raytheon) in Falls Church, VA.


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FEATURE ARTICLE

AD8368: A Broadband RF/IF VGA with 34 dB Linear-in-dB Gain Control Rangeby Phillip Sher, Analog Devices

Introduction

Most wireless receiv-ers incorporate some form of variable gain.

Variable gain, which is usually implemented at Intermediate Frequency (IF), is used to ampli-fy or attenuate received sig-nals so that a constant signal level is presented to subsequent stages in the receiver. Usually implemented at Intermediate Frequency (IF), variable gain is used to amplify or attenuate received signals so that a con-stant level is presented to subse-quent stages in the receiver.

Variable Gain Amplifiers (VGAs) will either have digital gain control or analog gain con-trol and are generally optimized for either receive or transmit applications. While the choice of an analog controlled or digitally controlled VGA often comes down to the preferences of the equipment designer and the available control signals, there are solid technical reasons for choosing one over the other. This article will discuss those trade-offs and will go on to discuss the operation and appli-cation of Analog Devices’ new analog controlled VGA.

A Linear-in-dB IF Variable Gain AmplifierThe AD8368 is an IF VGA with an operational bandwidth from near DC to 800 MHz and a gain control range of 34 dB from -12 dB to +22 dB. It also includes an onboard square-law detector that can be used in an AGC loop with the VGA. Using Analog Devices’ patented X-AMP architecture, the AD8368 achieves accurate linear-in-dB gain control. The part is designed with 50 input and output impedances.

The main signal path consists of a variable input attenuator followed by an integrator and output buffer. Feedback around the integrator creates a fixed-gain amplifier. Figure 1 shows a block diagram of the VGA.

Input Attenuator and InterpolatorThe input attenuator is built from a resistor ladder with eigh-teen -2 dB tap points. Each of these tap points is fed into

separate variable transconduc-tance gm stages, whose out-puts are summed and fed into an integrator. Gain control is achieved by using the GAIN pin to control the interpolator. As GAIN is swept from 0 V to 1 V, the interpolator selects different tap points by varying the transconductance of the gmstages. For gains between two tap points, the interpolator var-ies the transconductance such that the weighted sum of several adjacent tap points are chosen. In this way, an accurate contin-uous linear-in-dB gain control response is produced.

Integrator and Output BufferThe current outputs of the gm

stages are summed and fed into an integrator. Resistive feed-back from the output of the integrator to the gm stages cre-ates a low-noise, high-linearity fixed-gain amplifier. The out-put of this amplifier is fed into the output buffer, which provides an active 50 output impedance and additional 6 dB of fixed gain.

Output DC Level and Offset CorrectionSince the AD8368 is single-end-ed, the DC levels at the input and output are regulated to VPSI/2 by an internal regulator. The output of this regulator is connected to the DECL line and requires an external decoupling

capacitor. Since the fixed-gain amplifier and output stage have an extremely large overall gain, small DC offsets at the input of the fixed-gain amplifier can lead to large output offsets. To correct for these Vgain, supply and temperature variations, a low-pass offset correction loop is used which senses and main-tains the output DC level at the voltage on the DECL pin. The low-pass corner frequency of this loop is controlled by the size of the capacitor on the HPFL pin.

The AD8368 contains an accurate stand-alone RMS detector that enables versatile AGC operation. To form a com-plete AGC loop, the MODE pin is pulled low and the detector output pin is directly connected to the GAIN pin and an inte-grating capacitor. Then, by con-necting the VGA output OUTP directly to the detector input DETI, the output is leveled to the set-point -11 dBm. This ref-erence level can be raised by dividing down the output signal before applying it to the detec-tor input, allowing for a range of AGC levels.

Input and Output ImpedancesThe input to the AD8368 should be externally AC cou-pled to prevent disrupting the DC levels on the chip. Thus, a large coupling capaci-tor should be used, so that the series impedance of the capacitor is negligible at the frequencies of interest. On the chip, the input is connect-ed directly to a resistor ladder network whose impedance is nominally 50 .

The output of the part should also be AC coupled to prevent disrupting the output DC level. As with the input, a sufficiently large value of capacitance should be used so that the series impedance of the capacitor is negligible at the frequen-cies of interest.

The output impedance is synthesized by the output buf-fer. The fixed gain of the out-put buffer combined with the resistive feedback from output to input provides a nominally 50 output impedance.

Figure 1: Simplified Block Diagram

Figure 2: Gain Control Transfer Function and Linearity at 70 MHz.

7

Accurate Linear-in-dB Gain ControlThe AD8368 has a linear-in-dB gain control interface that can be operated in either a gain-up (positive gain control sense) or gain-down (nega-tive gain sense) mode. With the MODE pin pulled high in the gain-up mode, the gain increases with increasing gain control voltages; in gain-down mode (MODE pulled low) gain decreases with increasing GAIN voltages (Figure 2).

With MODE pulled high, the ideal gain function is given by the equation:

Gain(db) = 37 VGAIN – 14

With MODE low, the ideal gain function is given by the equation:

Gain(db) = -37.5 VGAIN + 24.8

where VGAIN is expressed in Volts.In addition to showing the

gain-up and gain-down transfer functions, Figure 2 also shows the error plot that reflects the deviation between the ideal gain control transfer function and real performance. From Figure 2, it is clear that the gain control transfer function closely follows the ideal for well over 30 dB.

Figure 3 shows the effect of temperature on the gain con-trol function at 140 MHz. To more closely examine the per-formance over temperature, the slope and intercept of the 25º C data is calculated over the linear part of the gain control range. This provides a sim-ple linear model to compare with the actual response of the AD8368. The comparison

of the ideal linear model to the three transfer functions at 25º C, -40 º C, and +85º C yields the linear conformance error curves scaled in dB. This method of error calculation resembles the expected error from single temperature calibra-tion during system production.

Using the AD8368 VGAThe AD8368 is a general pur-pose VGA suitable for use in a wide variety of applications where voltage-control of gain is needed. While having 800 MHz bandwidth, its use is not limited to high frequency signal process-ing. Its accurate, temperature-stable and supply-stable linear-in-dB scaling will be valuable wherever it is important to have a more dependable response to the control voltage than is usu-ally offered by Voltage Variable Attenuators (VVAs).

The input (INPT) and output (OUTP) of the AD8368 should be externally AC coupled to prevent disrupting the DC lev-els on the chip.

As a function of the gain voltage, the noise and distor-tion characteristics are easily predicted since the AD8368 consists of a passive variable attenuator followed by a fixed gain amplifier. The input-re-ferred noise increases in pro-portion to the attenuation level. Figure 4 shows output noise floor, as a function of VGAIN for the MODE pin pulled high. In receiver applications, the minimum NF should occur at the maximum gain where the received signal presum-ably is weak. At higher levels, a lower gain is needed, and the increased NF becomes less important.

The input-referred distortion varies in a similar manner to the noise. Figure 4 illustrates how the third-order inter-cept point at the input, OIP3, behaves as a function of VGAIN.At lower levels, a degraded OIP3 is acceptable. Overall, the dynamic range, represented by the difference between IIP3 and NF, remains reasonably con-stant as a function of gain. The output distortion and compres-sion are essentially independent of the gain. At low gains, when the input level is high, input overload can occur causing premature distortion.

The MODE pin controls whether the gain of the part is an increasing or decreasing function of the GAIN voltage. The ENBL pin is used to enable or disable the part. When ENBL is high, the part is enabled. With ENBL low, the part is disabled and draws a fraction of the nor-mal supply current.

The DECL pin should be decoupled using a large capaci-tor so that DECL acts as an AC ground. The HPFL pin is used to control the low-pass corner frequency of the out-put offset correction loop. The high pass corner frequency is inversely proportional to the HPFL bypass capacitor.

AGC OperationAs already noted, the AD8368 may be used as an AGC ampli-fier, as shown in Figure 5. For this application, the accurate internal square-law detector is employed. The output of this detector is a current that varies in polarity depending on wheth-er the rms value of the output is greater or less than its internally determined “set-point” of -11

dBm. This is 178 mV pk-pk for sine-wave signals, but the peak amplitude for other sig-nals, such as Gaussian noise, or those carrying complex modu-lation, will invariably be some-what greater. However, for all waveforms having a reasonable crest factor (less than 13dB), the rms value will be correct-ly measured and delivered at VOUT. The output set-point may be adjusted upwards using an external resistive divider net-work as depicted in Figure 5.In this configuration, the rms output voltage will be equal to (1+n)63mVrms, where n=R1/R2. For the default set-point of 63mVrms, simply short R2 (direct connection from OUTP to DETI) and remove R1. Other setpoints may be implemented by calculating the ratio of R2/R1. For example, a 0 dBm AGC output corresponds to 222 mV rms. This is 3.5 times 63 mV rms. Therefore (1+n)=3.5 and n=2.5. If we start with R1=100

then R2=250 . These val-ues can be further adjusted as needed.

The AGC mode of operation requires that the correct gain direction is chosen. Specifically, the gain must fall as VAGCincreases to restore the needed balance against the set-point. Therefore, the MODE pin must be pulled low.

Received Signal Strength Indicator (RSSI)A valuable feature of using a square-law detector is that the RSSI voltage is a true reflec-tion of signal power, and may be converted to an absolute power measurement for any given source impedance. The AD8368 may be employed as a

FEATURE ARTICLE

Figure 4: Noise and OIP3 vs. Control Voltage at 140 MHzFigure 3: Gain Control Transfer Function vs. Temperature

8

true-power meter by monitor-ing the voltage present at the DETO/GAIN interface.

Figure 7 illustrates the measured error-vector-mag-nitude (EVM) performance

for a 16-QAM modulation at 10MSymbols/sec using CDETO=1000pF. At lower symbol rates the AGC loop could start to track the peak to peak transitions due to the

modulation. At lower symbol rates it may be necessary to slow down the response of the AGC loop by increasing the value of CDETO .

ConclusionThe AD8368 is a high-per-formance voltage-controlled variable-gain amplifier/attenu-ator with a 34 dB linear-in-dB gain control range up to 800 MHz. The AD8368 operates from a supply voltage of 4.5 to 5.5 V and consumes 54 mA of current. It can be fully powered down to <1mA by grounding the ENBL pin. The AD8368 is fabricated in Analog Devices’ proprietary SiGe SOI comple-mentary bipolar IC process. It is available in a 24-pin CSP and operates over the industri-al temperature range of –40º C to 85º C. An evaluation board is available upon request.

About the AuthorPhillip Sher is a Senior Applications Engineer with the RFW group at Analog Devices in Wilmington, MA. He received a BEng in Electrical Engineering from Lakehead University in Thunder Bay, Canada and has more than 9 years of Engineering experience.

ANALOG DEVICES

FEATURE ARTICLE

Figure 5: AGC Mode of Operation

Figure 6: Output Power vs. Input Power in AGC Mode at 140MHz.

Figure 7: EVM Performance vs. Input Power in AGC Mode For 16 QAM at 10 Msym/sec

9

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All of our RF amplifiers, including the new ADL5321 RF driver amplifier, arefully specified over frequency, temperature, and supply voltage to minimizethe need for extensive device characterization. Every ADI RF amplifier offersunique performance advantages such as higher linearity, lower noise, lowersupply current, internal active bias, and Class 1C ESD protection. Most offeradditional features including internal matching and dual configurations.

Across the entire RF and IF signal chain, wherever you need moreperformance, greater integration, or lower solution costs, Analog Devicesis there. For more information about all of ADI’s solutions for RF designs, call 1-800-AnalogD or visit www.analog.com/rfamps-ad.

Low Noise Amplifiers (LNA)

Part

Number

Freq Range

(MHz)

Gain

(dB)

OIP3

(dBm)

P1dB

(dBm)

NF

(dB)

Current

(mA)

Specs @

(MHz)Price

ADL55211 400 to 4000 15.3 35.3 22.5 0.82 65 1950 2.15

ADL55231 400 to 4000 17.5 33.7 21.9 1.02 65 1950 2.15

Intermediate Frequency Amplifiers (IFA)

Part

Number

Freq Range

(MHz)

Gain

(dB)

OIP3

(dBm)

P1dB

(dBm)

NF

(dB)

Current

(mA)

Specs @

(MHz)Price

ADL55301 DC to 1000 16.8 37.0 21.8 3.0 110 190 1.56

ADL5531 20 to 500 20.9 41.0 20.4 2.5 101 70 2.25

ADL5534(Dual)

20 to 500 21 40.4 20.4 2.6 90 70 3.29

Gain Blocks

Part

Number

Freq Range

(MHz)

Gain

(dB)

OIP3

(dBm)

P1dB

(dBm)

NF

(dB)

Current

(mA)

Specs @

(MHz)Price

AD83531 1 to 2700 19.5 22.8 8.3 5.6 42 900 0.48

AD83541 1 to 2700 19.5 19.3 4.8 4.4 25 900 0.48

ADL5541 50 to 6000 14.7 39.2 16.3 3.8 90 2000 1.65

ADL5542 50 to 6000 18.7 39.0 18.0 3.2 93 2000 1.65

Driver Amplifiers

Part

Number

Freq Range

(MHz)

Gain

(dB)

OIP3

(dBm)

P1dB

(dBm)

NF

(dB)

Current

(mA)

Specs @

(MHz)Price

ADL5320 400 to 2700 13.7 42.0 25.6 4.2 104 2140 2.55

ADL5321 2300 to 4000 13.8 39.7 24.9 4.1 84 2600 2.55

ADL5322 700 to 1000 19.9 45.3 27.9 5.0 320 900 3.48

ADL5323 1700 to 2400 19.5 43.5 28.0 5.0 320 2140 3.481 3 V bias is also supported.2 Includes external input match

All prices shown are $U.S. in 1k quantities.

New

RF amplifiers available in 8-lead LFCSP, 16-lead LFCSP, and SOT-89 packages—from 6 mm2 to 16 mm2—with single/dual options

10

RF Bonus Feature

FEATURE ARTICLE

Measuring the RF Power in CDMA2000 and W-CDMA High Power Amplifiers (HPAs) By Larry Hawkins, Analog Devices, Inc.

Introduction

Designers of high-pow-er amplifiers (HPAs) used in CDMA2000

and W-CDMA base stations encounter many challenges in achieving accurate trans-mit power measurements. Complications include high peak-to-average ratios, peak-to-average ratios that change with base station call load-ing, large operating tempera-ture ranges, and large trans-mit power ranges. Taking advantage of accurate RMS output power measurement allows HPA manufacturers to reduce the maximum power for which they design. This article describes several ways to accurately measure and control RMS power over tem-perature.

Complex modulation schemes like CDMA2000 and W-CDMA have large peak-to-average ratios. For a given maximum average-output-power requirement, the max-imum designed-for power requirement will generally increase (or the linearization requirements increase) as the peak-to-average value increas-es, due to base station spectral mask and EVM requirements. If the peaks of the modulated signal are clipped, third order distortion will increase, caus-ing the base station to fail its spectral mask requirements. Clipping the peaks of a modu-lated signal can also cause a loss of data, making the system fail its EVM require-ments. Designing an HPA based on peak power trans-mission requirements is expen-sive but necessary. The added expenses are due to both an increased cost in the electrical components and a decreased efficiency of the HPA. There is always a $/Watt associated with the maximum designed for power of an HPA and running a HPA well below its saturation point is inefficient. A decrease in efficiency will increase the cost of an HPA module because it increases the cost, size, and weight of the mechanical structure used to dissipate the heat, reduc-es the HPA’s reliability, and

increases its operating cost. Reducing the maximum

designed-for power of an HPA is important to HPA manufac-turers. The closer an HPA’s saturation point can get to its average power, the more efficient and cost effective the HPA will be. There are many techniques used to get

a HPA’s saturation point as close as possible to the average transmitted power, but these techniques are all limited by the system’s ability to measure the output power. The maxi-mum designed-for power of the HPA needs to be increased by the RF power measurement tolerance (including variation

vs. temperature and peak-to-average ratio) to ensure spec-tral mask and EVM compli-ance. This makes the accuracy of the RF Power Measurement System critical to reducing the cost and efficiency of an HPA.

Not only do CDMA2000 and W-CDMA modulation schemes have large peak-to-av-erage values but also the peak-to-average value changes with the call volume of a particular base station. In CDMA2000 IS-95A, for example, the for-ward link crest factor is 6.6 dB for pilot only, and 12 dB for 64 channels (using no CF reduction techniques). Large peak-to-average values cause errors in non-RMS-responding RF power detectors. A modu-lation scheme’s large peak-to-average ratio can be calibrated out in production if it stays constant but variation in the peak-to-average ratio based on the amount of users is more difficult to handle. This requires keeping track of how many users are on the system, tight control of which Walsh codes are being used, and a very large look up table in order to know the peak-to-average ratio of the signal at a particular time. A better option is the use of a RMS-responding detector. Unlike diode detectors or log amps, RMS-responding detectors are largely immune to variations in crest factors. Figure 1 shows the error of a high performance Log Amp (AD8318) compared to that of an RMS-responding detector (AD8364) as a result of the crest factor change (user loading) in the TX section of a CDMA2000 IS-95A base sta-tion. Note that the AD8318’s output changes by 3.5 dB (or 86 mV) between CW and 64 channel CDMA2000 IS-95A and 2.4 dB between Pilot only and 64 channel CDMA2000 IS-95A, while the AD8364’s output only changes by 0.1 dB (or 5 mV). A diode detec-tor behaves similarly to a Log Amp, in that its output voltage changes with respect to the crest factor of the detected sig-nal. If a Log Amp were used for power detection in this system, the 2.4 dB variation

Figure 1: The errors in a RMS-responding RF detector (AD8364) vs. a non-RMS-responding RF detector show the effect of peak-to-average ratio on power detection. While a non-RMS-responding RF detector (AD8318) exhibits significant measurement error as the peak-to-average ratio of its input signal varies, an RMS-responding RF detector (AD8364) is largely immune to changes in peak-to- average ratio.

Figure 2: The Analog Devices AD8364 output voltage and log conformance error vs. Pin (@ 450 MHz) shows very little change when temperature is cycled from –40°C to +85°C. This remains true for 30 devices taken from differ-ent production lots, even though the performance is slightly different over temperature.

11

in detected power would need to be removed through signal processing or added to the maximum designed-for power in the HPA.

The errors in a RMS-responding RF detector (AD8364) vs. a non-RMS-responding RF detector show the effect of peak-to-average ratio on power detection. While a non-RMS-responding RF detector (AD8318) exhib-its significant measurement error as the peak-to-average ratio of its input signal var-ies, an RMS-responding RF detector (AD8364) is largely immune to changes in peak-to-average ratio.

Being able to accurate-ly measure the RMS power across the operating temper-ature range of the HPA is also critical in determining the maximum designed-for power of the HPA. The accuracy of this measurement (or lack thereof) will need to be added directly to the maximum designed-for power, unless the difficult and costly process of calibration over temperature is performed. All components involved with the detection of the HPA’s output power (e.g. directional coupler, attenua-tor, etc.) can add errors over temperature, but most change very little over the HPA’s oper-ating temperature. Generally, the accuracy of measuring the HPA’s output power over tem-perature is directly related to the temperature performance of the detector. In recent years RF detection technology has made large strides in creating devices with responses that are very stable over temperature (better than ±.5dB from –40°C to +85°C). Figure 2 shows the temperature performance of the AD8364 dual RMS-responding power detector. This data was taken at +25°C (black), –40°C (blue), and +85°C (red) @ 450 MHz. It includes voltage and error over temperature (after ambient calibration) vs. input power for at least 30 devices from multiple production lots. Each part behaves slightly dif-ferently over temperature.

The Analog Devices AD8364 output voltage and log confor-mance error vs. Pin (@ 450 MHz) shows very little change when temperature is cycled from –40°C to +85°C. This remains true for 30 devices taken from different produc-tion lots, even though the per-

formance is slightly different over temperature.

It is not only essential to accurately measure an HPA’s maximum output power, but it is also necessary to measure the output power over the entire transmit power range of the HPA, though the accu-racy at lower power levels is sometimes not as critical. However, the accuracy of mea-suring over a large dynamic range is related to both the detector and the ADC resolu-tion. Figure 3 shows the out-put of two RMS-responding detectors, the AD8364 and ADL5500. The ADL5500 is linear in RMS volts to the input RF signal, and the AD8364 is linear in RMS power (dB) to the input RF signal. Based on the requirements for dynamic range and accuracy at lower power levels, the required res-olution of the ADC used with the ADL5500 could be much greater than it would be for the AD8364. System require-ments will dictate which detector/ADC will provide the most cost-effective and easiest-to-implement solution based on accuracy at lower power levels and dynamic range requirements.

A comparison of a detec-tor whose output is linear to the input RMS power in dBm (Analog Devices AD8364) to a detector whose output is linear to the input RMS volts (Analog Devices ADL5500) shows the difference in dynamic range and emphasizes the necessity of choosing an ADC with the proper resolution.

In some instances, accurate-ly controlling the power or gain of a system using an ana-log feedback loop can improve the performance and replace simple power detection. Many currently offered detectors can control power using an analog feedback loop (i.e. a detector used in Controller Mode) in addition to detecting it. If an RMS-responding detector is used in Controller Mode, power can be set very accurate-ly vs. input power, temperature, and crest factor. This power can be set very accurately, and its level can be changed using an analog voltage controlled by an ADC. Using a power detector in Controller Mode to accurately control the input or output power of an HPA would be an ideal application, as it would remove the need

FEATURE ARTICLE

Figure 3: A comparison of a detector whose output is linear to the input RMS power in dBm (Analog Devices AD8364) to a detector whose output is linear to the input RMS volts (Analog Devices ADL5500) shows the difference in dynamic range and emphasizes the necessity of choosing an ADC with the proper resolution.

Figure 4: In Controller Mode, the detector determines the power at its input and adjusts a VGA (or variable attenuator) until the detected power coincides with the level set by the power control input voltage (VSTA).

Figure 5: When one side of Analog Devices AD8364 dual RMS-responding detector is used to control the power of a sys-tem, the power at the input of the detector (and at Pout) stays constant vs. input power and temperature (less than ±.1 dB).

12

to detect the input or output power. In Controller Mode the detector determines the power at its input and adjusts a VGA (or variable attenuator) until the detected power coincides with the power set by the Power Control input voltage. Figure 4 shows a basic schematic of an RMS-responding detector (AD8364) used in Controller Mode to control the output power. Figure 5 shows the overall cir-cuit performance vs. input power and temperature when the VGA is controlled by one side of an AD8364 (dual RMS-responding log detector). Note that an HPA can be put between the VGA and coupler as long as the power level is set correctly into the AD8364, and that any VGA (or variable attenuator) can be used if the control voltages are set properly between it and the AD8364 (an op-amp may be needed to invert and/or level shift the control voltage). If the control levels between the detector and VGA are set properly and power levels are properly designed, the power control range/usable input power range will be close to the detectable power range of the detector

(60 dB, in the case of the AD8364). In Controller Mode, the detector deter-

mines the power at its input and adjusts a VGA (or variable attenuator) until the detected power coincides with the level set by the power control input voltage (VSTA).

When one side of Analog Devices AD8364 dual RMS-responding detector is used to control the power of a system, the power at the input of the detector (and at Pout) stays constant vs. input power and temperature (less than ±.1 dB).

A dual RMS-responding detector oper-ating in Controller Mode can also be used to control the gain of an HPA very accurately vs. input power, temperature, and crest factor. If the gain of an HPA module is controlled with enough accuracy over input power, temperature, and crest factor, the HPA module’s output power would not have to be reported but would be directly related to the power feeding it. If both inputs of a dual detector are put in Controller Mode, the detector determines the power at each input and adjusts the gain of a VGA until the power detected

on one input is equal to the power on the other. Figure 6 shows a basic schematic of the AD8364 (dual RMS detector) used to control the gain of a system. Figure7 shows the performance of this setup. Everything that needs to be accurately controlled should be included between the two couplers. Note that a VGA, variable attenuator, or even the bias of the HPA can be used to control the gain. If the control levels between the detector and VGA are set properly and power levels are properly designed for, the usable input power range will be close to the detectable power range of the detector (60 dB, in the case of the AD8364).

When both inputs of a dual detector are used in Controller Mode, the detector will control a VGA (or VVA, etc.) in such a way as to equalize the power it detects at both RF inputs. The gain of the system will be determined by the couplers and attenuators used to set the power being detected by the dual detector.

When both inputs of Analog Devices dual RMS detector (AD8364) are put in Controller Mode, the gain is controlled to better than ±.15 dB vs. temperature and input power, with a dynamic range almost equal to the dynamic range of the RMS detector.

Many of the challenges associated with RF power detection for HPAs used in CDMA2000 and W-CDMA systems can be solved using RMS-responding RF detectors. Variations in detected power due to large peak-to-average values that change with base station loading, large operating temperature ranges, and large transmit power ranges are now manage-able. New ways to control power and gain accurately enough to remove the need for detect power are now available. All of these things allow HPA manufac-turers to reduce the cost and improve the reliability of their HPAs.

ANALOG DEVICES

FEATURE ARTICLE

Figure 6: When both inputs of a dual detector are used in Controller Mode, the detector will control a VGA (or VVA, etc.) in such a way as to equalize the power it detects at both RF inputs. The gain of the system will be determined by the couplers and attenuators used to set the power being detected by the dual detector.

Figure 7: When both inputs of Analog Devices dual RMS detector (AD8364) are put in Controller Mode, the gain is controlled to better than ±.15 dB vs. tempera-ture and input power, with a dynamic range almost equal to the dynamic range of the RMS detector.

13

Part

Number

–3 dB

BW

(MHz)

Gain

Low

End

(dB)

Gain

High

End

(dB)

Number

of

Channels

Noise

Figure

(dB)

Supply

Current

@ 5 V

(mA)

Gain

Accuracy

(dB)

OIP3

(dBm)Package

Price

@ 1K

($U.S.)

AD8376 690 –4 20 2 8.7 260 0.2 50 LFCSP 6.49

AD8372 130 –9 32 2 7.8 212 0.2 35 LFCSP 6.50

AD8375 690 –4 20 1 8 130 0.2 50 LFCSP 4.49

AD8370 700 –25 34 1 7 78 – 35 TSSOP 4.20

AD8369 600 –5 40 1 7 37 0.5 19.5 TSSOP 4.20

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Industry’s first digitally controlled dual VGAs:

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ADL5521 and ADL5523 Low Noise Amplifiers

400 MHz to 4 GHz low noise amps with the optimumamount of gain and current consumption.

ADF4360-9 Integrated PLL and VCO with

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ADL5541 and ADL5542 Broadband RF Gain Blocks

Operate from low frequencies up to 6 GHz; 50 internalmatching and bias circuitry reduces external components.

ADL5350 Low Frequency to 4 GHz High Linearity Mixer

Broadband RF, IF, and LO inputs allow it to be specified inboth receiver and transmitter signal paths.

AD6655 IF Diversity Receiver

Mixed-signal IF receiver comprising dual 14-bit, 80 MSPSto 150 MSPS ADCs, and a wideband downconverter.

ADI covers the entire RF signal chainAnalog Devices is the only vendor that offers acomplete portfolio of RF ICs. Optimize performanceand simplify your designs with:

Precise gain control, high IP3, low noise—for a wide

variety of receiver applications

Why use two individual VGAs when the Analog Devices AD8376 digital VGA

gives you dual channels in 67% less space? Analog Devices’ industry-

leading solution offers 50 dBm output IP3 on just 130 mA of current per

channel, providing unparalleled linearity and minimizing distortion. You

can maximize signal level prior to the ADC across a broad choice of IFs

up to 400 MHz, while reducing your footprint with the AD8376’s compact,

5 mm 5 mm 32-lead LFCSP package. For applications requiring

additional gain control range, such as upstream CMTS receivers, ADI’s

AD8372 VGA offers 41 dB of range in 1 dB steps.

For more information about Analog Devices RF VGAs, please call

800-AnalogD or visit www.analog.com/rf-vga.

Dual- and Single-Channel Digital VGAs

14

RF Bonus Feature

23S e m i c o n d u c t o r H i g h l i g h t

www.ECNmag.com • 09/2007

Many different standards forwireless communicationsequipment are in use today.

Narrowband communication standardsuse stronger transmission in a smallslice of bandwidth. Wideband stan-dards use lower transmission poweracross a larger bandwidth. Each stan-dard defines minimum performancecharacteristics for receivers, andincludes specifications such as band-width, maximum signal level, and sensitivity.GSM is one narrowband example; the channelbandwidth is 200 kHz. A GSM receiver musthave a minimum sensitivity of –104 dBm andbe able to tolerate a –13 dBm signal at theantenna. In contrast, CDMA2000 is a wide-band standard that uses a 1.25 MHz band-width. CDMA2000 receivers need to have aminimum sensitivity of –117 dBm/1.25 MHzand tolerate a maximum signal of –30 dBm at900 kHz offset.1

Wideband and narrowband communicationstandards can overlap in the crowded RF spec-trum, making it even more challenging todesign receivers that are immune to interfer-ence. Narrowband receivers can use narrowbandpass filters to remove interference, allow-ing them to amplify and then digitize only thechannel of interest. Unfortunately, designers ofwideband and multicarrier receivers cannot usethis solution, because channel selection is per-formed after the signal is digitized. Therefore,the entire spectrum must be digitized as cleanlyas possible to allow the digital signal processor(DSP) to remove the blockers in the digitalrealm. Wideband receivers must tolerate largenarrowband signals within the band of interestwithout degrading the sensitivity of the receiver.Although they cannot use filters to remove in-band interference, wideband and multicarrierreceivers will use Nyquist filters to remove out-of-band interference.

In the block diagram of a receiver (Figure 1),the analog portion of the receive signal chainconsists of:

• Antenna. Selective to the spectrum ofinterest — this provides some attenuation forout-of-band interference.

• Down-conversion. Translates the receivedsignal to a lower frequency that can be ampli-fied and converted to digital information. Thiscan be accomplished with one or two mixingstages. A single mixer stage can reduce the sig-nal’s center frequency from a few gigahertz to acouple hundred megahertz. A second mixerstage can translate the signal down to tens ofmegahertz. Using a single mixer stage savesboard space and the expense of the secondPLL, VCO, and filter. However, the higher IFrequires an amplifier and analog-to-digitalconverter (ADC) with very good performanceat high frequencies.

• VGA. A variable-gain amplifier is used toadjust the gain of the circuit depending on thereceived signal strength.

• Anti-aliasing filter. Attenuates signals out-side the band of interest.

Large-scale blockers interfere with convert-ing the desired signal in two ways:

1. An ADC’s input range is specified as someamplitude, typically 1V or 2V peak-to-peak orin terms of dBm. This input range limits howmuch gain the VGA can apply to the signalbefore the ADC starts to distort or clip. An rmsdetector or log-amp is frequently used todetermine the amplitude of the composite sig-nal, thus determining how much gain the VGAshould apply in order to use the ADC’s full

input range. Large-scale blockersincrease the amplitude of the receivedsignal, limiting the amount of gain thatcan be applied before saturating theinput of the ADC. In-band blockerseffectively limit the amplitude of thedesired signal. If no blocker was pres-ent more gain could be applied to thesignal to help overcome the noise floorof the ADC.

2) Nonlinearities within the ADCwill create intermodulation distortion productswithin the desired signal band, thus negativelyimpacting spurious free dynamic range (SFDR)performance. Intermodulation distortion occurswhen two frequencies mix together and createsignals at the sum and difference of the input

frequencies. For example, applying two tones tothe input of an ADC where F1=50 MHz andF2=52 MHz, will create new signals at 2 MHz(F1–F2), 102 MHz (F1+F2), 54 MHz (2F2–F1),48 MHz (2F1–F2), and so on. The amplitude ofthese new signals depends on the linearity of theADC and the amplitude of the input signals.The same phenomenon happens when a largein-band blocker mixes with another blocker orthe desired signal. New signals, which can bevery close to the signal of interest, are created.

Simulating the Effect of Blockerson Data Converter Performancein Wideband Receivers

ADCs

by Michael Sink and Pamela Aparo,Analog Devices

Figure 1. Receiver block diagram.

Figure 2. ADC performance comparison between CDMA2000 input andCDMA2000 input with blocker.

15

Knowing these blockers can cause problems inreceiver sensitivity, how does the engineer knowthat a design will meet the required specifications?There are a couple ways to do this (aside from trialand error). The ADC’s signal to noise ratio (SNR)and SFDR performance can be used to calculatethe effect of in-band blockers on a receiver. TheADC performance will be specified for differentsample rates and input frequencies, which maynot match your application. These specificationsare measured with pure sine wave inputs asopposed to the signals received from an antenna.Alternatively, a software package such as AnalogDevices’ (ADI) VisualAnalog can simulate ADCperformance with a real-world waveform and anysample rate.

The tool’s drag-and-drop GUI allows circuitcreation from functional blocks. It can createcomplex waveforms, import waveform data, andcustomize FFT analysis to quickly determine if aspecific ADC will meet the performance specs fora given communication standard. ADI’s ADCmodels account for the effects of clock jitter, tran-sitions between stages inside the part, the drooprate of the sample and hold capacitors of theADC input, and ultimately the SNR and SFDRperformance over frequency and sample rate.Using this tool, ADC performance can be simu-lated with any input signal — including a com-plex waveform like CDMA2000.

Figure 2 shows the results of using a

VisualAnalog canvas to evaluate the AD9246, a14-bit 125 Msps ADC. By creating a signal similarto a CDMA2000 waveform with and without anin-band blocker we can use the tool to analyze the ADC’s performance. This same canvas file(Figure 3) can be easily modified to accept anoth-er waveform (W-CDMA, GSM900) or evaluate adifferent ADC using another ADC model.

ConclusionWideband communication standards such asCDMA2000 require receivers that can toleratelarge in-band blockers. Although it is possible to

calculate the effect of the ADC’s SNR and SFDRon receiver sensitivity, the datasheet may notspecify ADC performance at the desired samplerate and input frequency. New simulation soft-ware makes it possible to quickly and easily eval-uate different ADCs with real-world signals, ulti-mately reducing design risk.

References1 AN-808 “Multicarrier CDMA2000 Feasibility”, BradBrannon and Bill Schofield. ©2006

“Correlating high-speed ADC performance to multi-carrier 3G requirements”, Brad Brannon, RF Design,June 2003, pp. 22-28.

Pamela Aparo is a marketing manager in theHigh Speed Converters Group at Analog Devices,Inc. Pam has worked in marketing and applicationsroles with ADI for seven years. Prior to ADI, sheapplied her engineering degree to medical applica-tions working for Baystate Medical Center and OECMedical Systems. Pam earned a BSEE from theUniversity of Connecticut. Michael Sink is an appli-cations engineer in the High Speed Converters Groupat Analog Devices. He has been with ADI for fiveyears. Michael earned a BSEE from North CarolinaState University. For more information, contactAnalog Devices, One Technology Way, Box 9106,Norwood, MA 02062-9106; (800) 262-5643;www.analog.com.

24 S e m i c o n d u c t o r H i g h l i g h t ADCs

Figure 3. VisualAnalog canvas used to analyze the effect of a blockeron ADC performance.

As seen in the September 2007 issue of ECN magazine

16

20

PartNumber

RF Frequency (MHz)

DynamicRange (dB)

OutputResponse

ResponseTime

Temp Stability (dB)

SupplyVoltage (V)

SupplyCurrent (mA)

Package Comments

AD8361 100 to 2500 30 Linear-in-volts 320 ns 0.25 2.7 to 5.5 1 2.9 mm 2.8 mm, 6-lead SOT-23

Low power, low cost rms detector

AD8362 >0 to 3800 60 Linear-in-dB 45 ns 1.0 4.5 to 5.5 20 5 mm 6.4 mm, 16-lead TSSOP

Wireless infrastructure

AD8363 >0 to 6000 >50 Linear-in-dB 8 s 0.5 4.5 to 5.5 66 4 mm 4 mm, 16-lead LFCSP

Broadband

AD8364 >0 to 2700 60 Linear-in-dB 45 ns 0.5 4.5 to 5.5 70 5 mm 5 mm, 32-lead LFCSP

Dual-channel rms detector

AD45102 50 to 3800 60 Linear-in-dB 45 ns 1.0 4.5 to 5.5 20 5 mm 6.4 mm, 16-lead TSSOP

Operation to 125°C

ADL5501 50 to 4000 30 Linear-in-volts 6 s 0.25 2.7 to 5.5 1.1 2 mm 2 mm, 6-lead SC70

Reduced size, improved temperature stability

TruPwr™ RMS Power Detectors

Features

Industry’s first patented RF true power detectors

Innovative line of TruPwr rms responding detectors with frequency ranges from >dc to 6 GHz

Immune to crest factor changes enabling modulation-independent true power detection

Single- and dual-channel rms detectors with linear-in-volts or linear-in-dB outputs

RF Bonus Feature

to diffract specific wavelengths oflight from the incoming spectrum.

DDS devices are excellent RF driversfor exciting crystals within an AOTF,due to the high resolutions attain-able. Precise frequency switching im-plemented by the DDS involves verylittle latency and no settling time.

An on-chip clock multiplier offersphase noise performance sufficientfor AOTF applications, and easy syn-chronization of additional multi-channel chips is possible. Operatingat a maximum system rate of 500Msamples/s, a four-channel DDS de-vice produces output frequenciesfrom dc to 250 MHz in steps of about116 mHz, with each DDS channelconsuming less than 165 mW.

Military systems applicationMilitary communications, electroniccountermeasures, and communica-

tions surveillance applications de-mand exceedingly fast switchingspeeds. Traditionally, the challengehas been to achieve this withoutcompromising frequency resolution.

The AD9910, from Analog Devices,is a 1-Gsample/s DDS with an inte-grated 14-bit DAC. 32-bit frequencytuning translates to 0.23-Hz tuningresolution.

The incredibly fast parallel dataport, used for writing frequency tun-

C O M M U N I C AT I O N S S P E C I A LC O M M U N I C AT I O N S S P E C I A L

D irect digital synthesis (DDS)has come a long way sincethe days when implementa-

tions were limited to complex, cost-ly designs that consumed largeamounts of power. Today’s DDS ICsoffer drastically reduced power dissi-pation and size—as well as greatlyimproved phase noise, spurious per-formance, and ease of use—makingthem attractive alternatives to ana-log synthesis in many communica-tions systems. DDS devices now of-fer many levels of integration,performance, packaging, and costbenefits, allowing customized andeasy selection into new designs.

The primary advantages of using adigital synthesizer over traditionalanalog solutions are fast frequencyhopping, extremely fast switchingspeeds with virtually no settlingtime, finer tuning resolution, andchannel flexibility. Designers requir-ing agile frequency sources with ex-cellent phase noise and low spuriousperformance often choose DDS.

Available DDS ICs now support in-ternal speeds of 1 Gsample/s, pro-vide outputs up to 400 MHz, and in-clude a high-performance 10-, 12-,or 14-bit DAC. With 48-bit frequen-cy tuning, 14-bit phase tuning, and10-bit amplitude scaling, extremelyfine resolution (1 μHz, 0.022°, and 3mV) is attainable.

Once viewed as power-hungrymonsters, some DDS cores nowboast power consumption less than165 mW at 400 Msamples/s. A phasenoise floor below –150 dBc/Hz at upto 100 MHz is possible, and im-provements in wideband SFDR (>55dBc) and narrowband SFDR (80 to

90 dBc) make DDS a more attractivesolution.

I/Q generationFor applications requiring in-phaseand quadrature (I and Q) generation,DDS offers unparalleled matching ofI and Q outputs. By using DDS tosend quadrature signals to the I/Qinputs of an analog modulator, theredundant sideband can be attenuat-ed significantly, relaxing the nor-mally tight filtering requirements.

To further simplify this approach,new two-channel DDS chips provideinherent synchronization acrosschannels while maintaining excellentisolation between them. Independentfrequency, phase, and amplitude con-trol on each channel provides flexibil-ity to correct imbalances betweenquadrature signals. In Fig. 1, two syn-chronous DDS channels generate digi-tal I and Qdata which isthen upcon-verted using amodulator.

OpticalsystemsWith channelbandwidth ata premium inoptical net-working sys-tems, packingmore functionality into a smallerspace is increasingly desirable and asingle-chip, four-channel DDS IC of-fers clear benefits.

Acousto-optics, a technique oftenapplied in optical communicationsystems, uses the relationship be-tween vibrations and light to targetan optical wavelength. During opti-cal transmission, devices such as theacousto-optic tunable filter (AOTF)use a slight adjustment in frequency

Today’s DDS ICs offer drastically reduced power dissipation and size

Improved DDS devices enableadvanced comm systems

69ELECTRONIC PRODUCTS http://electronicproducts.com SEPTEMBER 2006

2-ChannelDDS

AD9958

CH0

AD8349ADL537x

0º/90º +

Data(I)

Data(Q)

Modular

RF out

CH1 LPF

LPF

LO

BY VALOREE YOUNGAnalog DevicesGreensboro, NChttp://www.analog.com

Fig. 1. A two-channel DDS provides precise, synchronous control for in-phase and quadrature data generation.

25

ing word changes, allows the DDS ICto take a 16-bit word every 4 ns. Thedevice offers a 14-bit phase offsetword, a 1,024-element RAM, a linear-sweep block, and other features.

In systems needing to synthesizespecific frequencies with very lowspurious components, a recentlydeveloped implementation usesauxiliary DDS channels to reducethe magnitude of harmonic spurs inthe output spectrum. This spur re-duction approach extends the im-plementation to designs demand-ing better wideband SFDR (spuriousfree dynamic range) performancethan was previously attainable by aDDS.

In fact, a 12-dB improvement of asingle spur can be seen at 200 MHz.The technique is beneficial to cur-rent DDS users in reducing the tire-some task of frequency planningand in eliminating the need for acomplex filter design.

The AD9912 showcases this spurreducing concept, and includes anon-chip comparator for generating asquare wave output for clock genera-tion applications. Extremely finetuning resolution of 3.5 μHz on out-puts up to 400 MHz is made possibleby a 48-bit frequency tuning word.

Cellular base station benefitsIn base station transmit architecturesthat employ a direct-IF approach toupconversion, DDS-based modula-tors offer an alternative to traditionaldual-DAC direct-conversion solu-tions. A quadrature digital upcon-verter (QDUC) integrates a 1-Gsam-

ple/s DDS core, a highperformance 14-bitDAC, clock multipliercircuitry, digital filters,and other DSP func-tions onto a singlechip.

This solution offerscost, power, and spacesavings, while provid-ing excellent dynamicperformance. Figure 2shows architecture op-tions for single analogupconversion usingtwo different ap-proaches.

Implementing aQDUC in the trans-mission path avoids

quadrature phase and amplitude im-balance issues. In addition, only onemixer and one DAC are required, sothe overall noise will be reduced.

The QDUC supports real outputs upto 400 MHz. A 250-MHz 18-bit-widedata input port supports interleaveddata rates as high as 125 Msymbols/s,and innovations in low-power DDScores have brought power down toabout 1 W at 1 Gsample/s.

Portable devicesDesigners of portable and handheldwireless systems should note thedrastic reduction in power consump-tion. DDS ICs consuming less than50 mW are typically offered at fre-quencies of 50 MHz or lower.

Some higher-speed DDS devicesrunning at up to 250 Msamples/s arenow approaching 50-mW power lev-els. These cores are even being usedas auxiliary components, performingtasks such as multitone generationand spur reduction within highly in-tegrated complete DDS devices.

Other communication appsClock generation applications alsoreap the benefits of multipurposeDDS functionality, since the abilityto generate a clean, stable clock is vi-tal in many systems.

As advances in SFDR performanceand power consumption continue,DDS will expand into markets thatwere previously off limits. Its roleas a standalone function willevolve to recognize its potential asa building block in other morecomplex chips. �

COMMUNICATIONS SPECIAL - IMPROVED DDS DEVICES ENABLE ADVANCED COMM SYSTEMS

70 ELECTRONIC PRODUCTS http://electronicproducts.com SEPTEMBER 2006

DSPD/A

DUCfor

multiplecarriers

Antenna

DigitalFiltering

D/A

AmplifierComponents

ClockDistribution PLL/VCO

AD8349ADL537xAD9779

0/90

I

Q

+

DSP

Antenna

D/A AmplifierComponents

ClockDistribution PLL/VCO

AD9857AD9957

0/90

I

Q

+DEMUX Power

RampProfile

Fig. 2. Upconversion schemes can use a dual TxDAC(a) or DDS-based modulator (b).

(a)

(b)

26

RF/MICROWAVE SPECIALRF/MICROWAVE SPECIAL

The term “short-range device” (SRD) refers to a device capable of wireless communications

over a relatively short distance—from just a few centimeters up to a few kilometers. Several wireless stan-dards defining the communications processes for such devices exist, with new standards continuing to evolve.

ConstraintsGovernments impose restrictions on the use of the frequency spectrum. Figure 1 shows the UHF (300-MHz to 3-GHz) ISM unlicensed frequency bands available in different parts of the world.

As the figure shows, no common unlicensed ISM band is available be-low 2.4 GHz, although some RF transceivers will support operation across several of these sub-1-GHz bands. The Analog Devices ADF7020/-1, for example, supports operation from 135 to 950 MHz. Many designs use proprietary com-munications protocols in this fre-quency range.

Despite the inherent range advan-tage of the lower-frequency bands, the global nature of the 2.4-GHz band makes it attractive for many SRD communications protocols such as Bluetooth, WLAN and ZigBee. Ir-respective of the communications protocol used, countries apply addi-tional constraints driven by factors such as safety and quality of perfor-mance; these constraints are required to limit interference between differ-ent equipment. Some examples rele-vant for the 2.4-GHz band are shown in Table 1.

Existing standardsThe various communications proto-cols each offer advantages and disad-vantages, with the optimum choice

BY MARY O’KEEFFEAnalog Devices, Norwood, MAhttp://www.analog.com

New standards provide optimized solutions for the differing needs and priorities of different applications

RF standards for short-range

ELECTRONIC PRODUCTS http://electronicproducts.com NOVEMBER 200727

RF STANDARDS FOR SHORT-RANGE WIRELESS CONNECTIVITY

depending on the application. Blue-tooth, for example, offers data rates up to 3 Mbits/s, whereas 802.11g en-ables data rates as high as 54 Mbits/s and ZigBee is limited to 250 kbits/s.

While 802.11g has the higher data rate, it also has higher cost and high-er power consumption. ZigBee has the advantage of low power con-sumption. It can also support a high number of nodes. For example, Blue-tooth’s maximum of 8 nodes in a net could be a limiting factor in an in-dustrial application.

For sensor applications, where only a limited amount of data must

be transferred and low power con-sumption is of significant value, Zig-Bee appears to have an advantage over Bluetooth or WLAN. For appli-cations such as wireless headsets, the data rate offered by Bluetooth meets the requirements while maintaining a relatively low cost.

The Wibree standard currently in development can operate in a stand-alone mode or as a complement to Bluetooth, offering a lower-power so-lution than Bluetooth and a maxi-mum data rate of 1 Mbit/s. This is a higher data rate than ZigBee, but its range would be shorter than a low-

power ZigBee device. Other factors that differentiate the various stan-dards include latency and resilience.

Developing standardsThe industrial environment is one where resilience is of particular value. The recently ratified Wireless Hart standard is targeted at the industrial space. The SP100 group is also look-ing at a standard for industrial appli-cations.

Both the Wireless Hart standard and the ISA-SP100.11a standard, which is in development, indicate the use of an 802.15.4-compatible ra-

dio. The 802.15.4 radio also consti-tutes the physical layer for the Zig-Bee standard.

While several short-range device standards are already in existence, new standards are continuing to evolve. These are driven by and tar-geted at providing optimized solu-tions for the differing needs and pri-orities of different applications.

Table 1. Worldwide communication standardsRegion Standard Relevant Link

Europe ETSI EN 300 328ETSI EN 300 440

http://www.etsi.org/WebSite/homepage.aspx

USA FCC CFR47 part 15 http://www.access.gpo.gov/nara/cfr/waisidx_04/47cfr15_04.html

Japan ARIB STD-T66 http://www.arib.or.jp/english/

Fig. 1. Several UHF (300-MHz to 3-GHz) ISM unlicensed frequency bands are available in different parts of the world.

For more on RF ICs and RF standards, visit

www.electronicproducts.com/linear.asp

wireless connectivity

28

A BROADBANDI/Q MODULATORFOR BROADBANDRADIO DESIGNS

Modern digital radio transmitter designposes increasing challenges forequipment designers. The ongoing

trend towards increased throughput of data isincreasing the modulation density and carrierbandwidths of transmitted signals. Peak-to-av-erage ratios increase with higher order modu-lation schemes and to maintain good adjacentchannel power ratio (ACPR) while transmit-ting the same rms power level, componentswith lower intermodulation distortion andlower noise must be used.

Baseband, IF and RF bandwidth must beflat across the channel to maintain the spectral

shape of the modulated carrier.Furthermore, if digital pre-dis-tortion techniques are beingused then the higher order har-monics need to be passedthrough the baseband inputsand gain flatness must be main-tained up to the higher orderharmonics of the baseband sig-nal. When a radio transmitterdesign calls for operation over avery wide range of RF frequen-cies the RF gain flatness of theoverall signal chain becomes

critical. Minimizing gain variations in the sig-nal chain over frequency eases the burden ofsignal chain planning and budgeting. This arti-cle focuses on I/Q modulators, which are acritical component in modern transmitters.

A BROADBAND I/Q MODULATORI/Q modulators perform the frequency

translation that mixes the baseband signal tothe desired location in the RF spectrum. AnI/Q modulator consists of a local oscillator(LO) input that is split into in-phase (I) andquadrature (Q) components that are separatedby 90°. These two signals drive separate mixersthat are also driven by I and Q baseband sig-nals. The outputs from both mixers are thensummed to provide a modulated carrier eitherat RF or IF. The ADL5385 contains these ba-sic blocks (see Figure 1) and is able toachieve a wide tuning range that spans five oc-taves (50 MHz to 2.2 GHz) through the use ofan active divide-by-two LO splitter instead ofthe more traditional passive polyphase filter.Its wideband performance can be seen in

ANALOG DEVICES INC.Norwood, MA

IBBN

LOIP

LOIN

QBBP

QBBN

TEMP

Divide-by-2Quadrature

PhaseSplitter

VOUT

IBBP

ENBL

TemperatureSensorBIAS

Fig. 1 The ADL5385 I/Qmodulator’s basic blockdiagram. ▼

Reprinted with permission of MICROWAVE JOURNAL® from the September 2006 issue.©2006 Horizon House Publications, Inc.

29

Figure 2, where the output powerhas a very flat response over the en-tire output frequency range, with a 1dB bandwidth of 1300 MHz. Thisnew modulator is designed to directlydrive a 50 Ω load and also includes anintegrated temperature sensor.

GAUGING SIGNAL QUALITYUSING ERROR VECTORMAGNITUDE

Error vector magnitude (EVM) is ameasure of the quality of modulationof a signal and it is directly affected bythe quadrature and amplitude errorswithin the modulator. The amount ofquadrature and amplitude errors can

be gauged by observing the level ofsideband suppression in a single-side-band spectrum. Figure 2 shows thatthe native uncompensated sidebandsuppression of the ADL5385 I/Q mod-ulator is better than –38 dBc out to900 MHz. This level of sideband sup-pression typically yields EVM perfor-mance that is more than acceptable formost communication standards. Ifhigher performance is required, side-band suppression can be optimized byadjusting the relative gain and phase ofthe baseband signals.

The 64QAM constellation, eye-di-agram and spectrum, shown in Fig-ure 3, was generated using randomdata at 5.056941 MSym/s with a filteralpha of 0.18. This closely mimics thedata rate and modulation for a typicalcable modem head end application.It can be seen that the EVM for thissignal is 0.33 percent rms with aquadrature error of 0.27° and a gainerror of 0.003 dB.

SIGNAL QUALITY VS. POWER LEVEL

Figure 4 shows how ACPR varieswith output power for the same64QAM modulated carrier. The highOIP3 of the ADL5385 I/Q modulatorenables it to achieve high outputpower levels with minimal adjacentchannel leakage. This results in lessgain required in the subsequentstages of the radio.

The displayed performance wasobtained without digital compensa-tion of the baseband data. This,along with the wide RF tuning

range, allows the modulator to beused without factory calibration.This can significantly reduce thetime and effort required for designand manufacturing.

DIVIDE-BY-TWO SPLITTERENABLES BROADBANDOPERATION

Systems such as cable modem headend equipment must be able to dy-namically place carriers anywhere inthe the 40 to 900 MHz range. Tradi-tional modulators that use a passive re-sistor-capacitor polyphase network tosplit the LO into quadrature compo-nents have generally been unable tospan such a wide frequency range.This is because the resistor-capacitornetworks are tuned for a particularcenter frequency and typically have auseful range of just over two octaves.Traditional cable modem headendequipment designs use a two-stage up-conversion. The baseband signal is up-converted using an I/Q modulator toan IF frequency above the cable band,typically around 1100 MHz. This IFsignal is then mixed down into the ca-ble band using a mixer. These solutionsrequire more components and thecomplexity associated with such de-

PRODUCT FEATUREO

utpu

t Po

wer

and

Car

rier

Fee

dthr

ough

(dB

m)

Und

esir

ed S

ideb

and

Supr

essi

on (

dBc)

Output Frequency (MHz)

10

0

−10

−20

−30

−40

−50

−600 400 800 1200 1600 2000

−40°C Output Power+25°C Output Power+85°C Output Power−40°C Carrier Leakage+25°C Carrier Leakage+85°C Carrier Leakage−40°C Undesired Sideband Suppression+25°C Undesired Sideband Suppression+85°C Undesired Sideband Suppression

▲ Fig. 2 Single-sideband performance vs.output frequency from –40° to +85°C.

LO

I

I

I

QQ

Q

D

D

▲ Fig. 5 The ADL5385 modulator’s divide-by-two phase splitter showing theapplied LO at twice that of the desired LOfrequency in the mixer.

AC

PR

(dB

c)

CHANNEL POWER (dBm)

−55

−60

−65

−70

−75

−80−18 −14 −10 −6 −2 2

▲ Fig. 4 64QAM ACPR vs. output power(symbol rate = 5.056941 MSym/s with a filteralpha of 0.18, adjacent channel bandwidth =5.25 MHz).

▲ Fig. 3 The spectrum, constellation and eye-diagram of a 64QAM carrier at 350 MHz.

30

signs increases the design time and ef-fort. System cost and complexity canclearly be reduced if this signal chaincould be simplified to a single-stage di-rect launch architecture.

The ADL5385 overcomes the two-octave limitation of traditional I/Qmodulators by utilizing a divide-by-two LO splitter. This architecture isillustrated in Figure 5, where two D-flip-flops are clocked by an LO signal

and its inversion. In the ADL5385the inversion is achieved by crossingthe polarities of the inputs on one ofthe differential D-flip-flops. The Iand Q signals that drive the mixercores shown in the ADL5385 blockdiagram are generated through thealternate clocking of the D-flip-flopsby the two LO input signals. Close in-spection of the timing diagram on theleft of the figure will reveal that it isimperative that the applied LO signalbe at twice the desired RF outputfrequency and that the duty-cycle ofthat LO signal be exactly 50 percent.Any deviation from 50 percent willdegrade the 90° split and this will inturn degrade sideband suppression.

WIDE BASEBAND BANDWIDTHINCREASES DATA CAPACITY

In single-channel modulation sys-tems, data capacity can be increasedby either using a higher order modu-lation scheme or by using more band-width. Figure 6 shows the normal-ized baseband frequency response ofthe ADL5385. With wider carrierbandwidths, the challenge is to main-tain a flat gain across the bandwidthof the carrier. This ensures that thespectrum is not distorted by gain rip-ple. If the gain ripple is too greatthen precompensation might be re-quired in the digital domain. Thisprocess will require the characteriza-tion of the frequency response ofevery radio and will increase thecomplexity of the design and drive upthe cost to manufacture the radio.

The ADL5385 offers a 0.1 dB base-band gain flatness out to 85 MHz.This means that for most applica-tions, there should be no need to per-form any sort of precompensation.

A SEAMLESS INTERFACE TO BASEBAND I/Q DACS

The ADL5385 is designed to in-terface seamlessly with Analog De-vices’ family of transmit digital-to-analog converters (TxDAC). The in-terface between the two devicestypically involves six resistors and asimple LC filter (see Figure 7). Thefour 50 Ω resistors shunting toground from each of the DAC out-puts provide the 500 mV DC bias forthe ADL5385 baseband inputs whilethe 100 Ω resistor in shunt betweeneach differential pair sets the ACswing of the baseband inputs. Withthis simple interface the need for sin-gle-ended-to-differential or level-shifting amplifiers is eliminated.

PACKAGE, AVAILABILITY,EVALUATION BOARDS

The ADL5385 is packaged in aRoHS-compliant 24-lead LFCSPwith exposed paddle. Samples andevaluation boards are currently avail-able and may be ordered on the com-pany’s web site.

Analog Devices Inc., Norwood, MA (781) 329-4700,www.analog.com.

PRODUCT FEATUREN

OR

MA

LIZE

D B

ASE

BA

ND

FREQ

UEN

CY

RES

PO

NSE

(dB

) 2

1

0

−1

−2

−3

−4

−56 126 246 366 486 606 726 846

BASEBAND FREQUENCY (MHz)

▲ Fig. 6 The ADL5385 baseband section’snormalized frequency response.

AD9779 ADL5385

IBBP

IBBN

QBBN

QBBP

OptionalLow Pass

Filter

OptionalLow Pass

Filter

IOUTA1

IOUTA2

IOUTB1

IOUTB2

▲ Fig. 7 AD9779 and ADL5385 interfaceschematic.

31

32

Part Number

RF Frequency (MHz)

Gain(dB)

OutputP1dB (dBm)

OutputIP3 (dBm)

NoiseFigure (dB)

SupplyVoltage (V)

SupplyCurrent (mA)

Specs@ (MHz)

Package Comments

AD83531 1 to 2700 19.5 9 22.8 5.6 2.7 to 5.5 42 900 2 mm 3 mm, 8-lead LFCSP Gain block

AD83541 1 to 2700 20 5 19.3 4 2.7 to 5.5 23 900 2 mm 3 mm, 8-lead LFCSP Gain block

ADL5320 400 to 2700 17 25.4 45 4 4.75 to 5.25 104 880 4.25 mm 4.6 mm, 3-lead SOT-89

Driver

ADL5321 2300 to 4000 14 25 40 4 4.75 to 5.25 84 2600 4.25 mm 4.6 mm, 3-lead SOT-89

Driver

ADL5322 700 to 1000 20 28 45 5 4.75 to 5.25 320 880 3 mm 3 mm, 8-lead LFCSP Matched driver

ADL5323 1700 to 2400 19.5 28 43.5 5 4.75 to 5.25 320 2140 3 mm 3 mm, 8-lead LFCSP Matched driver

ADL55211 400 to 4000 15 22.5 35 0.82 3.0 to 5.25 65 1950 3 mm 3 mm, 8-lead LFCSP Single LNA

ADL55231 400 to 4000 17.5 22 36 12 3.0 to 5.25 65 1950 3 mm 3 mm, 8-lead LFCSP Single LNA

ADL55301 DC to 1000 17 22 37 3 3.0 to 5.5 110 190 3 mm 2 mm, 8-lead LFCSP Matched IF amplifier

ADL5531 20 to 500 21 20.4 41 2.5 4.75 to 5.25 100 70 3 mm 3 mm, 8-lead LFCSP Matched IF amplifier

ADL5534 20 to 500 19.4 20 40 2.7 4.75 to 5.25 180 190 5 mm 5 mm, 8-lead LFCSP Dual ADL5531

ADL5541 50 to 6000 15 20 44 3.5 4.5 to 5.5 90 500 3 mm 3 mm, 8-lead LFCSPBroadband matched

gain block

ADL5542 50 to 6000 19.5 20.6 46 2.8 4.5 to 5.5 93 500 3 mm 3 mm, 8-lead LFCSPBroadband matched

gain block

ADL55701 2300 to 2400 29 31 — — 3.2 to 4.2 130 2350 4 mm 4 mm, 16-lead LFCSP WiMAX power amplifier

ADL55711 2500 to 2700 29 31 — — 3.2 to 4.2 130 2600 4 mm 4 mm, 16-lead LFCSP WiMAX power amplifier

13 V bias supported.

2NF includes external input match.

RF/IF Amplifiers

Features

Broadband and narrow-band RF/IF amplifiers

High linearity and output power

Fully characterizedover frequency range, temperature and powersupply variation

Internal active bias

Most amplifiers internally matched to 50

Low power consumption

Small footprint packages

RF Bonus Feature

38

C Drivers

PartNumber

Bandwidth @–3 dB (MHz)

Gain(dB)

Distortion2nd (dBc)3rd (dBc)

Output IP3(dBm)

NoiseFigure(dB)

Input Noise(nV/√Hz)

SupplyVoltage (V)

SupplyCurrent

(mA)Package Comments

AD8350-15 900 15 –65/–66(50 MHz)

28(50 MHz) 6.8 1.7 4 to 11 28 3.1 mm 5.05 mm,

8-lead SOIC/MSOP

AD8350-20 700 20 –66/–66(50 MHz)

28(50 MHz) 5.6 1.7 4 to 11 28 3.1 mm 5.05 mm,

8-lead SOIC/MSOP

AD8351 2200(AV = 12 dB) 0 to 26 –79/–81

(70 MHz)31

(70 MHz) 10 2.7 3 to 5.5 28 3 mm 4.9 mm,10-lead MSOP

Gain adjustable withexternal resistor

AD8352 2000 0 to 24 –85/–85(100 MHz)

41(180 MHz) 10 2.6 3 to 5.5 37 3 mm 3 mm,

16-lead LFCSP

Gain adjustable withexternal resistor/ultralow

distortion

AD8375 700 –4 to +20 –85/–88(200 MHz)

50(70 MHz) 8.5 — 4.5 to 5.5 130 4 mm 4 mm,

24-lead LFCSPDifferential input/output

digital gain amplifier

AD8376 700 –4 to +20 –85/–87(200 MHz)

50(70 MHz) 8.5 — 4.5 to 5.5 260 5 mm 5 mm,

32-lead LFCSP

Differential input/output, dual-channel,digital gain amplifier

ADA4937-1/ADA4937-2 1900 Adjustable –84/–91

(70 MHz) — 15 2.2 3.3 to 5 40

Single: 3 mm 3 mm,16-lead LFCSP

Dual: 4 mm 4 mm,24-lead LFCSP

Single-ended input/differential output or

differential input/output;adjustable VOCM

ADA4938-1/ADA4938-2 1000 Adjustable –82/–82

(50 MHz) — 15.8 2.6 5 to 5 37

Single: 3 mm 3 mm,16-lead LFCSP

Dual: 4 mm 4 mm,24-lead LFCSP

Single-ended input/differential output or

differential input/output;adjustable VOCM

Features

Low distortion, fully differential amplifiers

Range of adjustable and fixed gain devices

Drive high resolution (12-bit to 16-bit) analog-to-digitalconverters (ADCs) at high speed (100 MHz)

Small footprint packages, single- and/or dual-supply

RF Bonus Feature

High Frequency AD

5

PartNumber

RF Frequency(MHz)

VGA Range (dB)

I/Q Frequency(MHz)

Phase Error(deg)

AmplitudeError (dB)

NoiseFigure (dB)

P1dB(dBm)

Input IP3(dBm)

SupplyVoltage (V)

Supply Current (mA)

Package

AD8333 DC to 50 N/A N/A 0.1 0.05 7.8 14.5 30 5.0 +44/–20 5 mm 5 mm,32-lead LFCSP

AD8347 800 to 2700 69.5 65 1 0.3 11 –2 11.5 2.7 to 5.5 64 9.8 mm 6.5 mm,28-lead TSSOP

AD8348 50 to 1000 45 75 0.5 0.25 11 13 28 2.7 to 5.5 48 9.8 mm 6.4 mm,28-lead TSSOP

ADL5382 700 to 2700 N/A 500 0.5 0.25 14 13 30 4.75 to 5.25 195 4 mm 4 mm,24-lead LFCSP

ADL5387 50 to 2000 — 240 0.5 0.25 15 14 30 4.75 to 5.25 180 4 mm 4 mm,24-lead LFCSP

Demodulators

Features

Wide frequency range from 50 MHz to 2.7 GHz

On-chip RF and baseband amplifiers

Wide demodulation bandwidth enables most high order modulation formats, including QAM, QPSK, and 8 PSK

Small footprint packages, single supply

Splitters

Features

Ideal for distribution of CATV signals

Differential inputs and outputs

1 dB gain flatness to 865 MHz

25 dB isolation between channels

Part Number I/O Configuration Input:Outputs 1 dB Bandwidth (MHz) Max Gain (dB) CSO (dBc) CTB (dBc) Noise Figure (dB) Package

ADA4302-4 Differential 1:4 900 5.7 –73 –66 4.4 3 mm 3 mm, 20-lead LFCSP

ADA4303-2 Single-ended 1:2 1200 4 –62 –72 4.4 3 mm 3 mm, 12-lead LFCSP




44

RF Bonus Feature

56

Features

RFCMOS mobile TV Tuners and receivers

Low power, low NF, good sensitivity

Smaller package sizes (SoC and SiP solutions)

Suitable for mobile/portable applications

Covers worldwide mobile TV standards:

CMMB/DTMB (China): UHF band

ISDB-T 1seg (Japan, Brazil)

DAB/DAB-IP/T-DMB (Europe, China, Korea)

S-DMB (Korea)

DVB-H (Europe and U.S.)

Mobile TV Tuners

Part Number

Mobile TV Configuration Frequency (MHz)Noise Figure

(dB)1

Sensitivity(dBm)1

Power Consumption (mW)

Package

ADMTV300

T-DMB/DAB/FM

RF88 to 108 (FM),

168 to 245 (Band-III),1450 to 1492 (L-Band)

2 70/70/78(FM/band-III/L-band) 5 mm 5 mm, 32-lead LFCSP

ADMTV315 RF+DemodSoC

88 to 108 (FM),168 to 245 (Band-III),

1450 to 1490 (L-Band)–102 90/90/100

(FM/band-III/L-band)7 mm 7 mm, 144-lead FBGA;

5 mm 5 mm, 75-lead WLCSP (optional)

ADMTV316 RF+DemodDual SoC

88 to 108 (FM),174 to 245 (Band-III) –103 90/180

(FM/T-DMB dual) 9 mm 9 mm, 192-lead FBGA

ITD3020 RF88 to 108 (FM),

174 to 245 (Band-III),1450 to 1592 (L-Band)

2.5/3.5(Band-III/L-Band)

100/100/160(FM/band-III/L-band) 6 mm 6 mm, 40-lead LFCSP

ITD3010 RF 88 to 108 (FM),174 to 245 (Band-III) 2.5 100/100

(FM/band-III) 6 mm 6 mm, 40-lead LFCSP

MTV330 S-/T-DMB/FM Dual RF88 to 108 (FM),

174 to 245 (Band-III),2605 to 2655 (S-Band)

2.5/3.5(T-DMB/S-DMB)

100/100/140(FM/T-DMB/S-DMB) 6 mm 6 mm, 48-lead LFCSP

MTV320 S-DMB RF 2605 to 2655 (S-Band) 3.5 140 5 mm 5 mm, 36-lead LFCSPADMTV340 CMMB RF 2635 to 2660 (S-Band) 6.7 150 5 mm 5 mm, 32-lead LFCSP

ADMTV102 DVB-H/DVB-TCMMB/DTMB RF 171 to 245 (VHF),

470 to 862 (UHF) 2.8 180/200(VHF/UHF) 5 mm 5 mm, 32-lead LFCSP

ADMTV202

ISDB-T

RF 470 to 806 (UHF) 2.5 75 2.1 mm 2.1 mm, 23-lead WLCSP

ADMTV203 RF 90 to 222 (VHF),470 to 806 (UHF) 2.5 75 2.1 mm 2.1 mm, 23-lead WLCSP

ITD2010 RF 90 to 222 (VHF),470 to 770 (UHF) 4 100 6 mm 6 mm, 40-lead LFCSP

MTV211 RF + Demod SiP 470 to 806 (UHF) –109 140 9 mm 9 mm, 46-lead LGA

1Numbers for typical value in center frequency.

RF Bonus Feature

60

Logarithmic Amplifiers

Part Number

RF Frequency (MHz)

DynamicRange (dB)

Temp Stability (dB)

ResponseTime (ns)

SupplyVoltage (V)

SupplyCurrent (mA)

Package Comments

AD8302 >0 to 2700 60 1.0 60 2.7 to 5.5 19 5 mm 6.4 mm, 14-lead TSSOP Dual-channel gain and phase detector

AD8306 5 to 400 100 1.0 73 2.7 to 5.5 16 10 mm 6.2 mm, 16-lead SOP Military-specified part available

AD8307 DC to 500 92 1.0 400 2.7 to 5.5 8 5 mm 6.2 mm, 8-lead SOIC/DIP High dynamic range

AD8309 5 to 500 100 1.0 67 2.7 to 6.5 16 5.1 mm 6.5 mm, 16-lead TSSOP Amplitude and limiter outputs

AD8310 DC to 440 100 1.0 15 2.7 to 5.5 8 3.1 mm 4.9 mm, 8-lead SOIC Low cost, high dynamic range

AD8313 100 to 2500 70 1.25 40 2.7 to 5.5 14 3 mm 4.9 mm, 8-lead SOIC Industry standard

AD8314 100 to 2700 45 1.0 70 2.7 to 5.5 4.5 2 mm 3 mm, 8-lead SOIC/LFCSP Industry standard

AD8317 1 to 10,000 55 0.5 6 3.0 to 5.5 22 2 mm 3 mm, 8-lead LFCSP Smaller package, lower cost version of the AD8318

AD8318 1 to 8000 70 0.5 10 4.5 to 5.5 68 4 mm 4 mm, 16-lead LFCSP High accuracy, fast responding

AD8319 1 to 10,000 45 0.5 6 3.0 to 5.5 22 2 mm 3 mm, 8-lead LFCSP Pin-compatible with AD8317

ADL5513 1 to 4000 75 0.5 <20 3.0 to 5.5 30 3 mm 3 mm, 16-lead LFCSP Next-generation AD8313

ADL5519 1 to 10,000 62 0.5 6 3.3 to 5.5 56 5 mm 5 mm, 24-lead LFCSP Dual-channel version of the AD8317

Features

Wide frequency range from dc to 10 GHz

Superior accuracy, better than 0.2 dB and wide dynamic range up to 100 dB

Available with both log and limiter outputs, single and dual channel

Wide range of package options to save board space in RF designs

RF Bonus Feature

FEATURE

14 • www.PlanetAnalog.com March 27, 2006

bbyy CChhrriiss CClloonniinnggeerr,, Analog Devices

CCoonnvveerrtteerrss ffoorr 33GG aarree ooppttiimmiizzeeddffoorr ccoosstt,, ssiizzee aanndd ppoowweerr

Industry demand

for lower-cost

systems and an

ever-increasing

array of features

have caused

designers to shift

their priorities.

A s communications systems haveevolved from second-generation (2G)standards to third-generation (3G)

standards, the performance requirements ofthe analog-to-digital converters (ADCs) anddigital-to-analog converters (DACs) used havealso evolved. In original 2G basestations,designers often selected the highest-perform-ance converters available to provide as muchsystem margin as possible and improve man-ufacturability. This also allowed the manufac-turer to differentiate its basestation with aperformance advantage over its competitors—for example, a higher receive sensitivity.

Focus on costThis is not usually the case with 3G designs,however. Industry demand for lower-costsystems and an ever-increasing array of fea-tures have caused designers to shift theirpriorities. Instead of focusing solely on per-formance, they are now focusing first onother system-enhancing elements, such ascost, power, size and integration, and sec-ondarily on performance. This article willexplore the transition from the highest-per-formance converters in 2G systems to thesmall, low-cost, low-power, highly integratedconverters needed for 3G platforms.

As early 2G/2.5G systems were designed

and deployed in the late '90s and early2000s, many designers needed state-of-the-art converters to address the performancerequirements for these systems. At that time,the highest available performance was foundin the AD6645 14-bit, 80-MSPS pipelinedADC, which was designed on a bipolarprocess and consumed 1.5 watts. Similarly,the best-performing 14-bit, 100-MSPS DACswere based on bipolar or BiCMOS technolo-gies and consumed more than 500 mW.Although this level of performance wasrequired for early-generation systems, thedevices represented leading-edge technology,so they tended to be somewhat costly.

As time has passed, the cost of the con-verter technology has decreased. Since thattime, there are at least three 14-bit, 125-MSPS ADCs that dissipate less than 800 mW.With the introduction of these new competi-tive devices, the price of high-performancehas decreased by at least 50 percent.Although these new devices do not equal theperformance of the higher-power ADCs, theydo offer extremely good performance at lessthan half the power of the first-generationdevice. The latest CMOS DACs, such as theAD9707, dissipate a mere 60 mW at 175MSPS and outperform their BiCMOS cousins.

The first-generation ADCs were designedon a bipolar process, and thefirst-generation DACs weredesigned using 0.6-micronBiCMOS technologies. Thecurrent generation of convert-ers is designed using 0.18-micron CMOS technology.This allows for much smallerdie size, increased feature setsand lower power dissipation,all of which allow semiconduc-tor manufacturers to supportan overall lower cost struc-ture. This benefit gets passedon to the end customer.

Power dissipationAt first glance, power dissipa-

Figure 1: ADC powerconsumption has

decreaseddramatically during

the last decade.

The transition from 2G to 3G standards also means that ADC power andperformance specifications have changed as well.

61

FEATURE


tion would seem somewhat insignificant in acellular basestation, especially when consid-ering that the power amplifiers (PAs) canoutput 40 watts. As basestation OEMs arelooking to reduce cost, however, they arelooking everywhere. In particular, somebasestation deployments are now occurringat the top of towers directly connected to thePA itself. The advantage to this type ofbasestation is that it does not need to com-pensate for the cabling losses normally asso-ciated with putting the transceiver at thebottom of the cellular tower.

However, when a system is mounted atthe top of the tower, no active cooling is pos-sible, while the temperature must be kept aslow as possible because there is a log-linearrelationship between temperature and MTBF(mean time between failures). In addition to

the cost of active cooling, OEMs are attempt-ing to save money in the mechanicals of thebasestation. Higher-power converters with-out active cooling require the mechanicalunit in which the transceiver is housed to bemore complex and more expensive in orderto dissipate the heat efficiently.

Converter manufacturers have addressedpower concerns through advances in processtechnology and architectural changes. Asmentioned previously, the latest ADCs andDACs are being designed in fine-line CMOStechnologies. This greatly reduces switchingtransients in the logic cells. In some cases,

dynamic logic elements are employed, fur-ther reducing switching transients by usinga parasitic capacitance to store the logicstate. In the case of ADCs, the architecturehas transitioned from pure flash to pipelinedsingle- and multibit converters, greatlyreducing the number of comparatorsrequired and hence the overall power. Thedata in Figure 1 demonstrates the dramaticdecrease in power consumption for 12-bitand 14-bit ADCs during the last decade.

SizeLike power dissipation, size has become amajor factor in determining the best convert-er for an application. In deployments suchas the tower-mounted system mentionedabove, OEMs are not only limited on power,but are also trying to implement more carri-

ers on the same form factor that orig-inally supported a single sector of abasestation. This increased densityallows operators to deploy more car-riers and thus support more users inheavily populated areas.

In addition to simply reducing the actual size of the converters,another trend is increasing integra-tion. Digital-to-analog converters nowinclude extensive digital signal pro-cessing, such as interpolating filters,complex modulation, inverse sinc filters and numerically controlledoscillators (NCOs). For ADCs, integra-tion has included adding NCOs anddecimating filters to improve per-formance. Both interpolating filtersfor DACs and decimating filters forADCs have the added benefit ofreducing the high-speed switchingnoise between the converter and thedigital logic.

While it may not be obvious, new-generation converters have also

reduced size by enabling simpler architec-tures. In particular, new low-power, high-performance DACs now make direct-conver-sion architectures feasible. In early genera-tions, a low intermediate frequency (IF) wasused, and then multiple mixer stages wereused to achieve the proper RF signal, Figure2a. By removing multiple mixers and ampli-fiers from this signal chain, as shown in Figure 2b, a significant size and costadvantage can be realized.

Although direct conversion has not yetbeen realized for basestation receivers, theIF-sampling capability of many A/D convert-

Figure 2a: Traditionalsuperheterodyne

architecture

62

FEATURE


ers has been greatly improved. It is now pos-sible to IF sample at up to 450 MHz andmaintain very good performance. That willallow the removal of a single mixer stage andagain reduce overall system cost.

PerformanceAlthough performance is still an importantfactor, it is no longer the first priority formost designers. As the number of competi-tors in the converter space has increasedover the last five to seven years, the numberof basestation suppliers has also increased.This, in conjunction with the high price paidby operators for 3G licenses, has led toincreased cost pressure for all basestationOEMs. It is this cost pressure that hasforced many designers to look at convertersthat just meet the system requirementsinstead of paying the price premium for thehighest performance converters. The goodnews for many designers, though, is that itis easier to meet many of the 3G (W-CDMA)converter requirements for the 2,100-MHzband than those of the GSM 900-MHz band.For example, a 12-bit, 65-MSPS ADC and14-bit, 65-MSPS DAC can meet the require-ments for a two-carrier W-CDMA system,and a 14-bit, 65-MSPS ADC and 14-bit, 125-MSPS DAC can meet the requirements of athree- to four-carrier system. On the otherhand, only a small number of ADCs andDACs can meet the requirements for themulticarrier GSM 900-MHz band. These, asnoted, represent leading-edge technologyand thus carry a price premium. Multicarrierand multistandard architectures utilizing

leading-edge converters can lower overalldevelopment and manufacturing costs byreducing the number of design variantsrequired, but that must be weighed againstthe higher bill-of-materials cost.

ConclusionIt's clear that the driving force behind choos-ing a converter for a basestation design is toremove cost from the system. Cost is mani-fested in many subtle ways, including powerdissipation, size and performance. Theseattributes affect choices such as systemarchitectures, number of carriers and evendeployment locations. This shift in thinkingis driving many converter manufacturers tointroduce parts that meet as many of thesedimensions as possible. Since it's very diffi-cult to meet every attribute with a singledevice, a broad product portfolio offers thebest chance of providing the right converterfor the specific radio architecture and per-formance requirements. ■

Chris Cloninger joined Analog Devices Inc. in 1995 after receivinga bachelor’s degree in computer engineering from ClemsonUniversity. He is a mixed-signal marketing/systems engineer forhigh-speed analog/digital converters for wireless infrastructureand can be reached at [email protected].

Figure 2b: A direct-conversion architec-ture reduces compo-nent count and cost

compared with a tra-ditional superhetero-

dyne architecture.

For more informationPlanet Analog: monthly in print, plus muchmore on the Web at www.planetanalog.com,covering all things "analog" (includingpower, too)ON

THE

WEB

63

64

Variable Gain Amplifiers

Features

Wide selection of VGAs with frequencies ranging from dc to 3 GHz

Wide dynamic range up to 60 dB

Analog or digital, choice of gain control suited for your applications

Differential or single-ended I/O

Part Number

ControlType

Bandwidth (MHz)

Gain(dB)

GainAccuracy

(dB)

Output IP3

(dBm)

NoiseFigure (dB)

InputNoise

(nV/√Hz)

Supply Voltage

(V)

Supply Current


AD603 Analog DC to 90 –11 to +31, +9 to +51 0.5

15 (40 MHz) 8.8 1.3 4.75 to

6.3 12.5 5 mm 6.2 mm,8-lead SOIC/DIP Single-ended input/output

AD604 Analog DC to 40 0 to +48, +6 to +54 0.3

35 (10 MHz) 8.4 1.8 5 64 8.2 mm 7.8 mm,

24-lead SSOP/SOIC/DIP Single-ended input/output

AD605 Analog LF to 40 –14 to +34, 0 to +48 0.2

33 (10 MHz) 8.4 1.8 5 36 10 mm 6.2 mm,

16-lead SOIC/DIP Single-ended input/output

AD8260 Digital LF to 180 –6 to +24 1.2542

(10 MHz) — 2.4 3.3 to 5

28.2 5 mm 5 mm, 32-lead LFCSP Single-channel transceiver

AD8330 Analog DC to 150 0 to +50 0.527

(10 MHz) — 5.0 2.7 to 6 20 3 mm 3 mm, 16-lead LFCSP/QSOP Differential input/output

AD8331 Analog LF to 120 –5 to +43, +7 to +55 0.3

33 (10 MHz) 4.2 0.8 4.5 to 5.5 25 9 mm 8.75 mm,

20-lead QSOPSingle-ended input LNA/

differential output

AD8332 Analog LF to 100 –5 to +43, +7 to +55 0.3

32 (10 MHz) 4.2 0.8 4.5 to 5.5 58 5 mm 5 mm, 28-lead

TSSOP, 32-lead LFCSPSingle-ended input LNA/

differential output

AD8334 Analog LF to 100 –5 to +43,+7 to +55 0.3

32 (10 MHz) 4.2 0.8 4.5 to 5.5 116 9 mm 9 mm,

64-lead LFCSPSingle-ended input LNA/

differential output

AD8335 Analog DC to 85 –10 to +38, –2 to +46 0.2

31 (10 MHz) 7.0 1.3 4.5 to 5.5 76 9 mm 9 mm,

64-lead LFCSPSingle-ended input/differential output

AD8336 Analog DC to 100 –14 to +46,0 to +60 0.3 — — 3.1 3 to

12 150 4 mm 4 mm, 16-lead LFCSP Single-ended input/output

AD8337 Analog DC to 280 0 to +24 0.2528

(45 MHz) 14 2.2 2.5 to 5

15 3 mm 3 mm,8-lead LFCSP Single-ended input/output

AD8367 Analog DC to 500 –2.5 to +42.5 0.2

36.5 (70 MHz) 6.2 1.9 2.7 to 5.5 26 5.1 mm 6.5 mm,

14-lead TSSOPSingle-ended input/output

VGA/AGC operation

AD8368 Analog LF to 800 –12 to +22 0.433.7

(70 MHz) 9.5 1.3 4.5 to 5.5 60 4 mm 4 mm, 24-lead LFCSP

Single-ended input/outputVGA/AGC operation

AD8369 Digital 0.001 to 600 –5 to +40 0.5

19.5 (70 MHz) 7.0 2.0 3 to 5.5 37 5.1 mm 6.4 mm,

16-lead TSSOP Differential input/output

AD8370 Digital 0.001 to 700

–11 to +17, +6 to +34 0.5

31 (70 MHz) 7.4 2.1 2.7 to 5.5 78 5.1 mm 6.4 mm,

16-lead TSSOP Differential input/output

AD8372 Digital 1 to 130 –9 to +32 — 35 (65 MHz) 7.9 1.7 4.5 to 5.5 106 5 mm 5 mm,

32-lead LFCSPDifferential input/output,

dual-channel

AD8375 Digital 700 –4 to +20 — 50 (70 MHz) 8.5 1.9 4.5 to 5.5 130 4 mm 4 mm,

24-lead LFCSP Differential input/output

AD8376 Digital 700 –4 to +20 — 50 (70 MHz) 8.5 2.0 4.5 to 5.5 260 5 mm 5 mm,

32-lead LFCSP Dual-channel AD8375

ADL5330 Analog 1 to 3000 –34 to +22 1.531

(900 MHz) 7.8 1.3 4.75 to 6 240 4 mm 4 mm, 24-lead LFCSP Differential input/output

ADL5334 Digital 150 to 2400 60 0.2530.5

(1900 MHz) 5.7 — 4.75 to 5.25 250 6 mm 6 mm,

40-lead LFCSPSingle-ended dual 30 dB

attenuators

Supply

RF Bonus Feature

WIMAX STANDARDSIEEE 802.16, the formal specification of

WiMAX, is targeted at providing broadbandwireless access beyond that which is currentlyavailable using IEEE 802.11x (WLAN).802.16-2004 (sometimes called 802.16d), thelatest full revision of the WiMAX standard, fo-cuses primarily on fixed position point-to-point or point-to-multipoint networks. Thestandard defines OFDM modulation, a fre-quency range of 2 to 11 GHz, and data ratesup to 70 Mbps. OFDM modulation in 802.16dutilizes up to 256 subcarriers with bandwidthsfrom 1.25 to 28 MHz. The subcarriers arespaced such that they are orthogonal to eachother, thus reducing signal interference. Thechoice of signal bandwidth can be determinedin multiple ways. The base station can changethe signal bandwidth based on transmissiondistance and signal environment, or networkproviders may determine the bandwidth avail-able to a user, based on various pricing plans.Figure 1 shows a basic diagram of the signalstructure for an 802.16d network.

CARLOS CALVOAND MATTHEW PILOTTEAnalog Devices Inc.Norwood, MA

WiMAX, which offers high speed dataaccess to large geographical areas —covering distances up to 30 km — is

defined by the IEEE 802.16 family of stan-dards. It uses orthogonal frequency divisionmultiplexing (OFDM) to attain the high datarates. Consequently, the composite signal en-velopes of the data bursts have significantpeaks, which cause large modulation crest fac-tors. Accurate measurement and control ofWiMAX signals is challenging, due to the typi-cally high WiMAX crest factors of 12 dB andto its susceptibility to the varying modulationpatterns. As WiMAX users move towards oraway from the base station, the transmitterchanges the waveform composition (or modu-lation) to optimize data speed and receptionreliability. As the waveform changes, the cor-responding crest factor variation introducesRF power measurement errors.

This article describes several methods toaccurately measure and control the power ofWiMAX transmitters. WiMAX transmit signalpaths can employ high dynamic range loga-rithmic amplifiers and accurate rms detectorsto ensure accurate control of the transmittedsignal across changing modulation types andover temperature. Some of the highlightedtopics will cover the difficulties in dealing withchanging crest factors and rapid envelopechanges.

RF POWER DETECTION:MEASURING WIMAXSIGNALS

Reprinted with permission of MICROWAVE JOURNAL® from the September 2006 issue.©2006 Horizon House Publications, Inc.

65

A recent amendment to 802.16-2004 focuses on the OFDMA physi-cal layer. This updated standard,802.16e-2005 (or Mobile WiMAX),introduces specifications that allowfor mobility in a WiMAX network atspeeds up to 75 MPH (120 kPH). Inorder to accomplish this, 802.16e in-creases the number of available carri-ers from 256 to 2048, with the BPSKpilot tones no longer at fixed intervalsduring each data burst. The band-width for each data burst includes1.25, 5, 10 and 20 MHz. It is also pos-sible that additional bands at 3.5, 5.5and 7 MHz will be made available foruse in Europe. While the 802.16dstandard includes specifications forthe entire 2 to 11 GHz band, 802.16efocuses on licensed bands below 4GHz. Figure 2 shows how the databursts for an OFDMA network over-lap in time, as opposed to the individ-ual bursts of OFDM. This addedcomplexity allows for a larger numberof users and handles the necessarycomplexity for a multi-path mobileenvironment. 802.16e also mergesWiBro under this IEEE standard.WiBro, a Korean system for wireless

broadband access, was introduced inFebruary 2002 when the Korean gov-ernment allocated 100 MHz of spec-trum from 2.3 to 2.4 GHz. This bandwas then standardized by the KoreanTelecommunications Technology As-sociation (TTA) in late 2004. WiBrobase stations offer a theoretical datarate up to 50 Mbps and cover a radiusof 1 to 5 km, allowing the use ofportable and mobile Internet deviceswithin the range of a base station.Under 802.16e, WiBro is defined asone of the available system profilesand consists of 1024 subcarriers with-in an 8.75 MHz bandwidth.

As shown in the figures, WiMAX istransmitted using OFDM and is madeup of 256 to 2048 subcarriers, each ofwhich is modulated using BPSK,QPSK, 16QAM or 64QAM. The com-bination of all these subcarriers and dif-ferent modulation schemes results inthe potential for large peaks andtroughs during each signal burst. Intheory, it is possible for these extremesto fall on top of each other causing alarge peak-to-average ratio (PAR) orcrest factor (CF). Variations in data rateand burst length will affect the overallsignal crest factor. This can cause issueseven in the simplestof WiMAX systems.For example, a sys-tem which utilizes256 subcarriers willhave a theoreticalcrest factor of 10log(256) = 24 dB. Inpractice, it is morelikely to only have apeak crest factor of12 dB because theprobability that thephase of every sub-

carrier will add together is very low. Acrest factor of 12 dB still poses signifi-cant design considerations with regardsto the selection of high linearity devices(mixers, modulators, power amplifiers,etc.) in the RF signal chain. BecauseWiMAX systems can be used for non-line-of-sight applications, gain controlof the transmitter is necessary to adjustthe output TX level depending on thechannel quality. It is also necessary toaccurately control the power amplifier’soutput in order to avoid signal clippingand increased distortion. Some systemsemploy crest factor reduction schemes,typically in the digital baseband pro-cessing, to minimize these effects.

RF POWER DETECTION IN THETRANSMIT SIGNAL CHAIN

Figure 3 shows the block diagramof a typical WiMAX transmit signalchain. The transmit signal path con-sists of three consecutive stages: digi-tal baseband processor or digital sig-nal processor, radio and power ampli-fier. A portion of the transmittedsignal is sampled by the directionalcoupler before it reaches the anten-na. The sampled RF power is deliv-ered to the power detector where it isconverted to a DC voltage. The out-put voltage of the power detector isdigitized and fed to the digital signalprocessor (DSP). Once the powermeasurement is available as a digitallevel, a decision is made based on themeasured output power versus thedesired output power. The DSP willadjust the output power using a digi-tal-to-analog converter to drive thesignal path power control, either atthe baseband, radio or power amplifi-er. The RF power management loopwill reach a steady-state once themeasured output power and the de-sired output power are balanced. Atemperature sensor can also be intro-

TECHNICAL FEATURE

Burst bandwidth=1.25 to 28 MHz200 Subcarriers-5.6 to 90 kHz spacing

Frame ControlHeader

8 Fixed PositionBPSK Pilots

Preamble Data Burst #1 Data Burst #2 Data Burst #N

Modulated SubcarriersBPSK, QPSK, 16QAM, 64QAM

▲ Fig. 1 806.16d OFDM data burst and signal spectrum.

Symbol Number

Time

Subc

hann

el N

umbe

r

FCH

Pre

ambl

e

Dow

nlin

k M

ap

Upl

ink

Map

Downlink Burst #4

Downlink Burst #1

Downlink Burst #2

Downlink Burst #3

Downlink Burst #5

Downlink Burst #6

Downlink Burst #7

▲ Fig. 2 806.16e OFDMA data burst.

RF Detector(Log Amp or

TruPWR)

TempSensor

DSP

DIRECTIONALCOUPLER

ANTENNA

PA Radio

▲ Fig. 3 WiMAX transit signal chain with RF power management.

66

duced as an input to the DSP to addtemperature compensation capabili-ties. This RF power managementconfiguration is not limited to a par-ticular application. Both base stationsand subscriber stations alike may in-corporate variations of this same RFpower control system.

There are two basic methods bywhich the RF power detector and theDSP can interact to control the pow-er of the WiMAX burst. The firstmethod, which is similar to the tech-nique used in envelope ramping inGSM applications, shapes the RFburst instantaneously. It uses thefeedback of the detector to shape theenvelope of the RF burst, made up ofthe preamble, frame control headerand data. This envelope shapingmethod requires high speed detec-tors and fast feedback paths. A morecommonly adopted method is that ofoutput power monitoring. Thismethod takes a power measurementduring a burst and adjusts the RFpower accordingly during the subse-quent burst. The power adjustmentsare highly dependent on the linearityof the radio components to scale andshape the RF burst. A single mea-surement of RF output power can beaffected by the high frequency com-ponents in the measured signal,which can manifest themselves as

noise or AC-resid-ual on the detector’sDC output. To miti-gate this effect,multiple measure-ment points can betaken throughoutthe burst to averageout the AC-residualerror.

DETECTOR BACKGROUNDHistorically, diode detectors have

been used in RF power control cir-cuitry to regulate transmitted power.The simple diode circuitry offers asmall dynamic range with poor tem-perature stability. Even with tempera-ture compensation circuitry, a diodedetector can only offer a small detec-tion range with worsening tempera-ture performance at low input powers.

A popular alternative to the diodedetector is the demodulating logarith-mic amplifier (log amp). The log ampoffers an easy to use linear-in-dB RFpower detection response, a wide dy-namic range, temperature stability andnanosecond response times. Thenewest RF power measurement alter-native is the TruPWR rms-respondingdetector, which offers wide dynamicranges and temperature stability. Inaddition, rms detectors are insensitiveto changes in the peak-to-average ra-tios, whereas diodes and log amps areboth waveform dependent.

Each WiMAX application has di-verse power control and RF detec-tion needs. Subscriber stations can bedesigned with dynamic ranges assmall as 30 dB, but are susceptible tosupply power consumption. Base sta-tions have more allowance for powerconsumption, but need to control dy-namic ranges of up to 60 dB. Both,similarly, require temperature stabili-ty for improved accuracy. Only logamps and rms detectors are able tomeet those needs.

LOGARITHMIC AMPLIFIERSThe first detection method to be

looked at is a peak-detecting device,the logarithmic amplifier. A wide va-riety of log amps is available with de-tection ranges from 40 to 100 dB, andfrequencies from DC to 10 GHz. Atypical block diagram of a log amp isshown in Figure 4.

The core architecture of a log ampis a cascaded chain of linear ampli-

fiers. Each amplifier has a gain of 5 to20 dB. The combination of gain andnumber of amplifiers determines thedetection range of the log amp. Theoutput of each amplifier stage is fedinto a full wave rectifier (markedDET). The outputs of each rectifierare summed together, and the sum-mer’s output is applied to a low passfilter to remove the ripple of the rec-tified signal. This yields the logarith-mic output (often referred to as the“video” output), which will be asteady-state DC output for a steady-state AC input signal. It is the band-width of this video output that is par-ticularly important in a WiMAX sys-tem. The wider the video bandwidth,the faster the log amp is able to re-spond to changes in the peak voltage,or amplitude, of the input signal. Thismakes the log amp particularly suitedto accurately keep up with the enve-lope of the WiMAX burst. With re-sponse times as low as 8 ns, log ampscan easily keep up and measure smallperiods of the RF burst, such as thepreamble, which last about 26 μs.

Using a peak-detecting device likea log amp is advantageous when mea-suring the signal power of a waveformat an exact point in time. Because thelog amp is able to track the envelopeof its input, provided the modulationrate is lower than the video band-width of the log amp, the DC outputwill be an instant-by-instant measure-ment of the peak amplitude of the in-put signal. This kind of measurementis useful in a WiMAX system to detecthigh crest factor signals during a burstand make the appropriate adjust-ments in power amplifier biasing orimplement a crest factor reductionscheme in the next burst. Figure 5shows the output voltage and linearityerror of a log amp at various 2.35GHz OFDM modulations, 256 sub-carrier signals with 10 MHz band-width. The error, normalized toQPSK with 3/4 encoding rate, isgraphed on the secondary y-axis,scaled in dB. While the log amp isable to maintain approximately 50 dBof measurement range within ±1 dBor error for each modulation, there isan obvious shift in the intercept of thetransfer function. The intercept is thepoint on the x-axis through which thetransfer function would pass if theoutput voltage could go to 0 V. Thisintercept shift is a byproduct of the

TECHNICAL FEATURE

INHI

INLO

V I

I V

SETPOINT

OUTPUT

DET DETDETDETΣ

▲ Fig. 4 Basic block diagram of a logarithmic amplifier.

OU

TPU

T (V

)

LINEA

RITY ER

RO

R (dB

)

INPUT (dBm)

2.0

1.6

1.2

0.8

0.4

0

5

3

1

−1−3−5−60 −50 −40 −30 −20 −10 0

CW16QAM 1/2BPSK16QAM 3/4

QPSK 1/264QAM 2/3QPSK 3/464QAM 3/4

▲ Fig. 5 Log amp output voltage andlinearity error at various 2.35 GHz OFDMmodulations.

67

successive detection architecture of alog amp. The amount of interceptshift is based on the crest factor of thesignal. Because the log amp behavioris repeatable over manufacturingprocess variations, the intercept shiftof the log amp for a sine wave versus amodulated input signal can be easilycharacterized. The DSP can then usean offset correction to compensate forthe detector’s output voltage and yieldaccurate RF power measurement.

The low power consumption, of theorder of 15 to 30 mA, makes log ampsviable in both base stations and sub-scriber stations alike. The well-estab-lished log amp architecture offers ex-cellent temperature stability acrosslarge dynamic ranges as well as fast re-sponse times for burst tracking andpeak sampling. However, as the peak-

to-average ratio of the RF signal varies,the output response of a log amp willalso vary. This introduces an uncertain-ty that in many cases must be compen-sated for by the DSP.

RMS-RESPONDING DETECTORSUnlike diodes and log amps, mean

power detectors (or rms detectors)have responses which are indepen-dent of waveform. The waveform-in-dependence is particularly useful asWiMAX systems optimize the qualityof the link by dynamically adjustingthe signal modulation. The compositesignal envelopes of the data burstsmay have significant peaks that candrastically change over time andthrow off measurement accuracy. Us-ing log amps in the RF power controlsystem require some method of com-

pensation; however,rms detectors sim-plify the complexityof the system by re-ducing and in somecases eliminatingc o m p e n s a t i o nschemes.

Figure 6 showsthe block diagramof a 30 dB rms de-

tector. It achieves independencefrom peak-to-average ratios by com-puting the square, mean and rootfunctions of an rms calculation. TheRF input is fed to one of two identi-cal squaring-cells. The squared signalis then averaged through a low passfilter network. The signal is fed to ahigh gain error amplifier that has thesecond squaring-cell in its feedbackpath. This feedback loop performsthe square-root function, thus com-pleting the rms calculation. The out-put is a linear-responding DC voltagewhose conversion gain has units ofVDC/Vrms. The linear-in-volts rms de-tector is able to operate at frequen-

cies as high as 6GHz. The rms-re-sponding detectorallows the RF pow-er control system tomonitor and dy-namically adjust thetransmitter’s outputpower even as thepeak-to-average ra-tio of the transmit-ted signal changes.Figure 7 illustrates

the accuracy in measuring variousOFDM waveform types. The methodused to calculate the error is similarin nature to that used in the log amperror calculation. The linearity errorof the detector is within ±0.5 dBacross the dynamic range of the de-vice. The various waveforms lie ontop of each other with a deviation of acouple tenths of a dB. This 30 dB dy-namic range and low 1 mA powerconsumption is useful for subscriberapplications. The slower responsetime, in the range of 25 μs, limits therms detector use to output powermonitoring. Figure 8 shows theblock diagram of a 60 dB rms detec-tor, which is appropriate for wider dy-namic range base station applications.The input signal is applied to a 12-step, continuously variable gain am-plifier, which is controlled by the set-point, a logarithmic control voltage.The output of the VGA is fed to anaccurate squaring-cell. The fluctuat-ing output is filtered and comparedwith the output of an identical squar-er. At this point, the square and meanoperations of the rms calculation arecomplete. The output is fed back tothe VGA setpoint, making the outputproportional to the logarithm of therms value of the input. The detectorresponse is linear-in-dB, allowing thedevice to measure RF signals in a 60dB dynamic range. The final step ofperforming the square-root functionis not needed for accurate rms detec-tion. Figure 9 shows the perfor-mance of the 60 dB rms detectorwhen measuring various OFDMmodulated input signals. Again, thevarious waveforms lie on top of eachother with negligible deviation. The

TECHNICAL FEATURE

RFINi

OUTPUT

X2

iX2 Buffer

ErrorAmp

TRANS-CONDUCTANCECELLS

+

−

▲ Fig. 6 Block diagram of a TruPWR rms detector with 3 dB linear-in-volts response.

INHI

INLOOUTPUT

SETPOINT

+

− Σ

X2

X2VTGT

▲ Fig. 8 Block diagram of a linear-in-dB TruPWR rms detector with60 dB dynamic range.

LIN

EAR

ITY

ERR

OR

(dB

)

OU

TPU

T (V)

INPUT (dBm)

3

2

1

0

−1−2−3

10

1

0.1

0.01−25 −20 −15 −10 −5 0 5 10

BPSK16QAM 1/2QPSK 1/264QAM 2/3

QPSK 3/464QAM 3/416QAM 3/4

▲ Fig. 7 Linear-in-volts rms detectoroutput voltage and linearity error at various2.35 GHz OFDM modulations.

LIN

EAR

ITY

ERR

OR

(dB

)

OU

TPU

T (V)

INPUT (dBm)

2.0

1.5

1.0

0.5

0

−0.5

−1.0

−1.5

−2.0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0−60 −50 −40 −30 −20 −10 0 10

CW16QAM 3/4BPSK16QAM 1/2

QPSK 1/264QAM 2/3QPSK 3/464QAM 3/4

▲ Fig. 9 Linear-in-dB rms detector outputvoltage and linearity error at various 2.35GHz OFDM modulations.

68

humps in the linearity error curvecorrespond to the steps of the loga-rithmic VGA. Still, the linearity erroracross the dynamic range stays wellwithin ±0.5 dB. As in the case of thelinear-in-volts detector, the 70 μs re-sponse time of this 60 dB detectoralso limits this detector application tooutput power monitoring.

CONCLUSIONThe emerging WiMAX standard

has great potential to offer wide areacoverage and mobile access to high

speed networks. The large crest fac-tors associated with the OFDM mod-ulation scheme require accurate trans-mit power measurements for PA con-trol and the implementation of crestfactor reduction algorithms. Designsrequiring fast response to the OFDMenvelope should consider the accuracyof log amps. The waveform-indepen-dence provided by rms detectors canreduce, or even eliminate, the needfor compensation schemes in thesenetworks, simplifying the overall de-sign of the transmit chain. ■

Carlos Calvo received his BS and MS degreesin electrical engineering from WorcesterPolytechnic Institute. He is an applicationsengineer in the Advanced Linear ProductsDivision at Analog Devices Inc.

Matthew Pilotte received his BS degree inelectrical engineering from WorcesterPolytechnic Institute. He is an applicationsengineer in the Advanced Linear ProductsDivision at Analog Devices Inc.

TECHNICAL FEATURE

69

70

Mixers/Multipliers

Part Number

RF Frequency (MHz)

IF Frequency (MHz)

LO Frequency

(MHz)

LODrive(dBm)

ConversionGain (dB)

IP3(dBm)

P1dB(dBm)

NoiseFigure(dB)

SupplyVoltage

(V)

SupplyCurrent


AD831 400 200 400 0 0 24 10 10 5 100 10.02 mm 8.38 mm,20-lead PLCC

IF active mixer

AD8342 LF to 500 DC to 350 LF to 850 0 3 24 8.5 12 4.75 to 5.25 97 3 mm 3 mm,

16-lead LFCSPRF/IF active

mixer

AD8343 DC to 2500 DC to 2500 DC to 2500 –10 7 16.5 2.8 14 5 50 5.1 mm 6.5 mm,14-lead TSSOP

RF/IF active mixer

AD8344 400 to 1200 70 to 400 470 to 1600 0 4 24 8.0 11 4.75 to 5.25 90 3 mm 3 mm,

16-lead LFCSPRF/IF active

mixer

ADL5350 LF to 4000 LF to 4000 LF to 4000 4 –6 26 20 6 2.7 to 3.5 16 3 mm 2 mm,8-lead LFCSP

RF/IF passive mixer

ADL5390 20 to 2400 20 to 2400 DC to 230 N/A 5 24 11 21 4.75 to 5.25 135 4 mm 4 mm,

24-lead LFCSPVector multiplier

ADL5391 DC to 2000 DC to 2000 DC to 2000 N/A Variable 29 15.1 — 4.5 to 5.5 130 3 mm 3 mm,16-lead LFCSP

RF/IF multiplier

Features

High linearity active mixers provide conversion gain

Broadband family portfolio with operation up to 4 GHz

Integrated LO driver on-chip

Small footprint packages, single supply

RF Bonus Feature

WIRELESS TECHNOLOGIESWIRELESS TECHNOLOGIES

used to measure gain and VSWR can re-duce overall component count. This articlewill focus on techniques that can be usedto perform these in-situ measurements inwireless transmitters.

A TYPICAL WIRELESS TRANSMITTERFigure 1 shows a typical wireless

transmitter. It consists of mixed-signalbase band circuitry, an up-converter(which generally includes one or moreintermediate frequencies or IFs), ampli-fiers, filters and a power amplifier. Thesecomponents may be located on differentPCBs or may even be physically separat-ed. In the example shown, an indoor unitis connected to an outdoor unit with a ca-ble. In such a configuration, both unitsmay be expected to have well defined,temperature-stable gains. Alternatively,each unit might be expected to deliver awell-defined output power. There are twodifferent approaches to the ultimate goalof delivering a known power level to theantenna: power control or gain control.

With power control, the system relies onbeing able to precisely measure the outputpower (using detector D in this example).Once the output power has been mea-sured, the gain of some component in the

Measurement and control of gain andreflected power in wireless trans-mitters are critical auxiliary func-

tions that are often overlooked. The powerreflected back from an antenna is speci-fied using either the voltage standingwave ratio (VSWR) or the reflection coeffi-cient (also referred to as return loss). PoorVSWR can cause shadowing in a TVbroadcast system as the signal reflectedoff the antenna reflects again off the pow-er amplifier and is then rebroadcast. Inwireless communications systems, shad-owing will produce multi-path-like phe-nomena. While poor VSWR can degradetransmission quality, the catastrophicVSWR that results from damage to coaxialcable or to an antenna can, at its worst,destroy the transmitter. The gain of a sig-nal chain is measured and controlled aspart of the overall effort to regulate thetransmitted power level. If too much ortoo little power is transmitted, the resultwill be either violation of emissions regu-lations or a poor quality link. The reflec-tion coefficient is calculated by measuringthe ratio between forward and reversepower. Gain, on the other hand, is calcu-lated by measuring input and output pow-er. The high commonality of hardware

Measuring VSWRand Gain in Wireless

SystemsEAMON NASH

Analog Devices, Wilmington, MA

Reprinted with permission of MICROWAVE JOURNAL® from the November 2005 issue.©2005 Horizon House Publications, Inc.

71

WIRELESS TECHNOLOGIES

system (in this case, it might be theIF VGA) is varied until the correctoutput power is measured at theantenna. It is not necessary toknow the gain of the circuit or theexact input signal amplitude; it isjust a matter of varying the gain orinput signal until the output poweris correct. This approach is often(incorrectly) referred to as auto-matic gain control or AGC. To becorrect, it should be referred to asautomatic power control or APCsince it is power not gain that is be-ing precisely regulated.

Gain control takes a differentapproach. Here, at least two powerdetectors are used to precisely reg-ulate the gain of the complete sig-nal chain or a part thereof. A pre-cise input signal is then applied tothe signal chain. A number of fac-tors ultimately determine whichapproach is used. Power controlrequires only one power detectorand makes sense in a non-config-urable transmitter whose compo-nents are fixed. For example, pow-er could be measured at the outputof the RF HPA but adjustments

would be made using the IF VGA.Gain control, on the other hand,may make more sense in a recon-figurable system whose compo-nents come from different vendors.In the example, the input powerand output power of the HPA arebeing measured (using detectors Cand D) so the gain can be regulat-ed independent of the other blocksin the circuit. Note that the pow-er/gain control loops can be allanalog or microprocessor based.Gain control would be less practi-cal in the example since the two re-quired detector signals (detectorsA and D) are physically remotefrom one another. A more practicalapproach would be to indepen-dently control the gain of the in-door and outdoor units.

RF DETECTORSUntil recently, most RF power

detectors were built using a tem-perature-compensated half-waverectifying diode circuit. These de-vices deliver an output voltagethat is proportional to the inputvoltage over a limited dynamic

range (typically 20 to 30 dB). As aresult, the relationship betweenoutput voltage and input powerin dBm is exponential (see Fig-ure 2). While the temperaturestability of a temperature-com-pensated diode detector is excel-lent at high input powers (+10 to+15 dBm), it degrades significant-ly as the input drive is reduced. Alog detector, on the other hand,delivers an output voltage pro-portional to the log of the inputsignal over a large dynamicrange (up to 100 dB). The temper-ature stability is usually constantover the complete dynamicrange. A log-responding deviceoffers a key advantage in gainand VSWR measurement applica-tions. In order to compute thegain or the reflection loss, the ra-tio of the two signal powers(either OUTPUT/INPUT orREVERSE/FORWARD) must becalculated (see Figure 3). Ananalog divider must be used toperform this calculation with alinear-responding diode detector,but only simple subtraction is re-quired when using a log-responding detector (since log(A/B) = log (A) – log (B)). A dualRF detector has an additional ad-vantage compared to a discreteimplementation. There is a natur-al tendency for two devices (RFdetectors in this case) to behavesimilarly when they are fabricat-ed on the same silicon wafer.Both devices will have similartemperature drift characteristics,for example. At the summingnode, this drift will cancel to yielda more temperature-stable result.

GAIN MEASUREMENTEXAMPLE

Figure 4 shows a transmitterwhose gain is regulated using adual power detector. The simplifiedtransmit signal chain shown con-sists of a high performance IF-syn-thesizing DAC, a VGA, a mixer/up-converter and a high power ampli-fier. High performance DACs, suchas the AD9786 and AD9779 thatrun at sampling frequencies up to500 MSPS and beyond, are capableof synthesizing intermediate fre-quency outputs (100 MHz in thisexample). The output of the DAC is

Mixed Signal (ADCs/DACs) and μProcessor/DSP

IFVGA

IFAMP

RFAMP HPA

Σ

DAC

SAW BPF

DETA

DETB

DETC

DETD

INDOOR UNIT OUTDOOR UNIT

▲ Fig. 1 Power control versus gain control.

OU

TPU

T V

OLT

AG

E (V

)

INPUT POWER (dBm)

2.5

2.0

1.5

1.0

0.5

0 -70 -60 -50 -40 -30 -20 -10 0 10 20

Diode DetectorLog Detector

▲ Fig. 2 Transfer functions of diodeand log detectors.

DIODE DETECTOR

Pin A Pin B

Vout = Vin A/Vin B

= Gain(V/V)

LOG DETECTOR

Pin A+ -

Pin B

Vout = log(Pin A) - log(Pin B)

= log(Pin A/Pin B)= Gain(dB)

� �Σ

▲ Fig. 3 Calculating the gain usingdiode and log detectors.

72

WIRELESS TECHNOLOGIESNyquist filtered using a bandpassfilter before being applied to anADL5330 variable gain amplifier.Conveniently, the amplifier acceptsa differential input that can be tieddirectly to the output of the differ-ential filter. This, in turn, is tied tothe DAC output. The VGA outputis converted from differential tosingle-ended using a balun trans-former, and is then applied to theADL5350 mixer. After appropriatefiltering (not shown), the signal isamplified and transmitted at amaximum output power level of 30 W (approximately +45 dBm).

The gain of the signal chain ismeasured by detecting the powerat the DAC output and at the out-put of the HPA. The gain is thenregulated by adjusting the gain of aVGA. At the DAC and PA outputs,a sample of the signal is taken andfed to the detectors. At the HPAoutput, a directional coupler isused to tap off some of the powergoing to the antenna. The transferfunction of the AD8364 dual detec-tor (see Figure 5) shows that at theoutput frequency used (2140 MHzin this case), the detector has thebest linearity and the most stabletemperature drift at power levels

below –10 dBm. Thus, the powercoming from the directional cou-pler (+25 dBm max) must be atten-uated before being applied to thedetector. If maximizing the detec-tor dynamic range is not critical tothe application, the attenuation canbe conservatively set at 41 dB sothat the detector sees a maximuminput power of –16 dBm. This stillleaves about 34 dB of useful dy-namic range over which the gaincan be controlled. To detect the in-put power level at the DAC output,a directional coupler is impracticalat this low frequency. In addition,directional coupling is not neces-sary since there will be little or noreflected signal at this point in thecircuit. Furthermore, the powerbeing delivered to the VGA is –10dBm, so the power to be deliveredto the detector is only 6 dB lower.Since the detector has an input im-pedance of 200 Ω and the VGA hasan input impedance of 50 Ω, itquickly becomes clear that the twodevices can simply be connected inparallel. With the same voltagepresent at both inputs, the 50 to200 Ω impedance ratio will result ina convenient 6 dB power differ-ence. Where high measurement

precision is required, care must bepaid to the temperature stability ofthe power detectors. This issue isfurther complicated if the tempera-ture drift characteristics of the de-tectors change with frequency. Thedual detector shown provides tem-perature compensation nodes. Thetemperature compensation is acti-vated by connecting a voltage tothe ADJ pins of each detector (thisvoltage can be conveniently de-rived using a resistor divider fromthe 2.5 V on-chip reference). Nocompensation is required for thelow frequency input (ADJB isgrounded), while a 1 V compensa-tion voltage is required at ADJA tominimize temperature drift at 2.1GHz. While the focus of the appli-cation circuit is gain measurement,it should be noted that input powerand output power can also be mea-sured. The outputs of the individ-ual detectors are available and canbe separately sampled. Becausethe detectors are log responding,their outputs can be simply sub-tracted to yield gain. This subtrac-tion is performed on chip and thegain result is delivered as a differ-ential voltage. The full-scale differ-ential voltage is approximately ±4V (biased up to 2.5 V) with a slopeof 100 mV/dB. Digitizing with a 10-bit ADC with an LSB size of ~10mV (±5 V full scale), 0.1 dB mea-surement resolution is achievable.

VSWR MEASUREMENTEXAMPLE

A dual log detector can also beused to measure the reflection co-efficient of an antenna. In Figure6, two directional couplers areused, one to measure the forward

IF Synthesizing

DAC60dBVGA

1nF 1.1

Mixer

DirectionalCoupler

+45dBm

41dB

20dB

LO

1nF

1nF

1nF100MHz

100 MHz-10 dBm

50Ω

50Ω

50Ω

DAC

ADC

ADC

μPro

cess

or/D

SP

ADC

OutputPower

InputPower

VSTB

CLPF

VGA Control

VGA Control

ITGT2

ISIG2

IERR

ITGT2

ISIG2

VSTA

CLPF

OUTA

FBKAChannel A

TruPwrTM

Channel BTruPwrTM

FBKB

OUTPOUTAOUTB

Vref

INLA

ADJA

VREF

ADJB

INLBINHB

0.1uF 0.1uF

-16 dBm(max)

0.1uF

1:4

0.1uF

INHA

OUTB

OUTN

Gain

HPA

▲ Fig. 4 Gain control using a dual rms-responding log detector.

GA

IN O

UTP

UT

(V)

CHANNEL A INPUT POWER (dBm)(CHANNEL B = -25 dBm)

543210

-1-2-3-4-5

2.52.01.51.00.50-0.5-1.0-1.5-2.0-2.5

-60 -50 -40 -30 -20 -10 0 10 20

GA

IN E

RR

OR

(dB

)

+85° +25° -40°

▲ Fig. 5 Gain transfer function of adual rms-responding log detector.

73

WIRELESS TECHNOLOGIES

power and one to measure the re-verse power. As in the previous ex-ample, additional attenuation is re-quired before applying these sig-nals to the detectors. The AD8302dual detector has a measurementrange of ±30 dB. The level planningused in this example is graphicallydepicted in Figure 7. In this exam-ple, the expected output powerrange from the HPA is 30 dB, from+20 to +50 dBm. Over this powerrange, reflection coefficients from0 dB (short or open load) up to –20dB should be able to be accuratelymeasured. Each of the AD8302’sdetectors has a nominal inputrange from 0 to –60 dBm. In thisexample, the maximum forwardpower of +50 dBm is padded downto –10 dBm at the detector input.When the HPA is transmitting at itslowest power level of +20 dBm, thedetector sees a power of –40 dBm,still well within its input range.

The power from the reversepath is padded down by the sameamount. This means that the sys-tem is capable of measuring re-flected power up to 0 dB. Thismay not be necessary if the sys-tem is designed to shut downwhen the reflection coefficientdegrades below a certain mini-mum (such as 10 dB), but it ispermissible because the detectorhas so much dynamic range. Forexample, when the HPA is trans-mitting +20 dBm, the reversepath detector will see an inputpower of –60 dBm if the antennahas a return loss of 20 dB. Theapplication circuit provides a di-rect reading of return loss, but noinformation is provided about theabsolute forward or reverse pow-er. If this information is required,the dual detector used in the gaincontrol would be more useful be-cause it would provide a measure

of absolute for-ward and reflect-ed power alongwith the reflec-tion coefficient.The dual log de-tector used in thereturn loss mea-surement alsoprovides a phaseoutput. Becauseof the large gainin the main signalpath of a progres-sive compressionlog amp, a limited(amplitude satu-rated) version ofthe input signal is

a natural by product. These lim-iter outputs are multiplied togeth-er to yield a phase-detected out-put with a range of 180° centeredaround an ideal operating pointof 90°. In a VSWR application, thisinformation constitutes the phaseangle of the reflected signal (withrespect to the incident signal) andmay be of use in optimizing thepower delivered to the antenna.

AMPLIFIER GAINMEASUREMENT USING ASINGLE LOG DETECTOR ANDAN RF SWITCH

Figure 8 shows an alternativeapproach to gain measurement,which is also applicable to VSWRmeasurement. In this application,measuring and controlling thegain of a PA is desired. The PA inthe example is running at 8 GHzand has an output power rangefrom +20 to +50 dBm. This is afixed-gain PA, so the output pow-er is adjusted by changing inputpower. Two directional couplersare used to detect input and out-put power. However, there is onlya single log detector so the twosignals are alternately connectedto the detector using a single-pole, double-throw RF switch.The AD8317 detector has a 0 to–50 dBm input range at this fre-quency. To measure the gain, theinput and output powers are al-ternately measured and digitized.The results are then simply sub-tracted to yield gain. Once thegain is known, the digital controlloop is completed by making anynecessary adjustments to the gainof the PA via a bias adjustment.The level planning for this exam-ple is shown in Figure 9. Attenu-ation is used so that the two inputpower levels at the RF switch areclose together and within the in-put range of the detector.

PRECISE GAIN MEASUREMENTWITHOUT FACTORYCALIBRATION

In addition to reducing compo-nent count, this gain measure-ment method has a number of in-teresting features. Because thesame circuit is being used tomeasure input and output power,it is possible to make precise,

+50

+40

+30

+20

+10

0

-10

-20

-30

-40

-50

-60

60 dBAttenuation

60 dBAttenuation

ForwardPowerRange

ReversePowerRange

Detector A/BInputRange

Powerat Input A Power

at Input B

P

OW

ER (

dBm

)

▲ Fig. 7 Level planning for VSWR measurement using a duallog detector.

μPro

cess

or/D

SP

ADC

ADC

60dB Log Amps(7 Detectors)

60dB Log Amps(7 Detectors)

20 dB 20 dB

40 dB 40 dB

0.1μF

0.1μF

INPA

INPB Log AMP B

Log AMP A

MFLT ForwardPower

ReversePower

MSET

PSET

VPHS

VMAG

PFLT

+

+ -

- +

- Σ Σ

Σ

Pin = -10 to -40 dBm

Pin = -10 to -60 dBm

Pout = +20 to +50 dBm

HPA

▲ Fig. 6 Return loss measurement using a dual log detector.

74

WIRELESS TECHNOLOGIESVOUT1 = SLOPE

• (PIN1 – INTERCEPT)

To figure out the unknown, PIN, theequation can be rewritten as

PIN1 = (VOUT1/SLOPE) – INTERCEPT

Since gain is the difference in themeasured input powers (the differ-ent attenuation levels of the twopaths still have to be factored in), itcan be written as

GAIN = (VOUT1 – VOUT2)/SLOPE

Therefore, the intercept of the detec-tor is not required to calculate thegain. Even though the slope of a de-tector will change from device to de-

vice and over temperature, if Vout1 and Vout2 are closeto each other (it can be done with good level plan-ning and because of the finite input range of the de-tector), a typical value for the slope can be taken di-rectly from the datasheet and used in the above cal-culation.

OUTPUT POWER MONITORINGIn the gain measurement using a single log detec-

tor, the power is measured in order to calculate gain,so the system shown can also be used to monitor theoutput power. However, this cannot be done pre-cisely without factory calibration. To calibrate thecircuit, the antenna must be temporarily replaced bya power meter. The output power and detector volt-ages are then measured at two points within the lin-ear range of the detector. These numbers wouldthen be used to calculate the slope and intercept ofthe detector. For optimum precision, the detector in-cludes a temperature compensation pin. A resistor isconnected between this pin and ground to reducethe temperature drift to approximately ±0.5 dB at thefrequency of operation (8 GHz in the exampleshown). As a result, it is not necessary to do any ad-ditional calibration over temperature.

CONCLUSIONBecause of their linear-in-dB transfer function, log

amplifiers can be easily used to measure gain and re-turn loss. When dual devices are used, very high mea-surement precision is achievable. In some cases, thiscan be achieved without factory calibration. In all cas-es, careful power level planning is necessary so thatthe power detectors are driven at power levels that of-fer good linearity and temperature stability. ■

Eamon Nash holds a BEng degree in electronics from theUniversity of Limerick, Ireland. He has worked at Analog Devices for15 years, first as a field applications engineer, based in Germany,covering mixed signal and DSP products, then as a product lineapplications engineer specializing in RF building block componentsfor wireless applications. He is now applications engineeringmanager for RF Standard Products at Analog Devices.

temperature-stable gain measurements withoutever calibrating the circuit. A look at the nominaltransfer function of a log detector will help in un-derstanding why (see Figure 10).

HPA40 dB

PABIAS

CONTROL

20 dB 20 dB

A

B

40 dB

DAC

μPro

cess

or/D

SP

ADCVOUT

500R100pF 0.1uF

VPOS

+5V

VSETV 1

CLPF

COMM

INHI

INLO1nF

1nF220pF

Select Input/Output

DET

Slope

DET DET DETΣ

Gain Bias

Pin = -20 to +10 dBm

Pout = +20 to +50 dBm@ 8 GHz

0.7pF

▲ Fig. 8 Gain measurement using a single log detector.

+50

+40

+30

+20

+10

0

-10

-20

-30

-40

-50

20 dBDirectional

Coupler

20 dBCoupler

+40 dB

Attenuation

PAInputPowerRange

PAOutputPowerRange

DetectorInputRange

Powerat SwitchInput A

Powerat SwitchInput B

P

OW

ER (

dBm

)

▲ Fig. 9 Level planning for gain measurement using a singlelog detector.

V out

(V

)

Erro

r (d

B)

Pin (dBm)

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

2.0

1.5

1.0

0.5

0

-0.5

-1.0

-1.5

-65 -55 -45 -35 -25 -15 -5 5 15

-40°C +85°C+25°C

Vout = Slope x (Pin-Intercept)Slope (mV/dB) = (Vout2-Vout1)/(Pin2-Pin1)Intercept (dBm) = Pin1- (Vout1/Slope)

Vout2

Vout1

Pin2Intercept

Pin1

▲ Fig. 10 Calibrating a log detector.

75

76

Part Number

RFFrequency

(MHz)

I/Q 3 dB Bandwidth

(MHz)

PhaseError(deg)

AmplitudeError(dB)

CarrierSuppress

(dBm)

SidebandSuppress

(dBc)

Noise Floor (dBm/Hz)

P1dB(dBm)

OutputIP3

(dBm)

SupplyVoltage (V)

SupplyCurrent

(mA)Package

AD8340 700 to 1000 230 — — –30 –32 –148 11 24 4.75 to 5.25 130 4 mm 4 mm,24-lead LFCSP

AD8341 1500 to 2400 230 — — –25 –34 –150.5 9 18 4.75 to 5.25 125 4 mm 4 mm,

24-lead LFCSP

AD8345 140 to 1000 80 0.5 0.2 –42 –42 –155 2.5 25 2.7 to 5.5 65 5.1 mm 6.5 mm,16-lead TSSOP

AD8346 800 to 2500 70 1 0.2 –42 –36 –147 –3 20 2.7 to 5.5 45 6.5 mm 5.1 mm,16-lead TSSOP

AD8349 700 to 2700 160 0.3 0.1 –42 –43 –156 6 19 4.75 to 5.5 135 5.1 mm 6.4 mm,16-lead TSSOP

ADL5370 300 to 1000 >500 0.76 0.03 –50 –41 –160 11 24 4.75 to 5.25 205 4 mm 4 mm,24-lead LFCSP

ADL5371 500 to 1500 >500 0.1 0.03 –50 –55 –158.6 14 27 4.75 to 5.25 175 4 mm 4 mm,24-lead LFCSP

ADL5372 1500 to 2500 >500 0.21 0.09 –45 –45 –158 14 27 4.75 to 5.25 165 4 mm 4 mm,

24-lead LFCSP

ADL5373 2300 to 3000 >500 1 0.13 –39 –39 –157 14 25 4.75 to 5.25 166 4 mm 4 mm,

24-lead LFCSP

ADL5374 2800 to 4000 >500 0.2 0.02 –32 –50 –158 12 22 4.75 to 5.25 175 4 mm 4 mm,

24-lead LFCSP

ADL5375 400 to 6000 >500 –0.05 –0.07 –46 –50 –160 9.4 23 4.75 to 5.25 131 4 mm 4 mm,24-lead LFCSP

ADL5385 50 to 2200 >500 0.39 0.03 –46 –50 –159 11 26 4.75 to 5.25 215 4 mm 4 mm,24-lead LFCSP_VQ

ADL5390 20 to 2400 230 N/A 0.5 N/A N/A –148 11 24 4.75 to 5.25 135 4 mm 4 mm,24-lead LFCSP

Analog I/Q and Vector Modulators

Features

Wide range of modulators covering frequencies of operation from 20 MHz to 4 GHz

Vector modulators provide simultaneous control of both gain and phase within a single IC

Pin compatibility to cover all cellular frequency bands

High dynamic range direct conversion

RF Bonus Feature

/1...../32

/1...../32

/1...../32

REF A

REF B

AD9549

DDS/DAC

REF MONITORSAND SWITCHING

SYSTEM CLOCKMULTIPLIER

DIGITAL PLLR, S DIVIDERS

HOLDOVER

LOW-PASSFILTER

AD9514

Δt LVDS/CMOS

LVPECL

LVPECL

10

–1000 500

SIG

NA

L P

OW

ER

(dB

m)

FREQUENCY (MHz)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

100 200 300 400

CANCELLEDSPUR

CANCELLEDSPUR

Figure 1. The plot shows the synthesizer’s output spectrum for a 399 MHz sine wave, with a 1 GHz sampling rate.

Figure 2. Shown is a complete clock synchronization, generation, jitter clean-up, and distribution circuit with the DDS at the heart of the system.

CARRIER = 399MHzSFDR WITHOUT SPURKILLER = –63.7dBcSFDR WITH SPURKILLER = –69.3dBcFREQUENCY SPAN = 500MHzRESOLUTION BW = 3kHzVIDEO BW = 30kHz

79

Direct Digital Synthesizers (DDS)

Features

AD9913: 250 MSPS DDS consumes only 50 mW power

Low power DDS moves into portable/handheld markets

Low cost DDS with integrated DAC replaces standalone DAC required after FPGA

Programmable modulus mode available for exact rational frequency synthesis

Part Number

MasterClock(MHz)

TuningWord Width

(Bits)

DAC Resolution

(Bits)

SFDR(dBc) to Nyquist

Narrow-BandSFDR (dB)/AOUT (MHz)/

Window (MHz)

Power Dissipation

(mW)Package

SupplyVoltage

(V)I/O Interface

REFCLKMultiplier

On-BoardComparator

Comments

AD9850 125 32 10 54 80/40.1/0.5 480 28-lead SSOP 3.3 to 5.0

Serial or parallel

AD9851 180 32 10 53 85/40.1/0.5 650 28-lead SSOP 3.3 to 5.0

Serial or parallel

AD9852 300 48 12 48 83/10/1 2200 80-leadLQFP/TQFP_EP 3.3 Serial or

parallel Chirp function

AD9854 300 48 12 48 83/10/1 2200 80-leadLQFP/TQFP_EP 3.3 Serial or

parallelQuadrature outputs,

chirp function

AD9858 1000 32 10 58 80/40/1 1900 100-leadTQFP_EP 3.3 Serial or

parallel

Integrated charge pump, phase detector,

analog multiplierAD9859 400 32 10 56 80/160/0.1 200 48-lead TQFP_EP 1.8 SerialAD9951 400 32 14 56 80/160/0.1 200 48-lead TQFP_EP 1.8 SerialAD9952 400 32 14 56 80/160/0.1 200 48-lead TQFP_EP 1.8 Serial

AD9953 400 32 14 56 80/160/0.1 200 48-lead TQFP_EP 1.8 Serial Programmable RAMLUT

AD9954 400 32 14 56 80/160/0.1 200 48-lead TQFP_EP 1.8 SerialProgrammable RAM

LUT, automaticfrequency sweep

AD9956 400 48 14 56 80/160/0.1 400 48-lead LFCSP 1.8 Serial On-board 2.7 GHz PLLAD9958 500 32 10 53 81/200/1 420 56-lead LFCSP 3.3/1.8 Serial 2 complete channelsAD9959 500 32 10 53 81/200/1 680 56-lead LFCSP 3.3/1.8 Serial 4 complete channels

AD9910 1000 32 14 53 86/300/0.5 800 100-leadTQFP_EP 3.3/1.8 Serial or

16-bit parallel

RAM, polar modulation, phase/

frequency/amp ramp

AD9911 500 32 10 53 81/200/1 275 56-leadLFCSP 3.3/1.8 Serial

Multimode modula-tion, targeted spur

reduction

AD9912 1000 48 14 58 86/398.7/0.5 800 64-leadLFCSP 3.3/1.8 Serial Spur reduction

AD9913 250 32 10 58 88/99.7/0.03 50 32-lead LFCSP 1.8 Serial or parallel

RF Bonus Feature

80

Analog Devices, Inc.

Worldwide Headquarters


One Technology Way

P.O. Box 9106

Norwood, MA 02062-9106

U.S.A.

Tel: 781.329.4700

(800.262.5643,

U.S.A. only)

Fax: 781.461.3113


Europe Headquarters


Wilhelm-Wagenfeld-Str. 6

80807 Munich

Germany

Tel: 49.89.76903.0

Fax: 49.89.76903.157


Japan Headquarters

Analog Devices, KK

New Pier Takeshiba

South Tower Building

1-16-1 Kaigan, Minato-ku,

Tokyo, 105-6891

Japan

Tel: 813.5402.8200

Fax: 813.5402.1064


Southeast Asia

Headquarters

Analog Devices

22/F One Corporate Avenue

222 Hu Bin Road

Shanghai, 200021

China

Tel: 86.21.2320.8000

Fax: 86.21.2320.8222

©2008 Analog Devices, Inc. All rights reserved.

Trademarks and registered trademarks are the property

of their respective owners.

Printed in the U.S.A. G07603-.55-8/08 www.analog.com/RF

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