the printed circuit designer's guide to signal integrity
TRANSCRIPT
PEER REVIEWERS
Happy Holden
Consulting Technical Editor, I-Connect007
Happy Holden is the retired director of electronics and innovations for Gentex Corporation.
Happy is the former chief technical officer for the world’s largest PCB fabricator, Hon Hai Precision Industries (Foxconn). Prior to Foxconn, Holden was the senior PCB technologist for Mentor Graphics and advanced technology manager at Nan Ya/Westwood Associates and Merix.
Happy previously worked at Hewlett-Packard for over 28 years as director of PCB R&D and manufacturing engineering manager. He has been involved in advanced PCB technologies for over 47 years.
Eric Bogatin
Eric Bogatin is currently the dean of the Teledyne LeCroy Signal Integrity Academy. Additionally, he is an adjunct professor at the University of Colorado-Boulder in the ECEE department, where he teaches a graduate class in signal integrity and is also the editor of Signal Integrity Journal. Bogatin received his BS in physics from MIT,
and MS and PhD in physics from the University of Arizona in Tucson.
Eric has held senior engineering and management positions at Bell Labs, Raychem, Sun Microsystems, Ansoft and Interconnect Devices. Bogatin has written six technical books in the field, and presented classes and lectures on signal integrity worldwide.
This book has been reviewed for technical accuracy by the following experts from the PCB industry.
MEET THE AUTHOR
Fadi Deek
Signal/Power Integrity SpecialistCorporate Application Engineer
In 2005, Fadi received his B.S. degree in computer and communications from the American University of Science and Technology (AUST) in Beirut, Lebanon.
That same year, he joined Fidus Systems as a design engineer. He designed circuit boards at Fidus for three years.
In 2010, Deek received his M.S. in electrical engineering from the University of Arkansas in Fayetteville. He soon joined Mentor Graphics as a corporate marketing engineer. In 2013, Deek became a corporate application engineer supporting the HyperLynx® tool suite. In parallel, he is also pursuing his Ph.D. at the University of Colorado in Boulder under the supervision of Dr. Eric Bogatin.
The Printed Circuit Designer’s Guide to...™
Signal Integrity by Example
Fadi Deek
Mentor Graphics Corp.,a Siemens Business
© 2017 BR Publishing, Inc.All rights reserved.
BR Publishing, Inc.dba: I-Connect007
PO Box 1908Rohnert Park, CA 94927
U.S.A.
ISBN: 978-0-9982885-2-9
Visit I-007eBooks.com for more books in this series.
CONTENTS
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Chapter 1
Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 2
Reflections and Terminations . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 3
Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chapter 4
Differential Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Summary and Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
The Printed Circuit Designer’s Guide to...™ Signal Integrity by Example
1
INTRODUCTIONIn our current high-speed regime, interconnects are no longer transparent. Interconnects screw up the pristine performance of the signals coming off the chips. If you do not consider these problems and design them out of your product from the beginning, there’s a good chance your product will not work.
This is what signal integrity is really about: how the electromagnetic fields of the signals interact with the boundary conditions of the dielectrics and conductors. Or, in the circuit's view, how the voltages and currents of the signals interact with and are distorted by the transmission lines and discontinuities of the interconnects.
The general process we use to eliminate signal integrity problems is to first be aware of the problems we might encounter, and then follow the best design principles to design them out. Since every product is really customized, with its own set of tradeoffs between performance, cost, risk and schedule, ultimately, we have to optimize each design individually.
This is most effectively done by applying analysis techniques such as rules of thumb, approximations and numerical simulations. We use these tools to explore design space as “virtual prototypes” trying different approaches and evaluating the “bang for the buck” to make engineering tradeoffs.
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But we can’t follow this process blindly and just run simulation after simulation. The most effective engineers are those who have a firm grasp of the essential principles of signal integrity. The farther up the learning curve, the more effectively we can apply the best design principles and explore tradeoffs.
That’s what this first book in the series is all about: exploring the essential principles by example.
The examples are based on an essential principles signal integrity boot camp developed by Mentor, a Siemens business. In this book, we introduce examples of five out of the six different problems that can arise in leading-edge products and some of the design solutions.
More information about the essential principles, their fundamental basis, and how we apply them, can be found in a book by Eric Bogatin, Signal and Power Integrity—Simplified, published in 2010 by Prentice Hall.
It’s important to keep in mind that when using simulations to explore design space, we must always practice safe simulation. This means never performing a measurement or simulation without first anticipating what you expect to see. If it is not as you expect, there is always a reason that is worth exploring.
In each example, we’ll apply the essential principles to illustrate the problem, the root cause, the solutions, and what we expect to see. Then we will use simulations to build virtual prototypes and explore design space to illustrate the problems and solutions.
The four examples in this book include:
1. Designing controlled impedance transmission lines
2. Engineering proper terminations to minimize reflection noise
3. Reducing crosstalk
4. Optimizing differential pair design and termination
We hope the information in this book helps you to better manage signal integrity issues in your next PCB design.
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4
CHAPTER 1
Impedance
Characteristic Impedance vs. Instantaneous ImpedanceA transmission line, or a trace on a printed circuit board with its associated return path, is electrically defined by two properties: its characteristic impedance, or Z0, and its time delay, TD.
As a signal propagates down the signal and return path, it will continuously encounter an instantaneous impedance. This means the signal will apply a voltage and drive a current through each infinitesimal section of the transmission line as shown in Figure 1-1. The impedance the signal sees is the instantaneous impedance. In a uniform transmission line, the instantaneous impedance is the same each step along the transmission line. That single impedance value is the characteristic impedance of the transmission line. This means that a non-uniform transmission line does not have just one impedance that characterizes it.
So, what elements of the transmission line can affect its impedance? To answer the question, a stripline configuration will be used.
For the analysis covered in this section, an advanced high-speed analysis tool was used to model several types of transmission lines, wires, cables
Signal path
Return pathVin
10.0 nH C1
100.0 pF
R2
0.0 ohms
v
i
∆x
Figure 1-1: Signal traversing a transmission line.
5
and connectors. One of the options available is a stripline modeler shown in Figure 1-2.
How does each term affect the Z0 and the TD? The two dielectric height parameters will affect the capacitance per length of the trace by the following rough approximation, C = εw/H where ε is the material permittivity, w is the width of the conductor and H is the height or the separation between each conductor. By decreasing any of the heights H1 or H2, the capacitance will increase.
The connection between the characteristic impedance and the capacitance per length is Z0=√(L/C). Any increase in the capacitance per length will decrease Z0.
Also, the width of the trace, if increased, will decrease Z0 since it will increase the capacitance per length.
Another factor that will affect the capacitance per length is the dielectric constant. From the capacitance approximation, any increase in ε will increase the capacitance per length.
Figure 1-2: Stripline modeler.
6
The length of the conductor will not affect Z0 since, as mentioned before, the instantaneous impedance is constant in a uniform transmission line.
Other parameters will have some effect on the impedance, but it will be minimal. As an experiment, Table 1-1 shows the impact on characteristic impedance from a 10% change in each parameter. The initial nominal values of the parameters produced a 49.6-ohm impedance. To capture the new impedance, only one parameter was changed at a time and then reset to its initial value. Only H1 was varied, since the impact of H2 would be identical.
We would expect that the things that affect capacitance per length the most would have the biggest impact. An item like dissipation factor should have no impact on the characteristic impedance at all.
As can be seen from Table 1-1, the dielectric constant and line width had the biggest impact whereas the loss tangent had no impact at all.
When it comes to the time delay, TD, the characteristic impedance will have no impact. Only the length of the transmission line and the dielectric constant are expected to have an effect. The velocity of the signal can be calculated using v=c/√(ε_r) where c is the speed of light in air. This formula shows that the velocity and the dielectric constant are inversely proportional. Other than that, the rest of the parameters should have no impact on the TD.
To explore this, another experiment was conducted to determine which parameter might have a bigger impact. A 10% increase was applied to
Parameter
T
W
H1
Er
Lt
Initial value for Z0=49.6
1.35
5
7
4.3
0.02
10% increase
1.485
5.5
7.5
4.73
0.022
New Z0
49
47.6
50.7
47.2
49.6
% change in Z0
1.2
4
2.2
4.8
0
Table 1-1: Comparison of parameter effect on Z0 due to 10% increase.
7
each of the parameters. Starting from a 527 ps TD, the results are shown in Table 1-2. Note that the length of the stripline had the biggest impact on the TD. An increase in the dielectric constant slowed down the velocity and thus the transmission line appeared to be longer. Other parameters had no impact at all, exactly as expected.
Another handy rule of thumb is the approximate ratio of the line width to the dielectric thickness that would achieve 50 ohms. Using the stripline modeler, a few values were calculated for a stripline. The width of the trace (W) and the total dielectric thickness (b) that is measured between the two reference planes were chosen so as to keep a constant 50-ohm impedance.
The ratio W/b is plotted in Figure 1-3 versus b in the left plot and versus W in the right plot. As can be seen the ratio varies slowly starting around 0.33. As a rough estimate, the ratio of line width to total dielectric thickness as 1/3 is a starting point when designing the stack up of the stripline layers.
Initial value for TD = 527ps 10% increase New TD % change in TDParameter
L
T
W
H1
Er
Lt
3
1.5
5
7
4.3
0.02
3.3
1.65
5.5
7.7
4.73
0.022
579.8
527
527
527
552.8
527
10
0
0
0
4.9
0
Table 1-2: Comparison of parameter effect on TD due to 10% increase.
8
Figure 1-3: Ratio of width vs. total dielectric thickness W/b for a 50-ohm stripline: upper plot is vs. b, lower plot is vs. W.
9
Driver Output ImpedanceA signal source can be simply modeled as a Thevenin equivalent voltage source as shown in Figure 1-4. Both models have an output impedance Z� that will affect the signal being transmitted onto the transmission line.
A simple way to measure the driver output impedance is simply by using a voltage divider circuit. We first measure the unloaded output voltage. Then we add a resistive load. As the resistance of the load is varied, we observe its value when the output voltage drops 50%. This value of resistance is the output resistance of the driver.
First, it is important to find the unloaded output voltage level of the driver. In order to do that, an open-ended driver was placed on the schematic and assigned to the desired buffer model as shown in U1.AF24 in Figure 1-5.
Every model has three different corners of operation: typical, slow-weak and fast-strong. A simulation was run and the results are shown in Figure 1-6. As can be seen in red, the output of the driver of a fast-strong falling edge starts at 1.4 V and settles at 0V. The rising edge of a typical corner starts at 0 V and settles at a voltage level of 1.2 V.
V
Zs
I Zs
Figure 1-4: Driver model: left, the Thevenin model, right, the Norton model.
Figure 1-5: Output impedance measuring circuit.
Arria10_NoPKG DDR4_DIMM_DQ0 Net002
Arria10_NoPKG DDR4_DIMM_DQ0 Net001
50.0 ohms
U1.AF24 U2.AF24
R1
10
Note that the package model was intentionally removed from the driver model so that a clean waveform can be generated. The package effect will be discussed in a later section.
Now that the output voltage is known, a resistor load is placed at the output of the receiver. The goal is to vary the resistor value to measure an output voltage of 1.2/2 = 0.6 V. As a start a 50-ohm value is assigned to the resistor and the simulation is run. The output voltage level is shown in blue in Figure 1-7 as 781 mV. In order to bring that voltage level closer to 600 mV the load resistor needs to be decreased. A few more values are taken and a resistance of 32 ohms came very close to our target.
An important point to keep in mind is that a driver will not have a single output impedance. Instead, in each of its operating corners the typical slow-weak, fast-strong might exhibit different output impedances. The pull-up, for a rising edge, and pull-down, for a falling edge, transistor circuitry might show differences as well. A similar analysis was done simulating the model at its fast-strong corner using a falling edge. The red plots in Figure 1-7 show that to achieve a voltage level of 1.4/2 = 700 mV a 32-ohm load is needed as well. It happens to be that this model is symmetric.
Figure 1-6: Output voltage of open ended driver: In red, falling edge fast-max corner; in blue, rising edge typical corner.
11
Driver Features and Package EffectsIn the previous section, the driver was used with its package information extracted from the IBIS model. However, in real design simulations, the package parasitic effects, the transistor parasitic capacitances and the on-die capacitance effects should be taken into considerations.
Before digging deeper into these effects, the output waveform shown in Figure 1-6 should be analyzed. Looking at the blue curve for a rising edge simulation, everything looks as expected except for a small dip between 200 ps and 260 ps. A close-up of the dip is shown in Figure 1-8. Where could this dip be coming from when all the driver parasitics have been commented out?
The answer is simply to look inside the IBIS model and examine the “raw” V-t curves. The model data is plotted in Figure 1-9. The plots represent that data measured by the model vendor and show that the dip is inherent to the model itself. Another important piece of information that
Figure 1-7: Driver output voltage when resistor value is swept: In blue typical operating corner, in red fast operating corner.
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Figure 1-8: Driver dip intrinsic to model.
the plot in Figure 1-9 shows is that the driver has an internal initial delay before it starts driving the signal. For the typical corner graph, that initial delay is close to 200 ps. This is another important factor to keep in mind, especially when doing timing analysis.
Figure 1-9: Rising waveform of model as captured by vendor.
13
Another important feature of the receiver in the IBIS model is the C_comp. This is a capacitance value that models the input gate capacitance, the ESD protection diodes and the I/O pad sizes. Thus, a signal reaching the receiver will see such a capacitance. On the other hand, when a signal reaches a driver model it will also see the C_comp capacitance.
In this case, the capacitances are due to the parasitic capacitances of a transistor and the metal to substrate capacitance on the die. Even though those two capacitances are of different values, the IBIS standard uses only one parameter to model both. An important note to keep in mind is that as the model is driving a signal, it does not see the C_comp. However, when a signal reflects from somewhere and comes back to the driver, the signal will see and interact with C_comp.
The impact of the C_comp input capacitance on the receiver will be to add to the RC rise time of the signal the RX sees. To simulate the effect of the C_comp parameter inside a receiver, the following circuit shown in Figure 1-10 is used.
The left circuit drives into a really high-value resistor which acts like an open circuit. The large resistor is used to model the high impedance state of a model when in the receiving state. In the middle circuit the driver is connected to a receiver that has a C_comp value of 1pF. The right circuit is used to reverse-engineer the value of C_comp, by modeling it as a capacitor and turning it off in the model.
A rising edge simulation is run and plotted in Figure 1-11. The blue plot shows the output of the driver when connected to the 10k resistor. Its 10-90 rise time is measured to be 30.5 ps. On the other hand, when the
Figure 1-10: Left circuit is driving into an open circuit; middle circuit is driving into receiver with C_comp, while right circuit is used to reverse-engineer C_comp value.
14
driver is connected to the receiver model U3.48 the driver now has to charge a capacitor when it reaches the receiver. Thus its 10-90 rise time slows down to 93.7 ps as shown in the red plot.
One way of measuring what the value of C_comp is to use the circuit on the right in Figure 1-11. By varying the capacitance value to 1 pf, the green dashed line overlapped the red plot almost exactly.
Now that the effect of C_comp is understood, the package effects will be investigated. Package parasitics are usually modeled inside an IBIS model using RLC values as shown in Figure 1-12. The IBIS standard can model package parasitics using an RLC matrix. Simulators typically convert the RLC elements into a uniform transmission line model with the equivalent characteristic impedance and time delay.
Figure 1-11: C_comp effect when: In blue driver connected to high impedance, in red driver connected to receiver with C_comp,
and in dashed green driver connected to capacitor and high impedance.
Figure 1-12: Excerpt from IBIS model for the package section.
Rise time: 30.515 ps
Rise time: 93.718 ps
15
To investigate the package effects, the right circuit in Figure 1-13 is the driver with no package parasitics driving an open circuit. The middle circuit is the same driver with the package parasitics driving an open circuit. The RLC values of the driver are shown in Figure 1-12
The results of the simulation are plotted in Figure 1-14; blue is the U1.AF24 circuit with no package, and the red is the U2.AF24 circuit with the package. So, where did all that ringing in the red plot come from? Currently, since the package is being modeled as a transmission line, there is an impedance and a TD that comes into play. All that ringing is due to the reflections bouncing back and forth on that package transmission line.
To calculate the Z0 and TD of that transmission line, the following formulas are used: Z0 = √(L/C) = 46.4 Ω and TD = √(L*C) = 130 ps, based on the IBIS package model. A transmission line with the calculated Z0 and TD is now added to the model with no package as shown in the left circuit of Figure 1-13. The results are also plotted in Figure 1-14 in dashed green lines. This shows how simple it is to reverse engineer the values of the package parasitics.
Figure 1-13: Circuit to investigate package effects.
16
Figure 1-14: Simulations of package effects: In blue model without any packages, in red model with RLC package parasitics, and in dashed green transmission line matching circuit.
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CHAPTER 2
Reflections and Terminations
Reflections and Noise MarginsA signal propagating on a uniform transmission line will continue to propagate uninterrupted unless the instantaneous impedance changes. Such an impedance discontinuity will cause part of the signal to reflect back towards the source and part of it to be transmitted beyond the discontinuity. For example, as shown in Figure 2-1, an incident signal propagating on a 50-ohm transmission line reaches an impedance discontinuity. Part of the signal reflects and has a Vreflected voltage level, and part gets transmitted with Vtransmitted voltage level.
To calculate the voltage levels of both the transmitted and reflected signals, the following formulas are used:
• ρ = (Z2 − Z1)/(Z2+Z1) where ρ, rho, is the reflection coefficient, Z2 is the characteristic impedance of the second transmission line and Z1 is the characteristic impedance of the transmission line on which the signal initially propagates.
• τ = (2×Z)2/(Z2+Z1) where τ, tau, is the transmission coefficient.
such that Vreflected = ρ * Vincident and Vtransmitted = τ * Vincident.
Z1 = Z2=Vtransmitted
Vreflected
Vincident
Figure 2-1: Incident, reflected and transmitted signal at an impedance discontinuity.
19
Typical noise margin for single-ended CMOS technology resulting from reflections is 5% of signal swing. The noise margin is calculated at the receiver using the Vinh and Vinl thresholds for each technology as shown in Figure 2-2. During a low-to-high transition, the received signal will cross the Vinh threshold for a first time. Beyond that point, the received signal will ring and might fall below the minimum voltage VOHmin before it settles. The difference between VOHmin and the Vinh threshold is the noise margin available for the TRX system.
Similarly, during a high-to-low transition, the received signal might ring and reach a maximum voltage level of VOLmax. The input low margin is measured between Vinl and VOLmax. The design target is to keep the received voltage above the minimum thresholds during the set up and hold times to read a true bit level.
Termination StrategiesTo reduce reflections from the impedance discontinuities at the ends of the lines, a termination strategy is used. To study some of the common termination topologies, the following five circuits are shown in Figure 2-3. Connecting the drivers and receivers is a 50-ohm, 500 ps trace.
Figure 2-2: Noise margin of the TRX system.
VOHmin
VOLmax
Vinh
VinlNoise margin, low
Noise margin, high
20
Figure 2-3: Termination topologies for single-ended lines.
21
First, to see how serious the situation is, consider a simple circuit made up of a transmitter U3.AF24, a 50-ohm transmission line and a receiver U4.48. The package parasitics of both the transmitter and receiver are included in the investigation. A rising and a falling edge simulation are run and plotted in Figure 2-4. Note that no loss is being included in the simulations of this section.
Both the rising and falling edges show a significant amount of ringing and reflections. The input high signal is measured to be 0.2 V above the threshold and the input low is measured to be 0.1 V below the threshold in this step response.
In order to quiet the line and absorb the continuous reflections back and forth in the line, a source series termination topology is considered first. The circuit is shown in Figure 2-3 as the circuit composed of U5.AF24 and U6.48. The fundamental question here is, what value should be used for the R10 resistor?
Once the transmitted signal reaches the receiver, it will see a really high impedance and reflect back. The reflected signal will propagate down the 50-ohm transmission line and reach the transmitter again. So, for the reflected signal to be terminated, it will need to see a 50-ohm termination at the source. The output impedance of the U5.AF24 driver was shown in
Figure 2-4: Rising and falling edge simulations measured at U4.48.
22
the previous section to be 32 ohms. Thus, the value of resistor R10 could be 50 – 32 = 18 ohms.
More rising and falling edge simulations were run with the 18 ohms placed near U5.AF24. The results are shown in Figure 2-5. As can be seen in the source series termination plots shown in blue, the reflection noise reduced significantly but was not eliminated.
Recall that the package model is a transmission line between the external source series resistor and the TX is a transmission line. This is where the reflection noise is now coming from.
Here is a different termination topology, a circuit composed of U7.AF24 and U8.48 with a far-end parallel termination. The value of the resistor R12 should simply be equal to the impedance of the transmission line. This means the signal reaches the receiver, sees a 50-ohm termination and does not reflect back to the source. However, there are still reflections and the cause will be discussed shortly.
The simulation for both a falling and rising edge is run and plotted in Figure 2-6 where the red plots are the previous result with source series termination, and the blue plots are for the far-end termination. With far-end termination, the ringing on the line was greatly damped down.
Figure 2-5: In red, results at U4.48 with no termination; in blue, results at U6.48 with source series termination.
23
However, the results show that the voltage level is around 800mV. This is expected since resistor R12 forms a voltage divider circuit with the 50-ohm transmission line. This creates an issue since the signal level is so close to the threshold, there is no margin left. However, the falling edge appears to have even bigger margin and a lot less ringing than the source series case.
So far, the far-end termination gave less margin but better suppression of the ringing of the received signal. Is there a way to improve the rising edge margin and maintain a good falling edge margin? The answer is by centering the signal, and to do that an extra power supply should be used to pull up the signal.
As shown in the circuit composed of U9.AF24 and U10.48, the far-end resistor is now connected to a Vtt source instead of ground. During the transient edge, the Vtt source will still appear almost as a short between R6 and ground. However, it will provide a DC offset to pull the signal up. So, the question, in this case, is how much does the signal need to be pulled up? Since the goal is to provide as much margin as possible from both the Vinl and Vinh thresholds, the answer then is that the Vtt value should be mid-way between them.
Figure 2-6: In red, results at U6.48 with source series termination; in blue, results at U8.48 with far-end parallel termination, and in green, results at U10.48 with Vtt termination.
24
A Vtt = 0.6V is used and the result is shown in Figure 2-6 in green. The margin for the rising edge is now at 0.3V and the falling edge one is 0.23V. Although the settling steady state voltage is not at 1.2V, the ringing dies out much faster than with a source series termination. However, one drawback of the Vtt termination is the need for an additional power supply that would drive cost up.
As mentioned earlier, neither type of far-end terminations took care of reflections completely. The reflections are circled in dashed lines on the rising edge signal measured at U10.48. When the signal reaches the receiver, the signal will see a tiny transmission line representing the package and C_comp = 1pf. These cause a reflection to propagate back to the driver, encounter its package and C_comp and reflect back to the receiver. The measured time delay of 1.21 ns between each of those reflections confirms this behavior. The 1.21 ns is made up of the round trip on the 500 ps trace and the package and the charging of the C_comp capacitors.
Single-Bit ResponseFor a specific data rate, sending a single bit down a transmission line and observing the result at the receiver shows, among many things, how long the reflections take to attenuate below a specific value. The reflections caused by a single bit on a transmission line and their effect on subsequent bits are called intersymbol interference or ISI. This type of channel characterization is called single bit response.
A branched topology is considered to test the effect of ISI and how to use the single-bit response as shown in Figure 2-7. In a branched topology, reflections will always occur. The multiple circuits shown in Figure 2-7 include the U1.AF24 and R33 resistor that show what a matched terminated signal looks like at the receiver. The circuit with U2.AF24 as the driver is the branched topology with no terminations. The circuits with U7.AF24 and U12.AF24 as the drivers are the circuits with source series and far-end Vtt terminations respectively. All the circuits have the same total transmission line length from transmitter to receiver.
25
A single-bit simulation with a unit interval of 1 ns is set up and the simulation is run. A comparison between the waveforms at R33 and pin U3.48 is plotted in Figure 2-8. The red plot shows how much reflection occurs on the branched topology when no terminations exist, whereas the blue plot shows no reflections at all.
Figure 2-7: Branched topologies with and without terminations.
Figure 2-8: Single-bit response: In blue at R33 of point to point circuit, and in red at U3.48 in non-terminated branched topology.
26
Next, a single-bit response simulation is examined at the two terminated circuits. The results are plotted in Figure 2-9, with the green plot showing the response at U8.48 and the blue plot at U13.48.
Comparing both termination plots, the results for the far-end termination appear to settle down around the steady state voltage a little bit sooner in time than the source series termination case. However, the reflections in the green plot die out faster. Comparing both to the point-to-point case, the red plot shows that the branched topology will never be as good as a point to point topology.
Figure 2-9: Single-bit response: In red at R33 with far-end termination; in green at U8.48 with source series termination, and in blue at U13.48 with far-end termination.
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CHAPTER 3
Crosstalk
Root CauseCrosstalk is another major issue to investigate during signal integrity analysis of a design. Typically, a third of the design’s noise budget is allocated to noise coming from crosstalk.
In order to solve crosstalk issues, it is very important to understand the root cause. Coupling between two transmission lines occurs due to fringe electric fields and magnetic fields. When a signal propagates on a transmission line, it will generate fields as shown in Figure 3-1. The E-fields, in blue, are lines emanating from the signal and return paths on which the signal is propagating and couples to all surrounding metal. That E-field will induce a voltage on any conductors lying inside the field. Similarly, the signal will also generate H-fields that will induce currents on the surrounding metal.
The coupling mechanism can also be described using mutual inductances and capacitances. A signal return path loop has a loop inductance. Any two loops in close proximity will have a loop mutual inductance between them. A signal carrying a time-varying current, di/dt, will couple from one loop to the other through this mutual inductance. Also, the same signal will have a time-varying voltage, dV/dt, and that will capacitively couple to neighboring traces.
REFERENCE PLANE
D e s i g n F i l e : U n t i t l e d . � s < C : \ P r o j e c t s \ D e s i g n C o n W o r k s h o p \ T E S T I N G \ >H y p e r L y n x L i n e S i m v 9 . 4 . 1
TL1
82.6 ohms443.734 ps3.000 inStackupNet001TL2
82.6 ohms443.734 ps3.000 inStackupNet002
C1
100.0 nF
L1
10.0 nH
De s i g n F i l e : U
n t i t l e d . � s < C : \ P r o j e c t s \ De s i g n C o n W
o r k s h o p \ T E S T I NG
\ >
Hy p e r L y n x L i n e S i m
v 9 . 4 . 1
TL1
82.6
ohms
443.7
34 ps
3.000
inStac
kup
Net001
TL2
82.6
ohms
443.7
34 ps
3.000
inStac
kup
Net002
C1
100.0
nF
L1
10.0
nH
L2
10.0
nH
Capacitive coupling E-field lines
Mutual inductive couplingH-field loops
Figure 3-1: Coupling between traces: E-fields lines in blue, H-fields loops in red.
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Based on this, it is important to keep in mind that as a signal propagates down a trace, the coupling takes place at the location of the transitioning edge, where the dV/dt and the dI/dt are. As a signal propagates, the edge will have a spatial extent along the interconnect. Whether it is a falling or a rising edge, the time varying fields exist where that edge is. The steady state part of the signal does not contribute to coupling since it contains no time varying voltages or currents.
It is very important to mention that once a signal couples onto a trace as noise, the noise will split and propagate in both directions as shown in Figure 3-2.
Near-End and Far-End CrosstalkCrosstalk noise, once generated on a victim line, will propagate toward both ends of the quiet line. When it arrives at the ends, the signature of the waveforms appearing at the two ends will be very different. To distinguish these ends, we refer to the end near the source as the near end. Since the noise appearing at the near end has been propagating backward compared to the direction the signal propagates, we also refer to this end as the backward end.
The noise appearing at the end far from the source is referred to as the far-end noise, and likewise is propagating in the forward direction compared to the direction of propagation of the signal.
In order to explore those signatures, the circuit in Figure 3-3 is used. To the left are a pair of coupled microstrips with 5-mil edge-to-edge spacing in between. The top microstrip, TL1, has a driver model attached to it and will be the aggressor net. The bottom microstrip, TL2, is the victim net.
To the right are a pair of coupled striplines with 5 mil edge-to-edge spacing as well. The top stripline, TL3, is the aggressor net and the bottom TL4 is the victim net. All transmission lines are terminated with 50 ohms to
v,i
v,i
Spatial extent of edge
Figure 3-2: Coupled signal at signal switching edge.
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avoid any effects from reflections for the time being. All the transmission lines are 10 inches long, with the microstrips having a TD of 1.541 ns and the striplines having a TD of 1.757 ns. The driver being used has a 10-90 rise time of 190 ps and 10-90 fall time of 198 ps. This means the coupled lengths are at least eight times the rise time of the aggressor signal and thus allow for a lot of coupling.
Figure 3-3: Top shows coupled microstrips; bottom shows coupled striplines.
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To simplify matters, two terms should be defined. Near-end crosstalk, or NEXT, is the noise that is measured at the pin of the victim net that is close to the driver of the aggressor net, which are pins R3 and R6 in this case. Far-end crosstalk, or FEXT, is the noise measured in the victim net away from the driver and closer to the receiver of the aggressor net, which are pins R2 and R5 in this case.
As a signal edge propagates down a coupled region between two traces, it is continuously inducing a voltage and a current in the victim net. At each time increment, the propagating edge will induce a finite amount of noise and then proceed another time step and induces some more noise. These small noise increments are circled in red in Figure 3-4. At the near end, pins R3 or R6, the small noise increments arrive one after the other and create a wide pulse which is encircled in the dashed ellipse. On the other hand, at the far end, pins R2 or R5, the noise increments closely shadow the propagating edge. With the edge continuously adding more noise at each increment, the noise increments overlap and the resulting noise at the far end will look like a pulse as encircled in a dotted ellipse in Figure 3-4. Keeping in mind these two different signatures of the FEXT and NEXT can help in uncovering crosstalk in a specific waveform.
Both Capacitive & Inductive Coupling Crosstalk on Microstrip Line
Figure 3-4: Coupling of signal edge onto victim. (Application that generated image is available at www.bethesignal.com)
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A rising edge simulation is run and plotted Figure 3-5. For the microstrip case the plot in red is for the NEXT at pin R3. As expected it shows a wide pulse having a peak of 42 mV. The output of U1.AF24 switches up to 800 mV, so the amount of near end noise coupling onto TL2 is 40/800 = 5%.
At the far end, the noise at R2 is plotted in blue. It shows a -360-mV negative peak followed by another ripple in the waveform that is circled in a dashed line. The source of the ripple will be explained shortly.
The question is, since a rising edge was run, why did the far end exhibit a negative peak? Due to Lenz’s law, which describes the direction of circulation of the current, the inductively coupled noise propagating towards the far end will be a negative peak. Also, due to Lenz’s law, the inductively coupled noise propagating towards the near end will be a positive peak. On the other hand, the capacitive coupled noise is positive. The sum of both ends up being a negative peak since the inductively coupled noise is larger. With the aggressor signal switching up to 800 mV the coupled noise is 360/800 = 45%!
The fact that a 360-mV negative pulse and a 40-mV wide pulse exist on the victim net, both will feedback noise onto the aggressor net. By
Figure 3-5: Crosstalk due to rising edge. For microstrip: In red, NEXT at R3, & in blue, FEXT at R2.For striplines: In orange, NEXT at R6; in green, FEXT at R5.
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reciprocity, 40% of the -360 mV FEXT and 5% of the 40 mV, although this value is insignificant, will be injected as noise and propagate all the way to the driver and the receiver.
The resulting noise on the aggressor is shown on the red plot in Figure 3-6. It is measured to be ~1.54 ns which is the time delay of the 10-inch microstrip. Once the ripple reaches the receiver, it will propagate through the package, reflect and then propagate through the package again and onto the microstrip. The ripple now propagating towards the receiver R1, couples 40% FEXT noise onto the victim net. This noise reaches R2 1.6 ns later as measured on the plot.
Looking at the stripline case, the orange plot in Figure 3-5 is for the near-end noise at R6 and has a magnitude of 66 mV. This is 66/800 = 8.2% coupling. Notice that it is higher in magnitude and wider than the NEXT at R3. Since the return planes are far away, the fringe fields extend more to the quiet line than in the case of the coupled microstrips. Also, since a stripline has a longer TD than the microstrip, the medium slows down the propagation velocity, the propagating aggressor signal has more time to couple.
The far-end crosstalk at pin R5 is plotted in green and is almost zero! This is also indirectly answered using Figure 3-7. Since for a stripline all
Figure 3-6: Coupled noise feeding back into aggressor net.
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the fields propagate in the same medium, both the inductively coupled noise and capacitively coupled noise arrive at the receiver with equal magnitude but opposite phase. Thus, they cancel out almost completely.
The plots shown in Figure 3-5 are a result of a rising edge. When the polarity of the edge is reversed, the NEXT and FEXT peaks should be reversed. As far as the magnitude is concerned nothing should change, assuming the rising and falling edge are identical.
One of the main ways to reduce far-end crosstalk is to reduce the coupling length between the two traces. As an experiment, the coupling length
VCC
VCC
GND
H-field loops E-field lines
Figure 3-7: Field plot: Top, coupled microstrips; bottom, coupled striplines.
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was reduced from 10 inches to 5 inches. Another rising edge is simulated and plotted in Figure 3-8. As can be seen now the far-end peak dropped down from -360 mV to -250 mV! The NEXT pulses’ magnitudes remained at 44 mV and 66mV for microstrips and striplines respectively.
The FEXT scales linearly with coupled length, so the magnitude of the peak is reduced as the coupling length is reduced. The magnitude of NEXT does not scale with length and is unchanged when the length is changed, but it lasts for a shorter amount of time. The NEXT signal is on for the round-trip time of the coupled length. The duration of the NEXT decreased when the coupled length decreased.
NEXT reaches its maximum peak (saturates) when the coupling length is greater than half the rise time of the aggressor signal. Notice that the width of the pulse, measured from when its edges cross 20 mV, for the microstrip is now 1.56 ns, down from 3.15 ns in the 10-inch coupling case. The NEXT for stripline case decreased in width as well from the case of 10-inch coupling.
Figure 3-8: Crosstalk due to falling edge. For microstrip: In red, NEXT at R3, & in blue, FEXT at R2.For striplines: In orange, NEXT at R6, and in green, FEXT at R5.
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Impact from Multiple AggressorsIt is valuable to understand how multiple aggressors can affect NEXT and FEXT. The circuit is illustrated in Figure 3-9.
The bottom circuit made up of U9.AF24 and U10.48 is the victim net, with NEXT and FEXT measured at those two pins respectively. The spacing between the transmission lines of each adjacent circuit is 5 mils. The dotted green lines show which transmission lines are adjacent to each other.
The issue to investigate here is to see how far away an aggressor can be and still contribute significant NEXT or FEXT. As a start, only U7 is turned on and is driving a rising edge. Then each of the other drivers are turned on subsequently. The pin U9.AF24 is pegged low, so that any voltage measured at U9.AF24 or U10.48 is only due to crosstalk. The simulations are plotted in Figure 3-10 with FEXT measured at U10.48 and plotted in red, NEXT measured at U9.AF24 and plotted in blue.
R1
Vcc 0.6V
U1.AF24 TL1 U2.48
Vcc 0.6V
R2
U4.48
U8.48
R4
TL2
TL4
U10.48
U5.AF24 TL3
TL5U9.AF24
R5
U7.AF24
U6.48
R3
Vcc 0.6V
Vcc 0.6V
50.0 ohms
50.2 ohms769.687 ps5.000 inStackupNet001
50.0 ohms768.449 ps5.000 inStackupNet003
50.2 ohms769.687 ps5.000 inStackupNet005
50.0 ohms767.831 ps5.000 inStackupNet002
50.0 ohms767.831 ps5.000 inStackupNet004
0
0
Arria10DDR4_DIMM_DQ0Net001
Arria10DDR4_DIMM_DQ0Net003
Vcc 0.6V
50.0 ohms
50.0 ohms
MT40A256M16Z80ADQ0Net005
MT40A256M16Z80ADQ0Net003
MT40A256M16Z80ADQ0Net001
Arria10DDR4_DIMM_DQ0Net002
Arria10DDR4_DIMM_DQ0Net004
MT40A256M16Z80ADQ0Net002
MT40A256M16Z80ADQ0Net004
50.0 ohms
50.0 ohms
U3.AF24
Arria10DDR4_DIMM_DQ0Net005
0
Figure 3-9: Multiple aggressors on victim circuit U9.AF24 - U10.48.
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Figure 3-10: Measured crosstalk with aggressors turned on subsequently: in red, FEXT at U10.48, and in blue, FEXT at U9.AF24.
Looking at NEXT first, the adjacent aggressor couples 33 mV on the victim net. The other four combined add just another 9 mV, which is only 1% of the aggressor’s voltage. This shows that the bulk of the coupling comes from the adjacent net.
Similarly, with FEXT, the adjacent net couples 152 mV of noise, with the second closest adding around 55 mV. The other two distant ones combined add only another 38 mV. This also shows that the highest contributor by far is the adjacent net.
The waveforms of the NEXT and FEXT show multiple dips and peaks that were not visible in the case when only resistor was placed on the far end. A measurement between the FEXT peak and the peak in the NEXT waveform located close to 1.9 ns shows a time difference of 715 ps. This indicates that the FEXT signal reaches the far end, reflects back due to the input gate capacitance of U10.48, and reaches the near end at U9.AF24, approximately one time delay of the microstrip interconnect.
In that experiment, the aggressors were all driving with the same polarity. What would happen if some were driving with the opposite polarity?
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the coupled noise peaks could be negative or positive, depending on the aggressor’s polarity there should be some cancellation. To test this idea, the adjacent driver was set to drive a rising edge, while the other drivers were driving a falling edge. As can be seen, both the NEXT in green and FEXT in orange dropped in value when compared to the case when all aggressors were driving in the same direction. This is indeed due to cancelation as per our earlier expectations.
Figure 3-11: Measured crosstalk when all aggressors driving with same polarity: In blue, NEXT at U9.AF24, and in red, FEXT U10.48.
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CHAPTER 4
Differential Pairs
Differential and Common SignalsA differential pair is made up of two transmission lines. The transmission lines can be closely coupled or loosely coupled, or there may be no coupling at all between them. The differential pair can transport both a differential signal and common signal.
A differential signal is defined as the difference of the voltages of the positive pin and the negative pin of the differential driver, Vdiff = Vp – Vn. The common signal, on the other hand, is the average of the voltages of the positive pin and the negative pin, Vcomm = 0.5 * (Vp + Vn). An example of the resulting signals is shown in Figure 4-1. When there is no common signal, the magnitude of the differential signal will be twice the single-ended signal. Also, the common signal is not always a DC signal. Sometimes it will have a switching behavior as well.
As a differential signal propagates on a pair of transmission lines, it sees a differential impedance which is equal to twice the odd-mode impedance of each trace, Zdiff = 2 * Zodd, where Zodd is the impedance of each transmission line when the pair is driven in the odd-mode. Driving a
Figure 4-1: Differential and common signal.
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pair of lines in the odd-mode means driving each transmission line with an opposite polarity to the other.
A common signal, on the other hand, will see a common impedance that is half the even-mode impedance, Zcomm = 0.5 * Zeven, where Zeven, is the impedance of each transmission line when the pair is driven in the even-mode. Driving a pair of transmission lines in the even-mode means driving both of them with the exact same signal having the same polarity and the same magnitude.
Figure 4-2: Differential pairs with same driver model: Top, uncoupled microstrips, and bottom, tightly coupled microstrips.
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In case of a tightly coupled pair, the odd-mode impedance of each transmission line will be smaller in magnitude than the single-ended impedance of each transmission line, Zodd < Z0. On the contrary, the even-mode impedance will have a higher impedance than the single-ended impedance of each transmission line Zeven, > Z0.
In the case where the differential pair are uncoupled, Zodd = Zeven, = Z0. This is because no coupling exists between the pairs and no matter which mode is being driven, the field pattern is the same and their impedance does not get affected.
To investigate a differential pair, the following two circuits are considered as shown in Figure 4-2. The top circuit has two identical drivers driving, with opposite polarity, two uncoupled microstrips terminated by 50 ohm resistors. The impedance of each microstrip is 50 ohms. The bottom circuit has a differential driver connected to two tightly coupled microstrips terminated by 50 ohm resistors. The odd-mode impedance of each of the microstrips Zodd = 50 ohms. However, the single-ended impedance
Shelf due to coupling effectsV (R2-1)V (R4-1)
(V(R2-1), V(R1-1))(V (R4-1), V(R3-1))
Common Signal (R2-1, R1-1)Common Signal (R4-1, R3-1)
dx = 344.76029p sdy = 217.7a5544m V
Figure 4-3: Comparison of signals between coupled vs uncoupled microstrips: Top graph for single lines, middle graph for differential signals, and bottom graph
shows common signal. In blue, signals passing through uncoupled microstrips, and in red signals passing through coupled microstrips.
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Z0 = 57 ohms. The purpose of using two single-ended drivers in the top circuit is to be able to drive a common signal onto the microstrips. The same driver model is assigned to both circuits.
As a start, it is insightful to look at how the signal propagates on each microstrip of the differential pair. For example, a question to answer is this: Will the signals reaching resistors R2 and R4 be any different?
A simulation is run and plotted in Figure 4-3. Looking at the top graph, a rising edge is measured at R2 for the uncoupled circuit and plotted in blue. The red plot is measured at R4 for the tightly coupled case. Both plots settle at the same voltage of 800 mV.
The rising edge at R4, the tightly coupled case, shows a slightly different behavior. There is a shelf around 500 mV on the red plot. This is due to coupling between the two traces. Since these are microstrips, far-end crosstalk acts like a high Q filter at certain resonant frequencies and absorbs some of the energy of the signal.
The middle graph of Figure 4-3 shows the differential signal measured at the two resistors of each circuit. Although both circuits are driving the same length of microstrips, the differential signal at resistors R4 and R3, plotted in red, arrives ~37 ps earlier than that at resistors R2 and R1, plotted in blue. This is also due to coupling. In a tightly coupled pair, most of the field lines are in the air medium rather than in the dielectric. Thus, their velocity is higher than for single-ended lines where the fields are mostly in the substrate. A visual comparison in Figure 4-4 shows that for the top graph, the blue E-field lines are radiating from each microstrip and coupling to the other in air. However, the bottom graph shows a single-ended line with most of the E-fields inside the substrate.
Finally, the bottom graph of Figure 4-3 shows the common signal. In a presumable symmetric model driving a pure differential signal on a symmetric channel, where can the asymmetry arise from? It turns out as shown in Figure 4-5 the rising waveform has a dip that does not exist in the falling waveform. In addition to the dip the two waveforms are skewed in time and intersect at around 150 mV instead of midway at 400 mV. As can be seen the common signal starts at the average between the positive and negative signals which is 400 mV. Right where the signals
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VCC
VCC
Figure 4-4: Field Lines: top, differential pair driven in odd mode, & bottom, a single-ended line.
Figure 4-5: Asymmetry in rising and falling waveforms.
Asymmetry due to dip
transition, the common signal shows a dip with a magnitude of 217 mV for the case of the coupled microstrips, as shown in red. The uncoupled microstrip case also exhibits a dip of similar magnitude which proves that the dip is not due to coupling but inherent to the model itself.
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Terminating Differential and Common SignalsIn the circuits shown in Figure 4-6, the top circuit uses a resistive T-network to terminate both the differential and common signals. Using the field solver, the different impedances of the microstrips used in each is calculated as follows: Z0 = 57.7 ohms, Zodd = 49.6 ohms and Zeven = 65.9 ohms.
A
B
C
Circuit 1
A
B
C
Circuit 2
Figure 4-6: Terminated differential pair: Top uses resistor T-network with pullup, bottom uses RC termination.
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First, consider Circuit 1, with resistive termination. To deduce the values for R1, R2 and R4, the propagating signal needs to be analyzed. When a differential signal reaches nodes A and B, the single-ended signals at each node will have the same magnitude but be 180° out of phase. Those two single-ended signals will pass through resistors R1 and R2 and then cancel each other at node C. So, node C will act as a “virtual” ground and thus the differential signal sees R1 and R2 in series. Since the Zdiff = 2* Zodd this yields R1 = R2 = Zodd = 49.6 or just 50 ohms.
The common signal reaches nodes A and B with the single-ended signals being exactly alike. So R1 and R2 will appear in parallel with each other as far as the common signal is concerned. This means so far, the common signal sees a 25-ohm resistance. However, Zcomm = 0.5 * Zeven = 33 ohms, which means we still need another resistor to bring the 25 ohms of resistance up to 33 ohms. That means R4 should be 8 ohms and the formula to calculate it is R4 = 0.5*(Zeven – Zodd). Note that the power supplies are designed to look like a very low impedance to ground for an AC signal. This is why Vt6 = 0.6V pull-up power supply acts like a short circuit to ground.
Circuit 2 in Figure 4-6 behaves similarly for the differential signal. However, for the common signal, the R4 resistor was replaced by a capacitor. The reason behind removing R4 is that for tightly coupled transmission lines, the value of the resistor R4 tends to be very small and can be ignored. For loosely coupled transmission lines Zeven = Zodd and thus R4 = 0.
The capacitor C1 provides a DC block to current that would otherwise cost a lot of power loss. Typical values of the capacitor range from 1 - 100 nF. The value should be selected such that the RC time constant is much longer than the period of the lowest-frequency bit pattern.
Two simulations are run to test how well the differential and common signals are terminated. In the first simulation, the drivers in each circuit drive with opposite polarity to generate a pure differential signal. In the second simulation both drivers of each circuit were set to drive with the same polarity to generate a pure common signal. The results are plotted in Figure 4-7. The top graph compares the differential signals between Circuit 1 in red and Circuit 2 in blue. Both waveforms show that
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they are well terminated. The common signal, in the bottom graph, also shows good termination for both circuits. However, notice for Circuit 2 (in red) that a reflection of around 52 mV appears in the waveform. The reflection arrives at the receiver 1.5 ns after the rising edge arrives. It is the negative of the signal at the RX because it reflected off the low output common impedance of the driver. The microstrips are 761 ps and the round trip amounts to 1.5 ns. This small, reflected, common signal component is irrelevant.
Channel-to-Channel Crosstalk in Tightly vs. Loosely CoupledWhen deciding between tightly or loosely coupled differential pairs, many believe that tightly coupled pairs will result in less channel to channel crosstalk. This may be the case when there is no return plane, but at the board level, the coupling to the adjacent plane is always larger than the coupling between traces in a pair. This means that coupling to the plane will dominate the crosstalk behavior of a differential pair. Whether the traces are tightly or loosely coupled is not an important criterion affecting channel-to-channel crosstalk. In fact, the planes will cause completely counterintuitive behavior, as we illustrate in this example.
The three circuits shown in Figure 4-8 are driving 100-ohm differential stripline pairs. Each circuit is composed of an aggressor differential pair
Reflections
DifferentialSignal (R2-R1)DifferentialSignal (R6-R5)
CommonSignal (R2-R1)CommonSignal (R6-R5)
dx = 1.59224n sdy = 13.63771m V
Figure 4-7: Top graph, differential signal; bottom graph, common signal. In blue, waveforms for Circuit 1, and in red, waveforms for Circuit 2.
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channel that has a driver connected to it and a victim channel that is terminated at both ends. All the signal lines in the schematic are fixed at a width of 5 mils. The edge-to-edge, channel-to-channel separation is also fixed at 5 mils between the two adjacent signal lines of adjacent pairs.
Figure 4-8: Channel-to-channel crosstalk comparison between tightly coupled, loosely coupled and uncoupled differential channels.
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The coupling between the p and n lines in each pair is different in each of the three circuits. For the tightly coupled circuit, the spacing between the lines in the pair is 5 mils. For the loose coupling, the separation between the lines of each pair is 10 mils. The uncoupled circuit has 15 mils spacing between the lines of each pair. To maintain the same 100 ohms of differential impedance of each channel, the distance between the signal lines and the reference planes was decreased as the separation increased.
A rising edge simulation is run and the differential channel to channel NEXT is shown in Figure 4-9. The “tight coupling” circuit plots are in blue, while the “loose coupling” plots are in green and the “uncoupled” circuit in red.
FEXT: V(R10-1)FEXT: V(R4-1)FEXT: V(R7-1)
NEXT: V(R11-1)NEXT: V(R5-1)NEXT: V(R8-1)
Figure 4-9: The top graph shows FEXT, and the bottom graph shows NEXT. In blue are plots for “tight coupling,” while green plots
depict “loose coupling,” and red plots show “uncoupled.”
A rising edge was run, but the NEXT showed a negative peak. This is because the stripline adjacent to the victim channel is an inverted driver and falling edge was generated by it. The signature of the NEXT is a wide pulse and it agrees with the three plots. An interesting observation to make is why the differential channel to channel NEXT is the largest on a tightly coupled differential pair compared to the differential channel to
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channel NEXT on loosely coupled or uncoupled at all. This is the exact opposite of what most engineers would expect. Shouldn’t there be less crosstalk in tightly coupled differential pairs?
The answer is apparent when the geometry is examined. In order to maintain a 100-ohm differential impedance with a 5-mil wide stripline the thickness of the dielectric was decreased as the separation between the p and n lines in each differential pair was increased. This means for the circuit that has the uncoupled differential pair, the return planes were closest to the signal lines of the three cases. One of the ways to reduce crosstalk is to bring the planes closer to the signal lines so that more fields couple to the planes rather than the adjacent striplines. And this is simply why NEXT is the least for the uncoupled case and the largest for the tightly coupled case.
Figure 4-10: Stackup for circuits: left shows tightly coupled, while middle shows loosely coupled, and the right depicts uncoupled.
13 mils5 mils
6.6 mils 10 mils 6.1 mils 15 mils
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In Chapter 1, the basic concepts of characteristic impedance and instantaneous impedance were introduced. A stripline modeler was used to show how the different parameters of the geometry can affect the impedance. Also in the first chapter, a couple of features of an IBIS model were introduced. The C_comp capacitance was shown to slow down a switching edge, and the package parasitics were shown to behave as a short transmission line.
In Chapter 2, a source series, far-end and far-end Vtt terminations were shown to improve noise margins measured from the Vinl and Vinh thresholds. The far-end Vtt was shown to have the best margins and centered waveforms. In a branched topology, the terminations were proven to have no great impact. A single-bit response showed that a point to point topology will have the lowest inter symbol interference, ISI, when compared to branched topologies.
Chapter 3 showed that the electrical signature of near-end crosstalk is a wide pulse, whereas the electrical signature of far-end crosstalk is a narrow pulse. Also, shown in this exercise is that the closest aggressors to a victim net are the biggest noise contributors.
Differential pairs were introduced in Chapter 4. The differential signal on a tightly coupled microstrip was shown to propagate a bit faster than a differential signal on an uncoupled pair of microstrips. Also, a resistive T-network and an RC network were used to terminate both the common and differential signal. Lastly, it was shown that an uncoupled pair of striplines will exhibit less noise than tightly coupled striplines.
Summary and Conclusion
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Glossary
C_comp: Defines die capacitance as per the IBIS standard.
Characteristic impedance: Impedance of a uniform transmission line.
Common signal: Calculated as the average of the signals on a differential pair.
Coupling: Exchange of electromagnetic energy between two or more transmission lines.
Crosstalk: The signal that is induced on a victim net due to coupling to an aggressor net.
Differential pairs: A pair of transmission lines driven with signals that are out of phase.
Even-mode: The mode by which a differential pair is driven by signals that are in phase.
Far-end crosstalk: The crosstalk measured near the end opposite the driven end of the active signal line(s). Sometimes called "forward crosstalk".
Impedance: The total passive opposition offered to the flow of electric current. This term is generally used to describe high-frequency circuit boards.
Instantaneous impedance: The impedance seen by a signal at each time increment.
Microstrip: A transmission line on a PCB where the signal trace is routed on the top or bottom layers of a printed circuit board. The transmission line is composed of a signal trace and a reference plane.
Near-end crosstalk: The crosstalk measured on the victim line near the driven end of the active signal line(s).
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Odd-mode: The mode by which a differential pair is driven by signals that are out of phase.
Output impedance: The impedance a driver exhibits as it is driving a signal onto a transmission line.
ps: Picosecond, an SI unit of time equal to 10−12 or 1/1,000,000,000,000 of a second. That is one trillionth, or one millionth of one millionth of a second, or 0.000 000 000 001 seconds.
Reflection coefficient: A value between 0 and 1 measuring the portion of a signal that is reflected back towards the source.
Rise time: The time required by a driver to rise or fall from 20% of its settled voltage level to 80% of its settled voltage level. It is also common to measure the rise time from 10% to 90% of its settled voltage level.
Signal integrity: The quality of an electrical signal after it has been sent down a conductor. It encompasses many parameters such as distortion, delay, attenuation, ringing, crosstalk, dispersion, impedance, etc.
Single-bit response: The response of a channel due to the transmission of a single bit.
Stripline: A transmission line on a PCB where the signal trace is buried within the PCB and is spaced above and below a reference plane by the dielectric material.
Termination: Addition of passive components onto the transmission line to ensure impedance matching between transmitter, receiver, and transmission line.
Time delay (TD): The time required for a signal to propagate through a transmission line.
Transmission coefficient: A value between 0 and 1 measuring the portion of a signal that is transmitted from one transmission line to the next.
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Book:Signal and Power Integrity—Simplified (2nd Edition) by Eric Bogatin
Mentor Resources:
Websites:
• HyperLynx Alliance
• HyperLynx Virtual Labs
• HyperLynx Technology Website
White Paper:
• An Introduction to HyperLynx SI/PI Technology
REFERENCES
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ABOUT MENTOR GRAPHICS
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