Agere Systems, Inc.

The Network Processor

Revolution

Fast Pattern Matching and

Routing at OC-48

David Kramer

Senior Design/Architect

Agere Systems, Inc.

Market Segments

DWDM RingOC–192 to OC–768

Optical Mux

Optical Mux

MetroArea

Network

Optical Core

DWDM RingOC–192 to OC–768

Metro EdgeOC–48 to OC–192

Metro EdgeOC–48 to OC–192

OC–12 to OC–192

MSSW

Carrier CoreOC–48 to OC–192, 10 GbE

Metro CoreOC–48 to OC–192, 10 GbE

OC–12 to OC–192

MSSW

CarrierNetwork

Carrier EdgeOC–48 to OC–192, 10 GbE

Access RingOC–3 to OC-48

AccessNetwork

Agere Systems, Inc.

Agere’s Approach

¾ Family of Chips for Network Devices

¾ New “Data-Flow” Approach

¾ High-level Software Programming

What are the old approaches?

Agere Systems, Inc.

Old Approach

¾ Worked well for awhile

¾ Higher speeds, more functionality needed

¾ Started falling behind dramatically

Lookup Table Data StorageProgram

Data in Data out

P(inside a router)

Old RISC-based Approach

Time

Speed

Processor Speed

(Moore’s Law)

2X per 18 m

onths

Netw

ork

Bandw

idth

Agere Systems, Inc.

Old Approach #2

¾ Develop custom ASIC to perform wirespeed routing/queuing

– High development costs

– Long time to market

– No flexibility (e.g. IPv6 = forklift upgrades, Diffserv = forkliftupgrade)

Lookup Table Data Storage

Data in Data out

Custom ASIC

ASIC based approach

Agere Systems, Inc.

Wire-speed Path• Forwarding

• Shaping

• Queuing

• SAR

• Monitoring, etc.

Slow-speed Path• Routing protocols

• Error processing

• Statistics reporting

• Configuration, etc.

Agere’s Approach

¾ Highly pipelined chip-set for fast “Data Path”

P

Data Path

Control Path

Data in Data out

Agere Systems, Inc.

Agere’s Approach

¾ Agere chip-set forms the wire-speed path

P

PH

Y

ASI

Data in Data out

FPP RSPB

PI

Agere Systems, Inc.

System Overview

¾ Fast Pattern Processor (FPP)

P

PH

Y

ASI

Data in Data out

FPP RSP

BP

I

Agere Systems, Inc.

PHY Assem.Recog.

Classify

FPP

Assem.Recog.

Classify

System Overview - FPP

¾ Recognition/Classification/Filtering

¾ Functional Processing

¾ Assembly (if necessary)

QueuingTraffic

Shaping

Packet

ModSeg. PHY

Agere Systems, Inc.

System Overview - FPP

¾ Programmable classification up to

Layer 7

¾ Functional Programming

Language

¾ Highly pipelined multi-threaded

processing of PDUs

¾ ATM re-assembly at

OC-48c rates

¾ Table lookup with millions of

entries & variable entry lengths

¾ Configurable UTOPIA/POS

interfaces

¾ Time to market, ease of upgrade

¾ Reduces development time, code

maintenance

¾ High performance scalable

architecture

¾ Eliminates external SAR

¾ Eliminates need for external CAMs;

deterministic performance

regardless of table size

¾ Simplifies design and reduces

development cost

BenefitsBenefitsFeaturesFeatures

Agere Systems, Inc.

Functional

Bus

Interface

Queue

EngineSSRAM

Pattern

Processing

Engine

Block Buffers

and

Context Memory

Input

Framer

SDRAM

Control

SDRAM

SSRAM

Output

Interface

32-bit Utopia/POS

from PHY

8-bit POS

from ASI

32-bit POS

to RSP

Functional Bus

to ASI

Configuration

Bus

Interface

8-bit

Configuration

Bus

from ASI

System Overview - FPP

Agere Systems, Inc.

System Overview

¾ Routing Switch Processor (RSP)

P

PH

Y

ASI

Data in Data out

FPP RSP

BP

I

Agere Systems, Inc.

PHY Assem.Recog.

ClassifyQueuing

Traffic

Shaping

Packet

ModSeg.

RSP

QueuingTraffic

Shaping

Packet

ModSeg. PHY

System Overview - RSP

¾ Transmit queuing

¾ Traffic Management and Shaping

– Quality of Service (QoS), Class of Service (CoS)

¾ Packet Modification

– Including Segmentation

Agere Systems, Inc.

BenefitsBenefitsFeaturesFeatures

System Overview - RSP

¾ 64K queues

– programmable shaping (such as

VBR, UBR, CBR)

– programmable discard policies

– programmable QoS/CoS

– 16 levels of priority

¾ Programmable packet

modifications

¾ Support for Multicast

¾ Highly pipelined processing of

PDUs

¾ OC-48c bandwidth

¾ Generates required

checksums/CRC

¾ Large number of connections

– OEM Differentiation

– Enables new policy based

management system

¾ Support for emerging apps

¾ Consistent software model across

all programmable features

¾ High performance architecture

¾ Smart processing at very high

bandwidths

Agere Systems, Inc.

32-bit POS

from FPP

8-bit

Configuration

Bus

from ASI

SSRAM SSRAM SSRAM

Config.

Bus

Interface Transmit Queue

Traffic

Shaping

Engine

Queue

Manager

Input

Interface

Traffic

Mgmnt.

Engine

32-bit Utopia/POS

to backplane

8-bit POS

to ASI

ContextBuffer

Management

Transmit

Request

Flow

Control

AssemblyStream

Editor

SDRAM

Output

Interface

SSRAM

System Overview - RSP

Agere Systems, Inc.

Chip Details (Payload Plus Chipset)

• TSMC 0.18um technology

• 26.4 million transistors

• 1.33 million RAM bits

• Measured Power Consumption: 6.2W

Agere Systems, Inc.

Software Landscape

PP

HY

ASI

Data in Data out

FPP RSPB

PI

FPL Code(Functional Programming

Language; defines classification)

ASL Scripts(Agere Scripting Language;

defines policing, traffic

management, shaping and

modification)

Control Code(interfaces to chipset via

Agere RTE and APIs)

Agere Systems, Inc.

Functional Programming Language (FPL)

¾ FPL is a high-level language expressly designed for high-

speed protocol processing

– Fast pattern matching of the data stream

– Easy-to-understand statement semantics

– Dynamic updating of FPL programs in the FPP

– A complete software development tool set

Agere Systems, Inc.

FPL IP Processing Example

IP: IPv4_header fskip(36) dest=route fTransmit(dest);IP: IPv4_header fskip(36) dest=route fTransmit(dest);

route: 10.20.15.12 freturn(FILTER)

route: 10.20.15.* freturn(LOCAL)

route: 10.20.*.* freturn(GATEWAY)

route: 10.20.15.12 freturn(FILTER)

route: 10.20.15.* freturn(LOCAL)

route: 10.20.*.* freturn(GATEWAY)

VERVER HLHL Service TypeService Type

IP Options PaddingPadding

Destination AddressDestination Address

Source AddressSource Address

Header ChecksumHeader ChecksumProtocolTime to Live

Fragment OffsetFragment OffsetFlagsIdentification

Total LengthTotal Length

0 3116

Agere Systems, Inc.

Performance: IPv4 4-tuple (ATM)

Payload Plus Chipset operating at 133Mhz

IP over ATM over SONET

Bandwidth vs. Payload Length

0

20

40

60

80

100

120

0 500 1000 1500 2000 2500

Payload Length

Ban

dw

idth

(%

of

2.5G

)

1 1st Pass Counter & 1 2nd Pass Counter

1 1st Pass Counter & 9 2nd Pass Counters

Agere Systems, Inc.

Performance: IPv4 4-tuple (POS)

Payload Plus Chipset operating at 150Mhz

IP over PPP over SONET

Packet over Sonet

0%

20%

40%

60%

80%

100%

120%

0 500 1000 1500 2000Packet Length

Ban

dw

idth

(%

of

2.5

G)

ip_pos 4 counter

Agere Systems, Inc.

Performance: IPv6 forwarding (ATM)

Payload Plus Chipset operating at 133Mhz

IMIX = 55% 64byte, 5% 72byte, 17% 596byte, 23% 1520byte

IPV6 ATM IMIX

0

20

40

60

80

100

120

0 5 10 15 20 25 30

Number of Counters

Ban

dw

idth

(%

of

2.5

G)

Agere Systems, Inc.

Performance: IPv6 forwarding (POS)

IPV6 POS IMIX

0%

20%

40%

60%

80%

100%

120%

0 5 10 15 20 25 30 35

Number of Counters

Ban

dw

idth

(%

of

2.5

G)

Payload Plus Chipset operating at 133Mhz

IMIX = 55% 64byte, 5% 72byte, 17% 596byte, 23% 1520byte

Agere Systems, Inc.

PayloadPlus™ Summary

¾ Value Add Elements

– Classification

– Statistics Gathering

– Buffer Management

– Traffic Shaping

– Data Modifications

¾ Hardware Overhead

– Linked List Maintenance

– Queue Maintenance

– Parallel Processing

– Pipeline Processing

OC-48c Classification, Scheduling, Statistics

133Mhz, 6.2W

Agere Systems, Inc.

¾ Backup Slides

Agere Systems, Inc.

FPP

PHY,

Framer RSP

Non “Wire

Speed” µPControl Plane:

Protocol Stacks,

Applications

Wire-speed DatapathBackplane

Fabric

APPs

IP, POS, ATM and Frame Relay at OC-48c Rates

Building Blocks for Wire-Speed Datapath

¾ FPP-Fast Pattern Processor

– Classification engine

¾ VPP - Voice Packet Processor

– AAL2 Co-processor

¾ RSP-Routing Switch Processor

– Queuing, QoS, CoS,Modification

¾ ASI-Agere System Interface

– Policing, Statistics, PCI bridge

ASI

VPP

Agere Systems, Inc.

FPL is to Communication Apps what

SQL is to Relational Databases

FocusFocus Communications Communications GenericGeneric

Hides parallelismHides parallelism üü

Real-time capableReal-time capable üü üü

Good for routing/switchingGood for routing/switching üü

Good for spreadsheetsGood for spreadsheets üü

Wide variety of prog. styles Wide variety of prog. styles üü

FPLFPL CC

Agere Systems, Inc.

System Overview - Applications

¾ Building-blocks approach allows flexibility

– Many different applications possible

– Mix-and-match chips for desired functionality

RSP

RSP

RSP

RSPFPP

FPP

OC-48c ATM Line Cards

RSP

RSP

RSP

RSPFPP

FPP

GbE/POS Line Cards

FPPLine

cardsRSP

Router Card

FPPLine

cardsRSP

Legacy I-Face

FPP

RSP

UTOPIA POS

FPP

RSP

OC-48 SAR

RSP

RSP

RSP

RSPFPP

FPP

GbE/POS Line Cards

RSP

RSP

RSP

RSPFPP

FPP

OC-48c ATM Line Cards

FPPLine

cardsRSP

Router Card

FPPLine

cardsRSP

Legacy I-Face

FPP

RSP

UTOPIA POS

FPP

RSP

OC-48 SAR