the memory controller
DESCRIPTION
The Memory Controller. Overview Control/Address Lines usage Memory Module Configuration Register settings Chip Select Base Address Register settings Device considerations. Memory Controller Overview. BBUS. 32 Bit Address Bus 32 Bit Data Bus. Memory Controller. Bus Controller. NET+ARM. - PowerPoint PPT PresentationTRANSCRIPT
The Memory Controller
OverviewControl/Address Lines usageMemory Module Configuration Register settingsChip Select Base Address Register settingsDevice considerations
Memory Controller Overview
CONTROL LINES
•Chip Select•Write Enable•Output Enable•Byte Enables•RAS•CAS
11 Direct Pins
BBUS
Memory Controller Bus Controller
32 Bit Address Bus32 Bit Data Bus
ADDRESS BUS DATA BUS
•A28 : A0•256 Mbytes / Chip Select•SRAM and DRAM Supported•A13 : A0 Multiplexed
•D32 : D0
•D31 : D24 8 Bit Device•D31 : D16 16 Bit Device•D31 : D0 32 Bit Device
External Bus Master
•Bus Request•Bus Grant•Busy
NET+ARM
Memory Controller Hardware Dependencies
RESET
RESET* Low for 512 Clocks Followed By 1 usec pulse
Address Line Bootstrapping
Internal pull up constant current sources onAddress Bus
The firmware MUST match the bootstrap setting
ADDR[24:23] CS0 Bootstrap Setting00 Bootstrap Disabled01 32-Bit SRAM port; 15 wait states10 32-Bit DRAM port; 15 wait states11 16-Bit SRAM port; 15 wait states
A24
A23
Memory Controller Memory Map
Address RegisterFFC0 0000FFC0 0010
FFC0 0018FFC0 0014
FFC0 0020FFC0 0024FFC0 0028FFC0 0030FFC0 0034FFC0 0038FFC0 0040FFC0 0044FFC0 0048FFC0 0050FFC0 0054FFC0 0058
MMCRChip Select 0 BARChip Select 0 ORChip Select 0 ORBChip Select 1 BARChip Select 1 ORChip Select 1 ORBChip Select 2 BARChip Select 2 ORChip Select 2 ORBChip Select 3 BARChip Select 3 ORChip Select 3 ORBChip Select 4 BARChip Select 4 ORChip Select 4 ORB
Address Range Module
0xFFC0 0000 0xFFCF FFFF MEM Module
Memory Module Configuration31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFCNT REFEN RCYC AMUX A27 A26 A25* AMUX2
Memory Module Configuration Register (MMCR) FFC0 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16BASE
Chip Select Base Address Register (CSBAR) [ FFC0 0010 FFC0 0040 ]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0BASE PGSIZE DMODE DMUXS EXTTA DMUXM IDLE DRSEL BURST WP V
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16MASK
Chip Select Option Register (CSOR) [ FFC0 0014 FFC0 0054 ]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0MASK WAIT BCYC BSIZE PS WP V
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0- - - - - - - - - - - - - - - -
MMCR RFCNT, REFEN, RCYC
RFCNT
D31 D24
Refresh Period = [ ( RFCNT + 1 ) * 4 ] / Fxtal
NOTE: The NET+ARM DRAM Controller Always Generates CAS before RAS Refresh Cycles
Example:For a refresh period of 15.191usec, RFCNT must be 13 .. Assuming Fxtal = 3.6864MHz
REFEN
D23
REFEN Must be Set for DRAM Devices
RCYC
D22:21
Refresh Cycle Count00 8 BCLK Clocks01 6 BCLK Clocks10 5 BCLK Clocks11 4 BCLK Clocks
MMCR AMUX
PortC0PortC1PortC2PortC3 / AMUXPortC4 / RIB*
SEL
DRAMNET+ARM
Address Pins
PORTC3
ExternallyMultiplexedAddresses
CAS Address DrivenRAS Address Driven
ExternalMultiplexer
AMUX
D20
LogicalAddresses
Lower Address
Bits
Upper Address
Bits
0 Disable external PortC3 multiplexing1 Enable external PortC3 multiplexing
MMCR AMUX2
SEL
DRAM
PORTC3
ExternalBUS MasterPortC0
PortC1PortC2PortC3 / AMUXPortC4 / RIB*
NET+ARM DRAM Addresses
NOTES:1. External bus master must have
the ability to multiplex RAS & CASaddresses
2. Inactive bus master must tri-state address bus
3. Drives PortC3 Multiplexing Regardless of AMUX & DMUXS
AMUX2
D16
0 Normal Operation1 Drive PortC3 DRAM Multiplexing
Internally Multiplexed Signals
CAS Address DrivenRAS Address Driven
Lower Address
Bits
Upper Address
Bits
MMCR A27, A26
GNDVCCADDR27/CS0OE*ADDR26/CS0WE*
FLASH
OE*WE*CS0*CS1*/RAS1*CS2*/RAS2*CS3*/RAS3*CS4*/RAS4*
WE* OE* CE*
Ground
FLASH
OE* WE* CE*
Enable A27 Output 0 CSO0E* Driven1 ADDR 27 Driven
Enable A26 Output 0 CSOWE* Driven1 ADDR 26 Driven
A27
D19
A26
D18
NET+ARM NET+ARMConventional MethodSpecial Case Method
Note: When used as special function, peripheral cannot ‘need’ A26 & A27
MMCR A25*
GNDVCCADDR27/CS0OE*ADDR26/CS0WE*ADDR25/BLAST*
ExternalBUS Master
MemoryPeripheral
(X32)
A23
A25* as Input is Burst Terminate Signal
BLAST*
Burst Continuance Last Cycle of Burst
Enable A25 Output 0 Used for Address Line 251 Used for BLAST* Signaling
A25*
D17
01
Note: When used as special function, peripheral cannot ‘need’ A25
CSAR BASE, PGSIZE, DMODESample NET+ARM
Memory Space
0000 0000
0200 0000
0400 0000
0800 0000
SDRAM
FLASH
FPGA
Peripheral Page Size
00 64 Bytes01 32 Bytes10 16 Bytes11 8 Bytes
PGSIZE
D11 D10
D9 D8
DMODE
00 FP DRAM01 EDO DRAM10 Sync DRAM11 RESERVED
BASE
D31 D12
NOTE: ALL DRAM BANKS MUST HAVE THE SAME DMODE SETTING
Physical Base Address of Peripheral
0x00200 equates to 0x00200000
BASE must be consistent with the size of theMASK field in the Option Register•A 4M device MUST reside on a 4M Base Boundary
Page
CSAR DMUXS, EXTTA, DMUXM
DRAM Address Multiplexer Select
DMUXS
D7 0 Internal Address Multiplexer1 External Address Multiplexer
IGNORED if AMUX or AMUX2 is set
External TA* Configuration
EXTTA
D6 0 Internal1 External
IGNORED if PS is set for 32 Bit Peripheral
DRAM Internal Multiplex Mode
DMUXM
D5 0 10 CAS1 8 CAS
MODE 1 Required for SDRAM
CSAR IDLE, DRSEL, BURST, WP, V
Force 1 BCLK at the End of the Memory Cycle•Can be useful for slower peripherals
IDLE
D4
Dynamic Ram SelectConfigures peripheral to operate in DRAM ModeMust be set for DMODE, DMUXS, and DMUXM
WSYNC and RSYNC are ignored when DRSEL = 1
DRSEL
D3
Enable Burst Capability for Chip Select•Must be turned on to support Burst memory cycles
BURST
D2
Write Protect Chip Select•Prevents any bus master from writing to the chip select•Useful for EEPROM and FLASH
WP
D1
Valid Bit•V bit enables the chip select•ALL other BAR and CSOR settings must be valid
V
D0
CSOR MASK
0000 0000
SDRAM
00FA 0000
0000 0000 + 16MBytes = 00FA 0000
FF000 is MASK setting for 16MBytes on NET+WorksBoard Support Package
Determining the MASK Setting for 16MBytes
LSB of MASK MUST be 4K
XXXX XXXX XXXX XXXX XXX1
4KBytesXXXX XXX1 0000 0000 0000
16MBytes
Therefore, extrapolation …
MemoryPeripheral
PhysicalSize
Mask Determines the Physical Size of the Chip Select•Base and Mask used to decode what CS is activated
CSOR Memory Aliasing with MASK
FF000 = 1111 1111 0000 0000 0000 16MByteTo Alias 4 Times on 64MByte Boundaries
FF000 F3000 = 1111 0011 0000 0000 0000 16MByte
BASE = 00000 0000 xx00 0000 0000 0000 = 0000 0000
0000 0000 00000100 0400 00001000 0800 00001100 0c00 0000
Quick Notes: •2(# of zeros) = # of repeats•Shift x bit right or left one position to increase or decrease boundary
To Alias 8 Times on 128MByte Boundaries88000 == F8000 == 1000 1000 0000 0000 0000 128MBytesBASE == 00000 == 00xx x000 0000 0000 0000 == 0000 0000
0000 0000 0000 00000000 1000 0800 00000001 0000 1000 00000001 1000 1800 00000010 0000 2000 00000010 1000 2800 00000011 0000 3000 00000011 1000 3800 0000
CSOR WAIT
WAIT
D11 Number of Wait States D8
Number of Wait States IN ADDITION To 2 BCLKS
BCLK
CS0*
WE*
T1 TW TW TW T2
BCLK
CS0*
WE*
T1 T2 T1 T2 T1
0 WaitStates
3 WaitStates
Note: For DRAM and ASYNC SRAM• 0000 and 0001 yield the same result
CSOR BCYC, BSIZE
BCYC
D7Number of Clocks forSubsequent Cycles D6
Controls the # BCLKS for SecondaryPortion of the Burst
00 1 BCLK in Length (x,1,1,1)01 2 BCLK in Length (x,2,2,2)10 3 BCLK in Length (x,3,3,3)11 4 BCLK in Length (x,4,4,4)
For SDRAM
CAS Latency BCYC Configuration
1
23
4
00
0110
11
BSIZE
D5 D4
Maximum# of Memory Cycles that can Occur in a Burst
00 2 System Bus Cycles01 4 System Bus Cycles10 8 System Bus Cycles11 16 System Bus Cycles
BSIZE Burst Length0001
10
11
2 Words (Not Supported)4 Words (Not Supported)
8 Words (Not Supported)
Full Page
BSIZE is Configurable to ALL Settings Only after Load Mode Command
CSOR PS, RSYNC, WSYNC
BCLK
CS0*
WE*
BCLKCS0*WE*
Read Cycle Synchronous Mode
RSYNC
D1
Write Cycle Synchronous Mode
WSYNC
D0
0 SRAM in ASYNC Mode1 SRAM in SYNC Mode
Asynchronous Mode Write
Synchronous Mode Write
Port Size
PS
D3PS Defines the Physical Interface of theMemory Peripheral00 32 Bit Port Size01 16 Bit Port Size10 8 Bit Port Size11 32 Bit Port with External TA*
D2
External SDRAM Multiplexing
Required Configuration•AMUX ‘1’•DMUXS ‘1’•PORTC3 Special Function
Output
PORTC3
SDRAM Write CommandSDRAM Read CommandSDRAM Load Mode Command•Driven on lower address lines
For AMUX2 UsageWhile PORTC3 is low ANDSDRAM issues ACTIVE Command
ACTIVE is CAS[3:1] == {011}
At ALL other Times, EBM Must Drive A23:A8. NET+50 Samples 1BCLK Before PORTC3 to ExamineCurrent SDRAM Page
CAS Address Driven
RAS Address Driven
Lower Address
Bits
Upper Address
Bits
Pin Configuration
SRAM
FP
EDO
SDRAM
Mode A13:0 CSx* CAS3* CAS2* CAS1* CAS0* OE* WE*
CS*
RAS*
RAS*
CS*
CAS3*
CAS3*
RAS* CAS*
CAS2*
CAS2* CAS1*
CAS1*
WE* A10/AP
CAS0*
CAS0*
OE*
OE*
OE*
WE*
WE*
WE*
Address
Address
Address
-- -- -- -- --
-- --
Other Address Lines are Driven with Logical Address
A31:A28 (Internally) are copied from A27:A24
Bus MappingD31 D24 D23 D16 D15 D8 D7 D0
Byte Enable 3BE3*
Byte Enable 2BE2*
Byte Enable 1BE1*
Byte Enable 0BE0*
8-Bit Devices
16-Bit Devices
32-Bit Devices
A0
32 Bit Data Bus
A1 A2 A28
LSB for ALL 32 Bit Devices
LSB for ALL 16 Bit Devices
LSB for ALL 8 Bit Devices
Address Bus Connections
NET+ARM to FLASH / SRAM Connections
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18
CE*OE*WE*
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
D16D17D18D19D20D21D22D23D24D25D26D27D28D29D30D31
A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19
NOTE: Not All Signals Shown
Figure 1
Figure 1
CE*OE*WE*
SRAM / Conventional FLASH
CSxOE*WE*
CE*OE*WE*
FLASH
GROUNDA27/CS0OE*A26/CS0WE*
NET+ARM Pins
NET+ARM to SDRAM Connections
A0A1A2A3A4A5A6A7A8A9A10/APA11A12/BS1A13/BS0
DQMUDQML
WE*RAS*CAS*CS*
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
64M SDRAM
NOTE: Not All Signals Shown
A2A3A4A5A6A7A8A9A10A11CAS0*A13A22A23
BE3*BE2*
CAS1*CAS3*CAS2*CS/RAS*
DEVICE 1D16D17D18D19D20D21D22D23D24D25D26D27D28D29D30D31
A0A1A2A3A4A5A6A7A8A9A10/APA11A12/BS1A13/BS0
DQMUDQML
WE*RAS*CAS*CS*
D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
64M SDRAM
A2A3A4A5A6A7A8A9A10A11CAS0*A13A22A23
BE1*BE0*
CAS1*CAS3*CAS2*CS/RAS*
DEVICE 2D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
Static Memory Controller
Memory Controller
OE* Output Enable
WE* Write Enable
BE[3:0]* Byte Enables
RW* Read / Write Strobe
ADDR[28:0] Address Bus
SRAMMemory Devices
FPGA
A/DConverters
Myriad of SRAMType Interface Devices
TA* Transfer Acknowledge
Asynchronous SRAM cycles operate a minimum1 wait state at ALL times
TA* Transfer Acknowledge
Suggested Memory Subsystems
16 Bit Flash (512K x 16) 32 Bit SRAM (128K/256K x 32)32 Bit SDRAM (2M x 32)
System BusA0 A1 A2 D31 : D16
FLASHA0 D15 : D0
A0 A1 A2 D31 : D0
SRAM/SDRAMA0 D15 : D0
• SRAM (X32)– Pros
• Extremely Fast• More Direct Interface• Suitable for Battery
Backed Applications– Cons
• Lower Densities• More $$
– Very efficient when used with FLASH executions w/ cache
• SDRAM (X32)– Pros
• More Density / $$• Large Densities Available• Fairly fast
– Cons• More Complex Interface• Timing is more Strict
Memory Controller Summary
• Relevant registers– One global Memory Module Control Register– One Base Address Register and one options
register per Chip Select• Control and Bus Controller’s address line
usage is dictated by device characteristics• External SDRAM multiplexing possible via
PORTC3