the imagination driving australia’s ict future.cs9242/06/lectures/08-hw.pdf · the imagination...

The imagination driving Australia’s ICT future.

HARDWARE AND POWER MANAGEMENT

David Snowdon

[email protected]

➀ About me

➁ How hardware exists

➂ Power management

SEPTEMBER 15, 2006 HARDWARE AND POWER MANAGEMENT. . . 1


ABOUT ME➜ Computer Engineering 1999–2002

➜ Honours: Hardware and Software Infrastructure for Sunswift II

➜ PhD: Operating system directed power management

➜ Solar cars: WSC (99, 01, 03, 05)

SEPTEMBER 15, 2006 ABOUT ME 2


IBOX

➜ purpose: intelligent video surveillance;

➜ 624MHz Xscale (PXA270), 64MB RAM, 4MB Flash;

➜ analogue video capture, overlays, MPEG 4 encoding, audio;

➜ USB, CF, Ethernet;

➜ designed for L4/Iguana (OK inside).



HARDWARE

HARDWARE

aka: convincing yourself that it just might work

SEPTEMBER 15, 2006 HARDWARE 5


OVERVIEW

Overview:

➜ why talk about hardware design in an OS course?

➜ hardware designs are difficult to change

Because:

➜ Operating systems interact closely with the hardware

➜ Hardware and system software engineers should work together

➜ OS developers are great embedded systems developers

➜ OS people think this stuff is cool



OVERVIEW

Case Study: the iBox:

➜ requirements;

➜ general design;

➜ schematics;

➜ layout;

➜ manufacture;

➜ board bring-up.



REQUIREMENTS

Purpose:

➜ processing platform for digital video surveillance;

➜ teaching platform for AOS.



REQUIREMENTS

Purpose:

➜ processing platform for digital video surveillance;

➜ teaching platform for AOS.

Video surveillance:

➜ motion detection;

➜ number recognition;

➜ face recognition.

SEPTEMBER 15, 2006 HARDWARE 8-A


REQUIREMENTS

Functional:

➜ Performance: five frames per second at 352 × 288;

➜ IO: Ethernet, audio, video, alarm, overlay;

➜ Video compression: MPEG4 at 768 × 576;

➜ System software update: by an engineer on-site;

➜ Power supply: up to 24V AC or DC;

➜ Power consumption: less than 5W.

➜ Software interfaces: video, audio, network stack, overlay

generation, MPEG compression



REQUIREMENTS

Non-functional:

➜ Cost

➜ Modularity

➜ Size

➜ Development time

➜ Connectors: standard

➜ Un-trusted software.



REQUIREMENTS

Non-functional:

➜ Cost

➜ Modularity

➜ Size

➜ Development time

➜ Connectors: standard

➜ Un-trusted software.

It should cost nothing, use no power, be infinitely small, and

take no time to develop. What’s the problem?



REQUIREMENTS

Trade-offs:

➜ Cost vs. Performance

➜ Size vs. Performance

➜ Size vs. Utility

➜ Power vs. Performance

➜ Time vs. everything

➜ Cost vs. Quantity

➜ In-house vs. out-sourcing



REQUIREMENTS

Summary:

➜ MPEG 4 requires serious processing grunt;

➜ Motion detection requires serious processing grunt;



DESIGN

Strategy:

➀ come up with lots of options;

➁ pick one that best fits the requirements;

➂ lather, rinse, repeat;

➃ work out that you’ve made a mistake as early as possible.

We’ll go through a few of the design decisions we made here



DESIGN

FPGA:

➜ Field Programmable Gate Array

➜ RAM + logic == configurable IC

➜ “programmed” using VHDL, Verilog, etc.

➜ can use soft cores



DESIGN

FPGA:

➜ Field Programmable Gate Array

➜ RAM + logic == configurable IC

➜ “programmed” using VHDL, Verilog, etc.

➜ can use soft cores

For:

V high performance

V low power

Against:

X difficult to implement algorithms

X some expensive soft-cores

X no L4



DESIGN

DSP:

➜ Digital signal processor

➜ VLIW processors optimised for signal processing

➜ e.g. TI TMS320C6416: 8 GMACs/s @ 1GHz



DESIGN

DSP:

➜ Digital signal processor

➜ VLIW processors optimised for signal processing

➜ e.g. TI TMS320C6416: 8 GMACs/s @ 1GHz

For:

V very high signal processing performance

V various implementations with video interfaces

Against:

X no MMU

X optimisation required to achieve performance

X expensive compilers



DESIGN

Digital signal processor + Generic processor:

➜ use a general-purpose processor for control

➜ use a DSP for signal processing algorithms

➜ often packaged together (e.g. TI OMAP, DaVinci)



DESIGN

Digital signal processor + Generic processor:

➜ use a general-purpose processor for control

➜ use a DSP for signal processing algorithms

➜ often packaged together (e.g. TI OMAP, DaVinci)

For:

V solves lots of problems with a DSP alone

V easier to handle real-time issues

Against:

X higher software complexity than a single-core solution

X need more than one DSP for our application



DESIGN

General-purpose processor:

➜ optimised for a wide range of tasks



DESIGN

General-purpose processor:

➜ optimised for a wide range of tasks

For:

V good support from compilers and operating systems

V MMU

V system-on-a-chip designs make implementation easier/smaller

Against:

X very high required performance == high power, large size

X not optimised for signal processing

X not capable of MPEG 4 encode



DESIGN

SMP:

➜ multiple generic cores



DESIGN

SMP:

➜ multiple generic cores

For:

V high performance

V retains generic capabilities while providing processing power

V OS transparently handles multiprocessing

Against:

X large size

X high power

X higher parts count



DESIGN

What next?:

➜ rough out the designs: identify components

➜ don’t worry about the easy bits (PSU, connectors)

➜ obtain development kits and test performance

➜ look at how well the software fits the design

Calculate:

➜ cost

➜ parts count

➜ part availability

➜ power consumption



DESIGN

What we considered:

➀ PXA270

➁ TI DaVinci

➂ Sierra MIPS



DESIGN

What we considered:

➀ PXA270

➁ TI DaVinci

➂ Sierra MIPS

We chose the PXA270, combined with an external MPEG 4

codec ASIC



DESIGN

PXA270 based solution:

➜ 624MHz XScale (ARM) core — fast enough for video algorithms

➜ quick-capture interface for video input

➜ tricky circuit for overlay generation

➜ other useful built-in peripherals (DMA, SRAM, USB, CF, LCD)

V L4 was already ported

V good Linux support

V MMX and DSP instructions

V very low power



DESIGN

PXA270 based solution:

➜ 624MHz XScale (ARM) core — fast enough for video algorithms

➜ quick-capture interface for video input

➜ tricky circuit for overlay generation

➜ other useful built-in peripherals (DMA, SRAM, USB, CF, LCD)

V L4 was already ported

V good Linux support

V MMX and DSP instructions

V very low power

X requires some expensive PCB technologies



DESIGN



SCHEMATICS

Schematics:

➜ schematics define how components connect logically

➜ component pins are connected to form nets

➜ hierarchical schematics are possible via ports



SCHEMATICS

Defining components:

➀ schematic component

➁ footprint



SCHEMATICS

Things to think about:

➜ get it right first time

➜ decoupling – reduce power supply noise

➜ regulator noise

➜ pin assignment – shortest paths

➜ DMA

Hardware should be designed to make software elegant


1

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2

2

3

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4

4

D D

C C

B B

A A

1

National ICT AustraliaLevel 4223 ANZAC PdeKensington, Sydney, 2052AUSTRALIA17

Top level schematic for iBox

112/09/2006 11:28:57 PMZ:\projects\ibox\design\toplevel.SCHDOC

Title

Size: Number:

Date:File:

Revision:

Sheet ofTime:

A4

PWR_EN

SYS_EN

nBATT_FAULTnVDD_FAULT

nRESET_OUT

nTRSTnRESETTCK

TMSTDI

TDO

nSRST

U_CPU_B CPU_B.SCHDOC

MA[0..24]MD[0..31]

nCS

nWEnOEnRP

U_FlashFlash.SCHDOC

MA[0..24]MD[0..31]DQM[0..3]

nSDCASnSDRAS

nWE

SDCLKSDCKEnSDCS

U_SDRAMSDRAM.SCHDOC

nRESET

nCSINT

nRDnWR

nDATACSRDY

DQM[0..3]

MA[0..24]MD[0..31]

U_LAN91C111LAN91C111.SCHDOC

VDATA[0..9]PCLK

VSYNCHSYNC

AVID

nPDN

FID/GLCOnINT

nRESET

SCLSDA

BLANK_IN

BLANK

OUT_ENABLE

PCLK_DIV2

ALT_VIDEO_OUT

U_tvp5150tvp5150.SCHDOC

SDINSDOUT

LRCLKMCLKSCLK

SDASCL

RESET

U_CS4270CS4270.SCHDOC

MA

[0..2

4]M

D[0

..31]

DQ

M[0

..3]

nWE

nOE

nSDRASnSDCAS

SDCKESDCLK1

nSDCS0

nCS0

I2S_BITCLK

I2S_SDATA_INI2S_SDATA_OUT

I2S_SYNCI2S_SYSCLK

FFR

XD

FFC

TS

FFT

XD

FFR

TS

SSPSFRM

SSPTXD

SSPSCLKEN

nCS1

PWM

_OU

T0

RD

Y

INT

0

INT1

PWR

_SC

LPW

R_S

DA

SCLSDA

LD

D_[

0..1

7]

L_F

CL

K_R

D

L_L

CL

K_A

0L

_PC

LK

_WR

L_B

IAS

nCS2

PSKTSEL

nCS3

CIF_FVCIF_LVCIF_PCLK

nPWE

nPIOIR

nPIOIW

nPCE2

nPREG

nPCE1nPOE

nIOIS16

nPWAIT

VDATA[0..9]

SSPSCLK

GPIO22

GPIO13GPIO11

INT

3 INT4

INT5

RDnWR

GPIO52

GPIO94GPIO20

GPIO101

GPIO96

GPI

O32

GPI

O40

GPI

O26

USB

H_P

USB

H_N

USB

HPE

NU

SBH

PWR

DR

EQ

1

GPI

O11

2

GPI

O10

9

PWM_OUT1

GPI

O11

4

GPIO42

GPI

O92

GPI

O39

U_CPU_ACPU_A.SCHDOC

RDnWRnPSKTSEL MD[0..31]

MA[0..24]

nPWEnPREG

nCD1nCD2

nPIOWR

nPWAIT

nPIOIS16nPOEnPCE1nPCE2nPIOR

nIREQ

RESET

nINPACKnDASP

nSTSCHG

U_cfcf.SCHDOC

VINSCLKSDAT

3V3_ENABLE

VCORE_ENABLELDO_EN

INT

nBATTFLT

nRESETnVDDFLT

2V5_ENABLE

U_PowerPower.SCHDOC

VOUT

U_Power_inPower_in.SCHDOC

nRESET_OUT

R46

3k3C57

100n

GND

R4710k

GND

nRESET_OUT

nRESET_OUT

nPWE

nPWEnRESET_OUT

nRESET_OUT

nRESET_OUT

12345678

J9

CON8

VCC_IO

GND

DQM[0..3]MD[0..31]MA[0..24]

LE

D0

LE

D1

LE

D2

LE

D3

USB

_P

USB

_EN

US

B_N

USB

_OC

nRE

LA

Y

U_misc

misc.SCHDOC

HADDR[0..5]HDATA[0..15]nCS

nRDnWR

INT

CA_PCK1CA_FIELD

CA_DVALIDCA_VSYNC

CA_DIN[0..7]

MCLK

nRSTWAKEUP

VID_OUT

SDASCK

U_MPEGMPEG.SCHDOC

VDATA[0..9]VPCLK

VPCLK

VDATA[0..9]

VAVID

VVSYNCVHSYNC

VFID

VVSYNCVAVIDVFID

VPCLK

Vin 5V

MPEG_VIDEO_OUT

MPE

G_V

IDE

O_O

UT

TX

DR

TS

RX

D

L_L

CL

K_A

0

L_F

CL

K_R

D

LD

D_[

0..1

7]L

_PC

LK

_WR

L_B

IAS

CT

S

L_V

ctrl

nLC

D_R

ST

U_MISC2MISC2.SCHDOC

LD

D_[

0..1

7]SCLSDA

SDASCL

1234567891011121314151617181920

J24

CON20

nTRST

TDI

TMS

TCK

TDO

nRST

nRST

nTRSTTCKTDITMSTDO

VCC_IO

C14

100u

F, 1

0V

GND

SEPTEMBER 15, 2006 HARDWARE 26-1

1

1

2

2

3

3

4

4

D D

C C

B B

A A

2


CPU A

2 *12/09/2006 11:33:37 PMZ:\projects\ibox\design\CPU_A.SCHDOC

Title

Size: Number:

Date:File:

Revision:

Sheet ofTime:

A4

GPIO15A3

GPIO49A10

GPIO47A11

GPIO113 A13

GPIO28A14

GPIO37A15

GPIO24A17

GPIO16A18

GPIO92 A19

GPIO32A20

GPIO34A21

GPIO118 A22

GPIO33B6

GPIO78 B7

GPIO18B9

GPIO12B10

GPIO46B11

GPIO29B13

GPIO38B14

GPIO26B15

GPIO23B16

GPIO110 B17

GPIO112B18

GPIO35B19

GPIO44B20

GPIO80 C7GPIO79 C8

GPIO13C10

GPIO11C11

GPIO31C12 GPIO30C13

GPIO36C14

GPIO27C15

GPIO17C16

GPIO111 C17

GPIO41C18

GPIO45C19

GPIO42C21

GPIO43C22

GPIO88 C23

GPIO116 C24

GPIO22D13

GPIO40D14

GPIO25D16

GPIO109 D17

GPIO39D19

GPIO117 D20

GPIO89 D22

GPIO114 D24

GPIO115 E21

GPIO90 F22

GPIO91F23

GPIO59G22

GPIO60G23

GPIO58G24

GPIO62 H22

GPIO63 H23

GPIO61 H24

GPIO64 J22

GPIO66K22

GPIO67 K23

GPIO65 K24

GPIO68 L21

GPIO71 L22

GPIO69 L23

GPIO73 M22

GPIO70 M24

GPIO86 N22

GPIO87 N23

GPIO72 N24

GPIO76 P22GPIO75 P23

GPIO77R21

GPIO19R22

GPIO74 R23

GPIO14T24

GPIO9U22

GPIO0V22

GPIO10V23

GPIO3W21

GPIO4W23

GPIO1Y24

GPIO55AA10

GPIO84AA11

GPIO54AA14

GPIO97 AA17

GPIO95 AA18

GPIO20AB6

GPIO56AB11

GPIO81 AB12

GPIO50AB13

GPIO53AB14

GPIO106 AB15GPIO105AB16

GPIO102 AB17

GPIO99 AB18

GPIO93 AB19

GPIO57AC11

GPIO85 AC12

GPIO48AC13

GPIO52AC14

GPIO107 AC15

GPIO103 AC16

GPIO101 AC17GPIO100 AC18

GPIO96 AC19

GPIO21AD5 GPIO82 AD9

GPIO83 AD10

GPIO51AD13

GPIO108 AD14

GPIO104 AD15

GPIO98AD18

GPIO94 AD19

U4A

PXA270

MA1A6

MA18C1

MA22C2

MA24C4

MA0C6

MA17D1

MA21D2

MA23D4

MA25D6

MA13E1

MA19E3

MA20E4

MA14F2

MA16F3

MA8G1

MA11G2

MA12G3

MA15G4

MA9H2

MA10H3

MA3J1

MA6J2

MA7J3

MD15 K1

MA4K2

MA5K3

MA2K4

MD14 L1

MD31L2MD30 M2MD29 M3

MD13 M4

MD27 N1

MD28 N2

MD12 N3MD11 P2

MD26 P3

MD10P4

MD24R1

MD25 R3

MD9 R4

MD23 T1

MD8 T3MD7 U1

MD5 U4

MD21 V1

MD22 V2

MD6 V3

MD20 W1MD19 Y1

MD4 Y2MD3Y3

MD18 AA1

MD2 AA3

MD16 AA4

MD1 AB1

MD17AB3

MD0 AB4U4F

PXA270

USBC_PB22

USBC_NC20

USBH_N1D23 USBH_P1E22

UIOE23

U4G

PXA270

nCS0B3

RDnWRC9

nSDCASAA6

nWEAB5

nSDCS0AB7

nSDCS1AB8

DQM0AB9

DQM1AB10

SDCLK0AC4

nOEAC5

nSDRASAC7

DQM2AC9

DQM3AC10

SDCLK2AD3

SDCKEAD6

SDCLK1AD7

U4I

PXA270

MA[0..24]MD[0..31]

MA0MA1MA2MA3MA4MA5MA6MA7MA8MA9MA10MA11MA12MA13MA14MA15MA16MA17MA18MA19MA20MA21MA22MA23MA24

MD0MD1MD2MD3MD4MD5MD6MD7MD8MD9MD10MD11MD12MD13MD14MD15MD16MD17MD18MD19MD20MD21MD22MD23MD24MD25MD26MD27MD28MD29MD30MD31

DQM[0..3]nWEnOE

nSDRASnSDCAS

SDCKE

SDCLK1

nSDCS0

nCS0

Design guide recommends: 20 ohm eries termination is required on the SDCAS and SDCLK lines. Not required on other lines. Requires a "Balanced T" layout. See the PXA270 design guide.

I2S_BITCLKI2S_SDATA_IN

I2S_SDATA_OUTI2S_SYNC

I2S_SYSCLK

FFRXDFFCTS

FFTXD

FFRTS

SSPSCLKSSPSFRM

SSPTXD

SSPSCLKEN

nCS1PWM_OUT0

RDY

R2210k

VCC_MEM

INT0INT1

PWR_SCLPWR_SDA

SCLSDA

R2310k

VCC_IO

R2410k

R1810k

VCC_BATT

R1910k

LDD_0LDD_1LDD_2

LDD_3LDD_4LDD_5LDD_6LDD_7LDD_8LDD_9LDD_10LDD_11LDD_12LDD_13LDD_14LDD_15

LDD_[0..17]LDD_[0..17]

L_FCLK_RDL_LCLK_A0

L_PCLK_WRL_BIAS

LDD_16LDD_17

nCS2

PSKTSEL

nCS3

CIF_PCLK

VDATA0

VDATA4VDATA5

VDATA6

VDATA1

VDATA2VDATA3

VDATA7

VDATA8VDATA9

VDATA[0..9]

nPWEnPIOIR

nPIOIW

nPCE2nPREG

nPCE1

nPOE

nIOIS16nPWAIT

CIF_FVCIF_LV

GPIO22

GPIO13

GPIO11

INT3

INT4

INT5

RDnWR

GPIO52

GPIO20

GPIO101

GPIO94

GPIO96

VDATA[0..9]

MA[0..24]

DQM0DQM1

DQM2DQM3

DQ

M[0

..3]

USBHPWRUSBHPEN

GPIO32

GPIO40

GPIO26

USBH_PUSBH_N

DREQ1

GPIO112

GPIO109

MD[0..31]

GPIO114

PWM_OUT1

GPIO42

GPIO39

GPIO92

SFRM

SFRM

B17 is connected to SFRM to ease layout

R20 22R

R14 22R


1

1

2

2

3

3

4

4

D D

C C

B B

A A

4

*Level 4223 ANZAC PdeKensington, Sydney, 2052AUSTRALIA17

RAM

4 *12/09/2006 11:37:29 PMZ:\projects\ibox\design\SDRAM.SCHDOC

Title

Size: Number:

Date:File:

Revision:

Sheet ofTime:

A4

VDD 1

DQ0 2

VDDQ 3

DQ1 4

DQ2 5

VSSQ 6

DQ37

DQ4 8

VDDQ 9

DQ5 10

DQ6 11

VSSQ 12

DQ7 13

VDD 14

DQML15

WE16

CAS17

RAS18

CS19

BA020

BA121

A1022

A023

A124

A225

A326

VDD 27

VSS28

A429

A530

A631

A732

A833

A934

A1135

A1236

CKE37CLK38

DQMH39

NC40

VSS 41

DQ8 42

VDDQ 43

DQ9 44

DQ1045

VSSQ 46

DQ11 47

DQ12 48

VDDQ49

DQ13 50

DQ14 51

VSSQ 52

DQ15 53

VSS 54

U12

VDD 1

DQ0 2

VDDQ 3

DQ1 4

DQ2 5

VSSQ 6

DQ37

DQ4 8

VDDQ 9

DQ5 10

DQ6 11

VSSQ 12

DQ7 13

VDD 14

DQML15

WE16

CAS17

RAS18

CS19

BA020

BA121

A1022

A023

A124

A225

A326

VDD 27

VSS28

A429

A530

A631

A732

A833

A934

A1135

A1236

CKE37CLK38

DQMH39

NC40

VSS 41

DQ8 42

VDDQ 43

DQ9 44

DQ1045

VSSQ 46

DQ11 47

DQ12 48

VDDQ49

DQ13 50

DQ14 51

VSSQ 52

DQ15 53

VSS 54

U11

MA[0..24]MD[0..31]

MD0MA10

VCC_MEM

GND

DQM[0..3]

DQM0DQM1

DQM2DQM3

SDCLKSDCKE

nSDCS

nSDCASnSDRAS

SDCLKSDCKE

nSDCSnWEnSDCASnSDRAS

SDCLKSDCKE


VCC_MEM

GND

nWE

MA11MA12MA13MA14MA15MA16MA17MA18MA19MA20MA21MA22

MA23MA24

MA10MA11MA12MA13MA14MA15MA16MA17MA18MA19MA20MA21MA22

MA23MA24

MA[0..24]MD[0..31]

DQM[0..3]

MD1MD2MD3MD4MD5MD6MD7MD8MD9MD10MD11MD12MD13MD14MD15

MD16MD17MD18MD19MD20MD21MD22MD23MD24MD25MD26MD27MD28MD29MD30MD31

C16

610

0nC

167

100n

C16

810

0nC

169

100n

C17

010

0nC

171

100n

C17

210

0nC

173

100n

C17

410

0nC

175

100n

C17

610

0nC

177

100n

VCC_MEM

GND GND

VCC_MEM


1

1

2

2

3

3

4

4

D D

C C

B B

A A

5


Flash memory

5 *12/09/2006 11:37:37 PMZ:\projects\ibox\design\Flash.SCHDOC

Title

Size: Number:

Date:File:

Revision:

Sheet ofTime:

A4

A151 A142 A133 A124 A115

A106 A97 A88

A219 A2010

WE11

RP12

VPP13

WP 14

A1915 A1816A1717

A718 A619 A520 A421

A322 A223 A124 A025

CE26

GND 27

OE28

DQ029

DQ8 30

DQ1 31

DQ9 32

DQ2 33

DQ10 34

DQ3 35

DQ11 36

VCC 37

DQ4 38

DQ12 39

DQ5 40

DQ13 41

DQ6 42

DQ1443

DQ744

DQ15 45

GND 46

VCCQ 47

A1648

U8

MA[0..24]MD[0..31]

nCSnWEnOEnRP

VCC_MEM

nCEnWEnOEnRP

GND VCC_MEM

MA[0..24]MD[0..31]


MA1MA2MA3MA4MA5MA6MA7MA8MA9MA10MA11MA12MA13MA14MA15MA16MA17MA18MA19MA20MA21MA22

VCC_MEM

GND

C16

110

0nC

162

100n

C16

310

0n


1

1

2

2

3

3

4

4

D D

C C

B B

A A

4


RAM

4 *12/09/2006 11:37:29 PMZ:\projects\ibox\design\SDRAM.SCHDOC

Title

Size: Number:

Date:File:

Revision:

Sheet ofTime:

A4

VDD 1

DQ0 2

VDDQ 3

DQ1 4

DQ2 5

VSSQ 6

DQ37

DQ4 8

VDDQ 9

DQ5 10

DQ6 11

VSSQ 12

DQ7 13

VDD 14

DQML15

WE16

CAS17

RAS18

CS19

BA020

BA121

A1022

A023

A124

A225

A326

VDD 27

VSS28

A429

A530

A631

A732

A833

A934

A1135

A1236

CKE37CLK38

DQMH39

NC40

VSS 41

DQ8 42

VDDQ 43

DQ9 44

DQ1045

VSSQ 46

DQ11 47

DQ12 48

VDDQ49

DQ13 50

DQ14 51

VSSQ 52

DQ15 53

VSS 54

U12

VDD 1

DQ0 2

VDDQ 3

DQ1 4

DQ2 5

VSSQ 6

DQ37

DQ4 8

VDDQ 9

DQ5 10

DQ6 11

VSSQ 12

DQ7 13

VDD 14

DQML15

WE16

CAS17

RAS18

CS19

BA020

BA121

A1022

A023

A124

A225

A326

VDD 27

VSS28

A429

A530

A631

A732

A833

A934

A1135

A1236

CKE37CLK38

DQMH39

NC40

VSS 41

DQ8 42

VDDQ 43

DQ9 44

DQ1045

VSSQ 46

DQ11 47

DQ12 48

VDDQ49

DQ13 50

DQ14 51

VSSQ 52

DQ15 53

VSS 54

U11

MA[0..24]MD[0..31]

MD0MA10

VCC_MEM

GND

DQM[0..3]

DQM0DQM1

DQM2DQM3

SDCLKSDCKE

nSDCS

nSDCASnSDRAS

SDCLKSDCKE


SDCLKSDCKE


VCC_MEM

GND

nWE

MA11MA12MA13MA14MA15MA16MA17MA18MA19MA20MA21MA22

MA23MA24


MA23MA24

MA[0..24]MD[0..31]

DQM[0..3]

MD1MD2MD3MD4MD5MD6MD7MD8MD9MD10MD11MD12MD13MD14MD15


C16

610

0nC

167

100n

C16

810

0nC

169

100n

C17

010

0nC

171

100n

C17

210

0nC

173

100n

C17

410

0nC

175

100n

C17

610

0nC

177

100n

VCC_MEM

GND GND

VCC_MEM


1

1

2

2

3

3

4

4

D D

C C

B B

A A

6


Network interface

612/09/2006 11:32:03 PMZ:\projects\ibox\design\LAN91C111.SCHDOC

Title

Size: Number:

Date:File:

Revision:

Sheet ofTime:

A4

MD[0..31]

GND

GND

GND

MA2

MA[0..24]

nRESET

GND

R1110k

nCS

INT

SRDY43

A178

A279

A380

A481

A582

A683

A784

A885

A986

A1087

A1188

A1289

A1390

A1491

A1592

ADS37

ARDY38

VLBUS40

LCLK42

AEN41

RESET30

W/R36

RD31

WR32

CYCLE35 DATACS34

LDEV45

RDYRTN46

INTR029 CNTRL28

BE

094

BE

195

D0

107

D1

106

D2

105

D3

104

D4

102

D5

101

D6

100

D7

99

D8

76

D9

75

D10

74

D11

73

D12

71

D13

70

D14

69

D15

68

IOS0

3

IOS1

4

IOS2

5

EN

EE

P6

EE

SK9

EE

CS

10

EE

DO

7

EE

DI

8

CSO

UT

2

XT

AL

112

7

XT

AL

212

8

RX

D2

122

RX

D1

123

RX

D3

121

RBIAS12

X25

OU

T47

RX

D0

124

RX

_ER

126

RX

_DV

125

TPI+ 17

TPI- 18

LEDA 22

LEDB 23

TPO+14

TPO- 15

LNK 20

LBK 21

MC

LK

27

CR

S100

119

MD

I25

MD

O26

AVDD 16

AVDD 11

AGND 19

AGND 13

VDD 98

VDD 77

VDD 62

VDD 44

VDD 33

VDD1

GND 103

GND 93

GND 72

GND 67

GND57

GND 52

GND 39

GND 24

D16

66

D17

65

D18

64

D19

63

D20

61

D21

60

D22

59

D23

58

D24

56

D25

55

D26

54

D27

53

D28

51

D29

50

D30

49

D31

48

BE

296

BE

397

RX

2511

8T

XD

011

6T

XD

111

5T

XD

211

4T

XD

311

3C

OL

100

112

TX

EN

100

111

GND 117

GND 108

VDD 110VDD120

TX

2510

9

U1

LAN91C111

nRDnWR

nDATACS

GND

RDY

GND

Y125MHz

C115pF

C215pF

GND

GND

R11k

R21k

TxCT1

Tx+2

Tx-3

Rx+4

Rx-5

RxCT6

Shield7

J1

R5

25R

R6

25R

C3100n

R7 25RR8 25R

C4

100nGND

GND

R3

50R

R4

50R

R9 11k

GND

C11

100n

C10

100n

C9

100n

C8

100n

C7

100n

C6

100n

C5

100n

GND

R1210k

Q1

MA[0..24]

MD[0..31]

C12

100n

R1010k

VCC_MEM

VCC_MEM

DQM[0..3]DQM[0..3]

DQ

M0

DQ

M1

DQ

M2

DQ

M3

VCC_MEM

VCC_MEM

VCC_MEM

VCC_MEM

VCC_MEM VCC_MEM VCC_MEM VCC_MEM

VCC_MEM


R1310k

VCC_MEM

MD

0M

D1

MD

2M

D3

MD

4M

D5

MD

6M

D7

MD

8M

D9

MD

10M

D11

MD

12M

D13

MD

14M

D15

MD

16M

D17

MD

18M

D19

MD

20M

D21

MD

22M

D23

MD

24M

D25

MD

26M

D27

MD

28M

D29

MD

30M

D31

D1A D1B

Remember that RDY needs a pullup elsewhere in the system

C120

100n


1

1

2

2

3

3

4

4

D D

C C

B B

A A

7

National ICT AustraliaLevel 4223 ANZAC PdeKensingtonNSW, 205217

Compact Flash

712/09/2006 11:34:30 PMZ:\projects\ibox\design\cf.SCHDOC

Title

Size: Number:

Date:File:

Revision:

Sheet ofTime:

A4

GND1

D032

D043

D054

D065

D076

nCE1 7

A108

nOE 9

A0910 A0811

A0712

VCC13

A0614

A0515

A0416

A0317

A0218

A0119

A0020

D0021 D0122

D0223

nIOIS16 24

nCD2 25nCD1 26

D1127

D1228

D1329

D1430

D1531

nCE2 32

nVS1 33

nIORD 34

nIOWR35

nWE 36nIREQ 37

VCC38

nCSEL 39

nVS2 40

RESET 41

nWAIT 42

nINPACK 43nREG44

nSPKR 45

nSTSCHG46

D0847

D0948 D1049

GND50

J2

Compact Flash

1DIR1

1B02

1B13

GND4

1B25

1B36

VCC 7

1B48

1B59

GND10

1B611

1B712

2B013

2B114

GND15

2B216

2B317

VCC18

2B419

2B520

GND21

2B622

2B723

2DIR 24

2OE 25

2A7 262A6 27

GND28

2A5 292A4 30

VCC 31

2A3 322A2 33

GND34

2A1 352A0 36

1A7371A6 38

GND39

1A5 401A4 41

VCC 42

1A3 431A2 44

GND45

1A1 461A047

1OE 48

U2

74LVT162245

MD0MD1

MD2

MD3

MD4

MD5

MD6

MD7

MD8

MD9MD10

MD11

MD12

MD13

MD14

MD15

MA0MA1

MA2MA3

MA4MA5

MA6MA7

MA8MA9

MA10

GND

VCC_MEM

GND GND

OE11

O02

O1 3

GND4

O2 5

O3 6

VCC7

O4 8

O5 9

GND10

O6 11

O712

O8 13

O9 14

GND15

O10 16

O11 17

VCC18

O12 19

O13 20

GND21

O1422

O15 23

OE4 24OE3 25

I1526 I1427

GND28

I1329 I1230

VCC31

I1132I1033

GND34

I935 I836 I737 I638

GND39

I540 I441

VCC42

I343 I244

GND45

I146 I047

OE2 48

U3

74LVT162244

GNDRDnWRnPSKTSEL

VCC_MEM

MD[0..31]MD[0..31]

MA[0..24] MA[0..24]

VCC_MEM

GNDnPWE

nPREG

nCD1nCD2

nPIOWR

nPWAIT

nPIOIS16

nPOE

nPCE1nPCE2

nPIOR

nIREQ

R1710k

VCC_MEM

nPSKTSEL

RESET

VCC_MEM

VCC_MEM

GND

nINPACK

nDASPnSTSCHG

C13100u

GND

VCC_MEM

R16

A10

K

R16

B10

KR

16D

10K

R16

C10

KR

1510

kR

104

10k

C12

410

0nC

125

100n

C12

610

0nC

127

100n

VCC_MEM

GND

C13

010

0nC

131

100n

C13

210

0nC

133

100n

VCC_MEM

GND

C12

810

0n

VCC_MEM

GND


1

1

2

2

3

3

4

4

D D

C C

B B

A A

8


Audio Codec

8 *12/09/2006 11:37:47 PMZ:\projects\ibox\design\CS4270.SCHDOC

Title

Size: Number:

Date:File:

Revision:

Sheet ofTime:

A4

SDINSDOUT

MCLK

SDASCL

R29

47k

Selects master mode

GND

GND GND

RESET

VCC_IO

R28 3k32, 1%

R31

6k65

, 1%

C18 10u

C20

2200

p, C

OG

GND GND GND GND

C22 3.3u

R3510k

R3610k

R34 470R

R33 470R

C24

3300

p, C

OG

GND GND GND GND

C29100n

C281uF

GND GND

C31100n

C301uF

GND GND

C33100n

C3247u

GND GND

SDIN1

LRCK2

MCLK3

SCLK4

VD5

DGND6

SDOUT7

VLC8

SDA9

SCL10

AD011

AD112

AD213

RST14

AINA 15

AINB 16

VQ 17FILT+ 18

VA 19

AGND 20

MUTEA 21

MUTEB 24

AOUTA 22

AOUTB 23

U6

CS4270

C27100n

C261uF

GND GND

VCC_IO

LRCLK

SCLK

12

J3

CON2

12

J4

CON2

12

J5

CON2

12

J6

CON2

GND

GND

GND

GND

VOUT 5VIN

1V

SS2

U7XC6201

Vin

GND

C351uF

GND

C341uF

GND

3.3V XC6201

C21

2200

p, C

OG

R30 3k32, 1%

R32

6k65

, 1%

C19 10u

C23 3.3u

C25

3300

p, C

OG

12

J17

CON2

12

J18

CON2

12

J19

CON2

12

J20

CON2

GND

GND

GND

GND

Pin headers for off-board connectorsPCB Connectors

GND


1

1

2

2

3

3

4

4

D D

C C

B B

A A

11


Video decoder and overlay generation

11 *12/09/2006 11:32:41 PMZ:\projects\ibox\design\tvp5150.SCHDOC

Title

Size: Number:

Date:File:

Revision:

Sheet ofTime:

A4

AIP1A1

AIP1B2

PLL_AGND3 PLL_AVDD4

XTAL15

XTAL26

AGND7

RESETB 8

PCLK 9

IO_DVDD 10

YOUT7 11

YOUT6 12

YOUT5 13

YOUT4 14

YOUT3 15

YOUT216

YOUT1 17

YOUT0 18

DGND 19DVDD 20

SCL 21

SDA 22

FID/GCLO 23

VSYNC/PALI 24

HSYNC 25

AVID26

INT 27

PDN 28

REFP29

REFM30

CH_AGND31CH_AVDD32

U18

TVP5150A

VDATA0VDATA1VDATA2VDATA3VDATA4VDATA5VDATA6VDATA7

VDATA[0..9]

PCLKVSYNCHSYNC

AVIDnPDN

FID/GLCO

nINTnRESET

SCLSDA VCC_IO

GND

GND

GND

GND

C70 1u

C711u

C721u

GND

Y414.31818MHz

GND

C67 33p

C69 33p

GND

GND

R5110k

VCC_IO Selects I2C address of 0xBA

C75100n

C76100n

GND

VCC_IO

5

41

3

62

U15OPA358

A1V8

A1V8 C7322u, 6.3V

L5 1u

GND

VCC_IOA3V3

A3V3

R5239R

R5339R

nPDN

GND

C66 100n

GND

Low pass filter here?

R501k

R49 1k

GND

R48 75R

Many circuits have a 220uF cap in here.

C68100n

GND

C77100n

C78100n

GND

A1V8

D1S12

GND 3

VDD 4

IN6

S28

U14

ADG719BRM

BLANK_IN

A3V3

GND

BLANK

A3V3

C59100n

GND

OUT_ENABLE

PCLK

D1

CLK2

GND 3Q4VCC 5

U13

SN74AUP1G80

Divide Pixel Clock by Two

VCC_IO

GND

VCC_IO

C58100n

GND

PCLK

PCLK_DIV2

Analogue switch between blank and inputBuffering and amplification

Power supply filtering

Video decode

Overlay generation

12

J12

CON2

12

J11

CON2

GND

GND

Video In

Video Out

VDATA[0..9]

VOUT5 VIN

1V

SS2

U16XC6201

3V3

GND

C621uF

GND

C611uF

GND

1.8V Generation

D1V8

D1V8

D1V

8

VOUT5 VIN

1V

SS2

U17XC6201

3V3

GND

C651uF

GND

C641uF

GND

A1V8

ALT_VIDEO_OUT

12

J22

CON2 GND

12

J21

CON2GND

R105 47R

A1

B2

GND 3Y4VCC 5

U5

NC7SZ08

VCC_IO

GND

AVID

AVID

Gate with active video

R7610k

GND


1

1

2

2

3

3

4

4

D D

C C

B B

A A

9


Power supplies

912/09/2006 11:34:39 PMZ:\projects\ibox\design\Power.SCHDOC

Title

Size: Number:

Date:File:

Revision:

Sheet ofTime:

A4

C36

1uF

R37 10R

GND

VIN

C40

10uF,10V

C39

10uF, 10V

C38

10uF, 10V

DEFDCDC31

VDCDC3 2

PGND33

L34

VINDCDC35

VINDCDC16

L1 7

PGND18

VDCDC1 9

DEFDCDC110

HOT_RESET11

DEFLDO112

DEFLDO213

VSYSIN 14

VBACKUP 15

VRTC 16

AGND217

VLDO218

VINLDO19

VLDO1 20

LOWBAT21

LDO_EN 22

DCDC3_EN 23

DCDC2_EN 24

DCDC1_EN 25

TRESPWRON26 RESPWRON27

INT28 SDAT29SCLK30

PWRFAIL31

DEFDCDC232

VDCDC2 33PGND234 L2 35

VINDCDC236

VCC37

PWRFAIL_SNS 38

LOWBAT_SNS 39

AGND140 POWERPAD0

U9

TPS65021

GND

2V5

VIN

VIN

VIN

SCLKSDAT

3V3_ENABLE

2V5_ENABLE

VCORE_ENABLE

L1 3.3uH

L2 3.3uH

L3 3.3uHVCC_CORE

2V5

3V3 VCC_MEM VCC_IO

C37 22u, 6.3V

GND

C41 22u, 6.3V

GND

C42 22u, 6.3V

GND

LDO_EN

C464.7uF

VCC_BATT

GND

3V3

C432.2uF

GND

C442.2uF

GND

GND

VCC_SRAM VCC_PLL

R4010k

VCC_BATT

INT

nRESET

C45 1nFGNDR3810k

R3910k

nBATTFLTnVDDFLT

R4210k

S1SW-PB

VCC_BATT

GND

BT1Battery

VIN

R41100k

R43100k

R44100k

GND

VIN

GND

C1002.2uF

GND


1

1

2

2

3

3

4

4

D D

C C

B B

A A

10


Power input and conditioning

1012/09/2006 11:34:46 PMZ:\projects\ibox\design\Power_in.SCHDOC

Title

Size: Number:

Date:File:

Revision:

Sheet ofTime:

A4

A1 C

2

K3

C4

D3Bridge1

GND

POWER IN #1

POWER IN RETURN

C48

470u

F, 5

0V C49

470u

F, 5

0V C50

470u

F, 5

0V

GND GND GND

F1

FUSE D5

33V

Tra

nsie

nt S

uppr

esso

r, S

MA

J33A

GND

Bridge Rectifier Protection Bulk Capacitance

GND1

SW 2

NC3

VIN4

NC5

BOOST6

NC7

GND8

GND9

BIAS10

VC 11

FB/SENSE 12

NC13

SYNC14 SHDN15

GND16

GND0

U10

LT1956-5

C53

2.2u

F, 5

0V

GND

GND

R454k7

C5422uF Ceramic

C55220pF

C564700pF

GND

C47100n

L4

15uH

D4MMSD914TI

D610MQ060N

GND

VOUT

GND

Buck Regulator

12

J7

CON2

1

23

J8

DCSOCKET

~3V ripple worst case, populate or not depending on requirements

C51

470u

F, 5

0V

GND



LAYOUT

Layout technology and terminology:

➜ design a printed circuit board (PCB)

➜ layers of fibreglass and copper

➜ the iBox uses an 8 layer board (8 copper layers)

➜ vias are holes used to connect between layers



LAYOUT

Component footprints:

➜ through-hole

➜ surface-mount



LAYOUT



LAYOUT

Trade-offs:

➜ number of layers vs. size

➜ component size vs. manufacturability

➜ component size vs. signal integrity



LAYOUT

Routing:

➜ the physical pins are connected with traces of copper

➜ the design software only allows connections defined by the

schematic

➜ design rules are defined to ensure manufacturability

➜ the artwork is used by a manufacturer to build a PCB



LAYOUT

Things to think about:

➜ Auto-routing vs. manual routing

➜ boxes and enclosures

➜ connector locations

➜ pin assignment

➜ size of the traces

➜ isolating noise

➜ signal integrity

➜ simulation



LAYOUT

Signal integrity: Digital systems are still analogue!

➜ Above 100MHz, edges on digital signals tend to have

high-frequency components

➜ transmission line effects

➜ inductance and capacitance in the traces/packages

➜ noise, cross-talk, EMI problems

So:

➜ keep stub lengths short

➜ use termination

➜ think about return paths

➜ use simulation



LAYOUT



LAYOUT

iBox layout:

➜ 624MHz PXA270 is a uBGA — 0.5mm between balls

➜ We need very small vias — laser drilling

➜ We need buried and blind vias



LAYOUT



MANUFACTURE

Surface-mount:

➜ Solder stencil

➜ Pick and place

➜ Reflow

Through-hole:

➜ wave soldering



BRING-UP

JTAG: Joint Test Action Group – a standard for board testing

➜ boundary scan

➜ debugging

➜ custom commands

JTAG can be daisy-chained – multiple chips on one port



BRING-UP

PCB Testing:

➜ PCBs are tested using a “bed of nails”

➜ this doesn’t work with BGA and PGA packages

➜ JTAG defines boundary scan: the device pins can be controlled

➜ can be used in combination with “bed of nails”



BRING-UP

IC LOGIC

Instruction

TCK TMSControl

TDI TDOBypass



BRING-UP

iBox JTAG:

➜ Boundary scan lets us control all of the pins on the PXA270

➜ so we can manually control the bus

➜ so we can program the flash memory



BRING-UP

Debug:

➜ some processors have extra, debugging JTAG instructions

➜ Xscale cores can execute instructions from a mini-instruction

cache

➜ breakpoints

➜ single step

➜ watch variables

Trace:

➜ a trace port exports which instructions are run

➜ analysis tools can step backward



BRING-UP

Bootloader:

To load software, you need software?

➜ prepares the system for boot

➜ handles device-specific tasks

➜ loads and jumps to the operating system

➜ commonly saved in read-only memory as firmware

➜ can be very simple or complex

➜ some systems use multi-stage loaders

The iBox uses U-Boot, the NSLU2 uses Redboot



BRING-UP

Start up on the PXA270:

➀ start executing at 0x00000000 (Flash, on iBox)

➁ configure the GPIO pins

➂ initialise the static memory and SDRAM

➃ initialise the IRQs

➄ set the core clock frequency

➅ enable the caches

➆ copy into RAM

➇ set up a stack

➈ read configuration

➉ set up devices and other services



BRING-UP

Porting an OS to the new platform:

➜ configure for PXA270

➜ configure specific devices (network, CF, USB, etc)



BRING-UP

Bringing up the iBox:

➜ Power supplies

➜ Soldering the PXA270

➜ Testing using JTAG

➜ Flash

➜ SDRAM

➜ Bootloader

➜ Ethernet

➜ The rest



DEMO

DEMO

SEPTEMBER 15, 2006 DEMO 49


POWER MANAGEMENT

POWER MANAGEMENT

aka: doing more with less

SEPTEMBER 15, 2006 POWER MANAGEMENT 50


POWER MANAGEMENT

Overview:

➀ Why?

➁ Concepts

➂ OS directed power management

➃ Evaluation techniques

➄ Energy accounting



POWER MANAGEMENT

Why do we care about power?

➜ Thermal management

➜ Electricity consumption

➜ Energy limited devices

Power-conscious systems can use energy more effectively.



POWER MANAGEMENT



➀ Enclosure size and noise

➁ Performance




SEPTEMBER 15, 2006 POWER MANAGEMENT 52-A


POWER MANAGEMENT




➁ Performance


➀ Environment

➁ Cost



SEPTEMBER 15, 2006 POWER MANAGEMENT 52-B


POWER MANAGEMENT




➁ Performance


➀ Environment

➁ Cost


➀ Battery powered

➁ Solar powered


SEPTEMBER 15, 2006 POWER MANAGEMENT 52-C


CAUSES OF ENERGY USE

Where does the energy go?:

➜ switching circuits

➜ peripherals

➜ voltage conversion

➜ batteries




Switching circuits:

➜ short circuit power

➜ gate capacitance

➜ leakage




Gate capacitance:

➜ to turn on a transistor, we charge the gate beyond its threshold

voltage

➜ to turn it off, we discharge it

➜ the charge disappears and is the main source of power

consumed

➜ the charge transferred is: q = Cv

➜ the energy transferred is: E =1

2Cv2




Hardware techniques:

➜ clock gating




Software energy consumption:

➜ more instructions = more energy

➜ different instructions use different energy

➜ different data use different energy

“Source Code Optimisation and Profiling of Energy

Consumption in Embedded Systems”: Simunic, et al, 2000.



DYNAMIC VOLTAGE SCALING

Dynamic frequency scaling:

➜ reduce the system frequency to reduce the power

➜ each switch we lose E =1

2Cv2

➜ C comes from the gate and interconnect capacitance

➜ frequency is the rate at which we switch

➜ conclusion: power scales linearly with frequency




Dynamic frequency scaling:

➜ reduce the system frequency to reduce the power

➜ each switch we lose E =1

2Cv2

➜ C comes from the gate and interconnect capacitance

➜ frequency is the rate at which we switch

➜ conclusion: power scales linearly with frequency

The energy required to complete a given amount of work is

unchanged




Dynamic voltage scaling:

➜ if we reduce the frequency, the transistors don’t have to switch

as fast

➜ transistor speed is dependent on the driven voltage

➜ if we reduce the frequency, we can reduce the voltage

➜ given E =1

2Cv2, we get quadratic energy savings




Voltage/frequency switching overheads:

➜ frequency generation is usually via a crystal and PLL

➜ clock multipliers control the PLL

➜ clock dividers generate lower frequencies

➜ the PLL has to settle following a change

➜ on the PXA255 (XScale) this is ≈ 500µs

➜ or, always run the PLL at full speed and change dividers

➜ on the PXA255 this takes 20 cycles.




Scheduling for Reduced CPU Energy: Weiser, et al, 1994.

➜ assumption: idleness is bad

➜ eliminate idleness using DVS

• if idle time is large, decrease speed

• if idle time is small, increase speed

• adjust the speed periodically

Other algorithms:

➜ lots of ways of predicting idleness




Balancing Batteries, Power and Performance:

System Issues in CPU Speed-Setting for Mobile

Computing: Thomas Martin, 2001

Peukert:

Q =k

Iα

➜ battery capacity is related to rate of discharge

➜ steady discharge may increase the battery life

➜ can DVS be used to attain this?




QoS issues:

➜ reducing frequency reduces performance

➜ missed deadlines

➜ reduced QoS

➜ real-time techniques may be employed




QoS issues:

➜ reducing frequency reduces performance

➜ missed deadlines

➜ reduced QoS

➜ real-time techniques may be employed

every man and his dog has an RT DVS technique




Trouble in wonderland:

➜ ignoring leakage, transistors only use power when they switch

➜ not every part of the circuit switches on every clock cycle

➜ different sections run at different frequencies

➜ off-chip devices aren’t aren’t affected




Trouble in wonderland:

➜ ignoring leakage, transistors only use power when they switch

➜ not every part of the circuit switches on every clock cycle

➜ different sections run at different frequencies

➜ off-chip devices aren’t aren’t affected

Also:

➜ We can’t ignore leakage!

The simple models only work in special cases



DVS: MYTHS AND FACTS

“Power Management and Dynamic Voltage Scaling:

Myths and Facts”: Snowdon, et al, 2005.

➜ most academic research uses simulation for evaluation

➜ the naive models lead to incorrect results.








So:

➜ we take real measurements of a real system

➜ we run an appropriate benchmark suite (MiBench)








So:

➜ we take real measurements of a real system

➜ we run an appropriate benchmark suite (MiBench)

Results:

➜ real measurements differ dramatically from models

➜ optimum processor setting is dependent on workload

SEPTEMBER 15, 2006 POWER MANAGEMENT 66-B



The naive model:

➜ P ∝ fv2

Limitations:

➜ ignores “static” power (core-frequency independent)

➜ ignores external components

• affects computation time

• energy consumption scales differently to the CPU




Experimental setup:

➜ single board computer – PLEB 2

➜ instrumented power supplies

Valid configurations:

Vcore (V) fcpu (MHz) finternalbus (MHz) fmem (MHz)

1.0 100 50 100

1.0 200 100 100

1.1 300 100 100

1.3 400 100 100

1.3 400 200 100




Execution time for CPU bound:

4

6

8

10

12

14

16

18

20

22

24

50 100 150 200 250 300 350 400 450 500

Tot

al E

xecu

tion

Tim

e (s

)

Turbo Frequency (MHz)

Execution time vs. Frequency for cpubound

"cpubound.dat" index 0:7 using 1:2"cpubound.dat" index 8 using 1:2




Execution time for Memory bound:

120

140

160

180

200

220

240

260

280

300

50 100 150 200 250 300 350 400 450 500

Tot

al E

xecu

tion

Tim

e (s

)


Execution time vs. Frequency for membound

"membound.dat" index 0:7 using 1:2"membound.dat" index 8 using 1:2




Number of cycles for CPU bound:

0.8

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

50 100 150 200 250 300 350 400 450 500

Nor

mal

ised

cyc

les


Normalised cycles vs. Turbo Frequency for cpubound

"cpubound.dat" index 0:7 using 1:2"cpubound.dat" index 8 using 1:2




Number of cycles for Memory bound:

0.8

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

50 100 150 200 250 300 350 400 450 500

Nor

mal

ised

cyc

les


Normalised cycles vs. Turbo Frequency for membound

"membound.dat" index 0:7 using 1:2"membound.dat" index 8 using 1:2




CPU energy:

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

CP

U E

ne

rgy

Configurations

Vcorefcpufint bus

1.010050

1.0200100

1.1300100

1.3400100

1.3400200

Model predicted energyCpu-intensive

Memory-intensive




Memory energy:

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Me

mo

ry E

ne

rgy

Configurations

Vcorefcpufint bus

1.010050

1.0200100

1.1300100

1.3400100

1.3400200

Cpu-intensiveMemory-intensive




Total energy:

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

No

rma

lize

d T

ota

l E

ne

rgy

Configurations

Vcorefcpufint bus

1.010050

1.0200100

1.1300100

1.3400100

1.3400200

Model predicted energyCpu-intensive

Memory-intensive




Padded with low-power mode power:

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

1

To

tal

En

erg

y

Configurations

Vcorefcpufint bus

1.010050

1.0200100

1.1300100

1.3400100

1.3400200

Cpu-intensiveMemory-intensive




Conclusions:

➜ the memory/cpu frequency ratio affects the number of cycles

➜ the most effective DVS policy depends on usage

➜ the lowest-energy setting depends on the workload

➜ increasing frequency doesn’t improve membound performance

➜ idling in a low-power mode may be better than running at a low

frequency




“Process cruise control: event-driven clock

scaling for dynamic power management”: Weissel and

Bellosa, 2002.

➀ maintain per-thread CPU performance counters

➁ use cache miss and instruction counters

➂ use a lookup table to select a frequency

➃ construct the table for ¡ 10% performance hit

Demonstrated energy savings of up to 37% with a 10%

slowdown for gzip




“Process cruise control: event-driven clock

scaling for dynamic power management”: Weissel and

Bellosa, 2002.

➀ maintain per-thread CPU performance counters

➁ use cache miss and instruction counters

➂ use a lookup table to select a frequency

➃ construct the table for ¡ 10% performance hit

Demonstrated energy savings of up to 37% with a 10%

slowdown for gzip

How would this affect a µK based system?



SLEEP MODES

Sleep modes:

➜ processors and devices have low-power modes

➜ these modes switch off parts of the processor

➜ some state or functionality will be lost

➜ lower-power modes tend to lose more functionality

➜ lower-power modes take longer to enter and exit



SLEEP MODES

Sleep modes:

➜ processors and devices have low-power modes

➜ these modes switch off parts of the processor

➜ some state or functionality will be lost

➜ lower-power modes tend to lose more functionality

➜ lower-power modes take longer to enter and exit

How do we choose when to sleep?

➜ processor(s)

➜ devices



SLEEP MODES

Case study: PXA255

Power

200MHz Run/Turbo 178mW

200MHz Idle 63mW

33MHz Idle 45mW

Sleep 0.175mW



SLEEP MODES

Case study: Hard disk

Sleep delay Wake delay Power

Idle 0 0 657mW

Standby 0.85s 1.03s 235mW



SLEEP MODES

Transition management:

➜ some energy is saved while “asleep”

➜ some energy is wasted while transitioning

➜ introduced delay reduces quality-of-service

We need to predict the future



SLEEP MODES

“Idleness is not sloth”: Golding, et al, 1995.

➜ an “idleness detector” should predict the start time and duration

of an idle period

Idle start:

➜ timeout based: (static, variable, adaptive)

➜ rate-based: (static, adaptive thresholds)

➜ periodic: (maintain a DPLL)



SLEEP MODES

“Idleness is not sloth”: Golding, et al, 1995.

➜ an “idleness detector” should predict the start time and duration

of an idle period

Idle start:

➜ timeout based: (static, variable, adaptive)

➜ rate-based: (static, adaptive thresholds)

➜ periodic: (maintain a DPLL)

Idle duration:

➜ static (infinite, none, fixed)

➜ moving average (filtered, unfiltered)

➜ backoff (geometric increase, arithmetic decrease)

➜ periodic



SLEEP MODES

OS support:

➜ Cooperative IO (Weissel, et al)

➜ Ghosts in the machine (Anand, et al)

➜ Power-aware page allocation (Lebeck, et al)

➜ Timer ticks (IBM Watch project)

Other possible power down areas:

➜ LCD backlight (user context sensing, selective lighting)

➜ wireless network

➜ sound card



SLEEP MODES

Conclusions:

➜ keep it simple - DTT with break-even time does OK.

➜ adaptive techniques can save power

➜ operating system co-operation improves

➜ Douglis et al present potential reductions of 60% beyond a 5s

timeout



ADAPTATION

Adaptation:

➜ applications can sometimes adjust their computation best

• MPEG/JPEG

• audio bitrate

• game FPS

• distributed process migration

• map viewer detail (Flinn)

➜ applications can scale their QoS to meet a goal

• a given battery lifetime

• a given CPU temperature

➜ requires operating system feedback



EVALUATION TECHNIQUES

Evaluation techniques:

➜ Simulation

➜ State-based accounting

➜ Indirect measurement

➜ Real measurement




➜ Simulation

X necessary information may not be available

X non-trivial to build

X usually limited to CPU/memory.

X computing power vs. detail

X difficult to interface

➜ State-based accounting

X assumes a constant power in each state

➜ Indirect measurements

X only really applies to the CPU and memory (at the moment)

X Insufficient performance counters for energy-related events

➜ Real power measurements

X may measure background activity incorrectly

X overhead vs. resolution

X cumbersome difficult to obtain setup




Powerscope (Energy profiling):

➜ Flinn, 99

➜ designed to be similar to performance profile

➜ A host computer monitors a computer being profiled

➜ a computer-controlled multimeter samples the actual energy

used

➜ the profiled computer records PIDs and PC for each sample

➜ post-processing attributes energy to procedures/processes



ENERGY ACCOUNTING

Energy accounting:

➜ ECOSystem (Zeng, et al, 2001)

• currentcy is used as a primitive for energy allocation

• currentcy is only valid for a certain time

• resource containers are used for resource charging

• model-based techniques are used to charge RCs.

• internal policy is used to select resource containers

➜ LEA

• charges using real power measurements



ENERGY ACCOUNTING

Energy accounting:

➜ ECOSystem (Zeng, et al, 2001)

• currentcy is used as a primitive for energy allocation

• currentcy is only valid for a certain time

• resource containers are used for resource charging

• model-based techniques are used to charge RCs.

• internal policy is used to select resource containers

➜ LEA

• charges using real power measurements

Energy Budgeting:

➜ a budget is allocated to each resource container

➜ resource containers in debt are not scheduled

➜ the budget is periodically refreshed



ENERGY ACCOUNTING

‘‘Event-Driven Energy Accounting for Dynamic

Thermal Management’’: Bellosa, et al, 2003

➜ use CPU performance counters to estimate CPU temp

➜ account the energy contribution of each RC

➜ schedule ”hot” processes interspersed with ”cold” processes

➜ can maintain a given temperature limit


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