Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124-3450Phone: 408-559-7778FAX: 408-879-4780©2000 Xilinx Inc.All rights reserved.

Xcell is published quarterly. XILINX, theXilinx logo, and CoolRunner are registeredtrademarks of Xilinx, Inc. Virtex,LogiCORE, Spartan, SpartanXL, AllianceSeries, Foundation Series, CORE Generator,Checkpoint Verification, TimeSpecs, SmartIP, QPRO, SelectI /O, SelectI/O+, True Dual-Port, WebFITTER, WebPACK, Select RAM,BlockRam, Xilinx Online, and all XC-prefixproducts are trademarks, and TheProgrammable Logic Company is a servicemark of Xilinx, Inc. Other brand or productnames are trademarks or registered trade-marks of their respective owners.

The articles, information, and other materi-als included in this issue are providedsolely for the convenience of our readers.Xilinx makes no warranties, express,implied, statutory, or otherwise, andaccepts no liability with respect to anysuch articles, information, or other materi-als or their use, and any use thereof issolely at the risk of the user. Any personor entity using such information in anyway releases and waives any claim itmight have against Xilinx for any loss,damage, or expense caused thereby.

Within the next five years, pro-grammable logic will be thekey technology for develop-

ing next generation products; within thenext ten years, programmable logicdevices (PLDs) will be used in virtuallyevery electronic product on the market.These industry predictions are based ona number of recent developments thathave forever changed the way electronicsystems are designed.

The old advantages of custom ASICsare quickly being overcome by the newadvantages of programmable logic. Hereare some of the reasons why:

Very High Density, System-levelDevices - We now produce high perfor-mance FPGAs with advanced featuresand up to 3.2 million system gates. Plus,we have just announced our next gener-ation 10-million gate architecture. Withdevices this powerful and this dense youare limited only by your imagination.

Very Low Power, Low-costDevices - Many new designs requirebattery operation and low cost. Our FastZero Power™ CPLDs are perfect for cellphones, PDAs and other power sensitiveapplications. Our Spartan FPGAs alreadygive you 100K gates for less than$10.00, and higher density, lower costFPGAs are on the way. Power and priceare no longer an issue with PLDs.

Intellectual Property - The fastestand surest way to get your PLD-basedproduct to market is to use proven

designs, either those created in-house orby third party suppliers. There is alreadya wealth of IP, and many new designsare being introduced every day. IP signif-icantly reduces your development timeand your risk.

Highly Efficient DevelopmentTools - Speed is critical. Not only doyou want the fastest design you can cre-ate, but you want to complete thatdesign with the least possible risk andeffort. The currently available develop-ment tools from Xilinx allow you toquickly develop your designs in manydifferent ways, with multiple developerslocated in different places. These toolsare fast, efficient, and easy to use; andthey are constantly improving.

Field Upgradeability - With thecurrent Xilinx device and software tech-nologies you can create designs that areeasily changed, in the field, over anynetwork, right at your customers’premises. The possibilities are enor-mous, and the advantages are over-whelming; this cannot be duplicatedwith any other technology. Now, just likesoftware, your hardware can easilychange to meet the demands of themarketplace.

With programmable logic you notonly get the fastest and easiest way tocreate next-generation systems, youalso get significant advantages that can-not be offered by fixed logic ASICs; thereis no better way to create value.

2

EDITOR

Carlis Collinseditor@xilinx.com408-879-4519

SENIOR DESIGNER

Jack Farage

BOARD OF ADVISORS

Dave StiegAndy LargMike Seither

Pronto Creativewww.prontocreative.com

The Future of Logic Design...

3

COOLRUNNERCOOLRUNNER 12

View from the TopThe Promise of Field UpgradableSystems . . . . . . . . . . . . . . . . . . . . .4

Cover StoryCreating Field Upgradable Hardware Systems . . . . . . . . . . . . . .5

CoolRunner CPLDsFast Zero Power (FZP)Technology .10

XPLA3 Development Kit . . . . . . . . .12

Implementing a 16B/20B Encoder/Decoder in a CoolRunner CPLD . . .14

VirtexNew Virtex-EM FPGAs Over 1 Mbits of RAM . . . . . . . . . . . . . . .15

SoftwareXilinx Development Systems . . . . .16

On-chip, Real-time Logic Analysis .19

JTAG Programmer . . . . . . . . . . . . .22

Architecural Synthesis from Behavioral C Code . . . . . . . . . . . . .23

CoresData Encryption Cores . . . . . . . . . .26

Image Compression Cores . . . . . . .28

Using an 8051 Core and QPRO . . .30

Support ProductsA High Speed Platform for Dynami-cally Reconfigurable Logic . . . . . . .33

New PCI 64/66 Design Kit . . . . . . .34

Mass Storage for Xilinx FPGA . . . .37

ApplicationsUsing the Virtex Look Up Tables . . .40

Efficient Debugging Using PROBE .44

Control Virtex Design Optimzation 47

Success StoriesA New Internet Protocol Service Switch Uses FPGAs . . . . . . . . . . . .49

FPGAs for a Reconfigurable ImageProcessing Module . . . . . . . . . . . .51

Columns/ReferenceElectronic Distribution . . . . . . . . .54

Trade Shows . . . . . . . . . . . . . . . .55

Customer Education . . . . . . . . . . .56

Virtex Reference Guide . . . . . . . . .57

Spartan Reference Guide . . . . . . .58

CPLD Reference Guide . . . . . . . . .59

QPRO Reference Guide . . . . . . . .60

PROM Reference Guide . . . . . . . .61

Configuration Solutions . . . . . . . .62

Inside This Issue:

The CoolRunner XPLA3 Development Kitis the perfect way to get started usingthe most efficient, low power CPLD onthe market.

57

For A FREESubscriptionTo The Xcell

Journal

1. Your full name and mailing address

2. Your title

3. The name of your company

4. Your e-mail address

5. Is this new subscriptionor a subscription renewal?

E-mail your request to: literature@xilinx.com,please be sure to include:

REFERENCEREFERENCEAvailability guides for Virtex FPGAs,Spartan FPGAs, XC9500 and CoolRunnerCPLDs, QPRO FPGAs, PROMs, andConfiguration Solutions.

34SUPPORT PRODUCTSSUPPORT PRODUCTSNew PCI Development Kit includes a pro-totyping board, driver development tools,and reference designs.

www.xilinx.com

5COCOVER STVER STORORYYGoAhead Software—A complete systemfor managing and remotely upgradingyour FPGA designs in the field.

16SOFTWSOFTWAREAREXilinx Software R&D delivers new version3.1i software tools that empower you tomaximize your productivity, while lever-aging your creativity.

JTAGConnection

One of the most exciting devel-

opments in our industry is the

increasing shift toward using

networks, including the Internet, to

remotely upgrade the digital equipment

that is already installed at a customer’s

location, anywhere in the world, and beyond.

Updating software remotely, with new enhance-

ments and bug fixes, is a common practice. However,

remotely updating hardware may appear to be more

challenging because hardware is typically a fixed

entity that is updated by manually replacing circuit

boards. Now, with our current FPGA families and the

Xilinx Online software technologies, doing automatic,

remote hardware upgrades is not only a reality, it is

becoming a necessity in many new applications.

Researchers have been investigating this concept

for years, and a few forward looking companies have

already deployed FPGA-based remotely reconfigurable

products. IBM, for example, currently markets an ATM

switch whose FPGA-based logic can be changed over

the network to bring it into accord with the latest

changes in the ATM standard. A number of Xilinx cus-

tomers, including large communications companies

building the next generation of WCDMA wireless sys-

tems, are very interested in the idea, and a few are

well along the way with major designs efforts.

The advantages of this new possibility are enor-

mous. For example, the ability to remotely update

hardware with new features or the latest bug fix can

accelerate your time-to-market, extend the useful life

of existing systems, and significantly cut production,

maintenance, and support costs. Many of today’s sys-

tems already come with some form of built-in com-

munications or microprocessor interface, making the

addition of remote field update capability a simple

matter. If you consider doing remote updates during

the initial specification and design process, your sys-

tems can easily reap all the benefits of being updated

remotely.

Remote upgradability significantly increases the

useful lifetime of a system. The ability to add new

hardware features and fix existing ones without send-

ing a technician out to the field can add up to consid-

erable maintenance and support savings over the

entire life of the system. Imagine the implications for

satellite-based communications equipment.

Remotely upgradeable systems can also provide

new revenue prospects. After the initial product is

released, you can develop new hardware features

then sell and distribute those features to existing cus-

tomers just as software developers do today. Or a

standard “off-the-shelf” application can be developed

so features can be swapped in and out depending on

what the end-user purchases or needs.

Any system that has some type of connectivity to

the “outside world” could potentially benefit from

being designed to support field updates. Typical prod-

ucts include network appliances, set-top boxes, secu-

rity systems, network equipment, cellular base sta-

tions, and satellite communications systems. Other

likely applications are HDTV, video and image pro-

cessing, encryption, military communications, surveil-

lance, radar, and sonar.

Clearly, electronic equipment manufacturers who

begin to think about the benefits of remote hardware

upgrades today will be the ones who lead their mar-

kets in the not-to-distant future.

4

View from the Top

by Wim Roelandts, President and CEO, Xilinx

The Promise of

Field Upgradable Systems

For many years designers have been usingXilinx programmable logic devices (PLDs)to reap the benefits of fast time-to-market.

Now, a second major advantage is made possi-ble through the partnership of GoAheadSoftware and Xilinx—the ability to upgrade yourdesigns via a network after they have beendeployed in the field. This can result in dramaticfield service cost savings and it helps “future-proof” your product.

The Solution for Field Upgrading

The new Xilinx and GoAhead Software solutioncombines the GoAhead commercial software(GoAhead FieldUpgrader™) with the XilinxInternet Reconfigurable Logic methodology(IRL™) to provide the enabling technology tohelp you create and manage field upgradablesystems. This technology provides the backbonefor network-based system designs as well as thedelivery mechanisms to successfully deployupgradable products.

GoAhead FieldUpgrader

The GoAhead FieldUpgrader software consists ofthree parts:

• GoAhead DeviceStudio™ - a developmentenvironment used to create the UpgradeAgentsoftware.

• GoAhead UpgradeAgent™ - the softwarethat is embedded in the target device. Eachagent is unique to the particular operatingsystem that is resident on the target system.The target system containing theUpgradeAgent polls the UpgradeServer at reg-ular pre-determined intervals to look forFPGA upgrades. When an upgrade is avail-able, the device downloads the upgrade to apredetermined storage location. This processis illustrated in Figure 1.

• GoAhead UpgradeServer™ - used to createand publish upgrades and is usually locatedon a server at the manufacturer’s site. Whenthe need for an FPGA upgrade arises, themanufacturer publishes the upgrade withUpgradeServer.

5

Cover Story

Hardware Systems UsingEnabling Technology from

GoAhead

A complete system for managing andremotely upgrading your FPGAdesigns in the field.

by Greg Brown, Xilinx Software Product Manager for Internet Applications, greg.brown@xilinx.comand by Mike Akers, GoAhead Software FieldUpgrader Product Manager, mikea@goahead.com

FIELD UPGRADABLECreating

Software

Data Security and Integrity

To upgrade devices over a network, it is criticalthat the devices only accept upgrades from theauthorized, designated server. It is also impor-tant to ensure that the upgrade payload is notmodified or corrupted. GoAhead FieldUpgraderand the UpgradeServer use a variety of tech-niques to authenticate the upgrade and preventmodifications along the way.

GoAhead FieldUpgrader uses the DigitalSignature Standard (DSS), which specifies aDigital Signature Algorithm (DSA). The DSA pro-vides the capability to generate and verify signa-tures using public and private keys. In addition,the device-initiated approach provides built-insecurity; the device does not accept externallyinitiated upgrades. The location and port of theupgrade server is configured into the targetdevice and the device will only allow upgradesfrom this designated upgrade server. Thismethod ensures that the upgrade payloadreceived at the target device matches the origi-nal upgrade payload published at the upgradeserver and guarantees that the message was notmodified en-route to the device.

The payload of the upgrade is broken intosmaller chunks to make the transfer more effi-cient and re-startable. GoAhead FieldUpgradercalculates a 32-bit CRC checksum for each ofthese individual chunks. If the target device

detects a checksum error, it discards that chunkand re-fetches it from the upgrade server. Onceall of the chunks have been downloaded, thedevice reconstructs the payload and performsthe higher-level data integrity check.

Data integrity is also checked during theactual programming of the Xilinx FPGAs; there isa CRC checksum built into the programmingstep.

Fault Tolerance

The UpgradeAgent is fault tolerant during thetransmission of the upgrade. The Agent knowsthe contents of the payload based on the mani-fest list and will re-initiate the upgrade to fetchany missing chunks if the connection with theserver is lost.

The application of the upgrade to the Xilinxdevice can also be made fault tolerant in the sys-tem architecture, which is shown in Figure 4.The concept uses redundant non-volatile storageareas—one to hold the current, known good sys-tem, and the other to hold the upgrade. The sys-tem can always fall back to the known goodconfiguration if there are any issues associatedwith upgrading the system.

Flexibility By Design - Pull or Push?

There are some applications that may require a“push” method of upgrading. The term “push”

6

Device Manufacturer

Device initiated request

Upgrade request response

Request for payload

Payload

Response

Figure 1 - The remote upgrade process.

entails the directing and initializing of upgradesfrom a central server. There are cases or man-agement decisions that may dictate this alterna-tive to providing upgrades.

The FieldUpgrader software primarily uses adevice-initiated or “pull” methodology. However,it was developed to be flexible as well, and canbe enhanced to allow a “push” methodology. Ata pre-determined time, the UpgradeAgent maysimply open a communications port to listen for“hello” messages that are broadcasted or multi-casted from the UpgradeServer. If theUpgradeAgent responds after verification, theUpgradeServer sends a request packet to thesystem to begin the upgrade process. TheUpgradeAgent then makes the request for anupgrade from the secure UpgradeServer. Thismethodology solves the problems associatedwith firewalls and security. The requests maypass through firewalls and the device portremains open for only the specified upgradeperiod.

System Support

GoAhead FieldUpgrader supports the followingplatforms:

• GoAhead UpgradeServer, GoAheadDeviceStudio:

Windows NT4.0, Linux 2.2, MicrosoftInternet Explorer 4.x or greater, Netscape4.x or greater

• GoAhead UpgradeAgent:

Wind River VxWorks 5.3.1 or greater (x86,PowerPC, ARM, MIPS), Windows 95/98/NT(x86, PowerPC), Windows CE (x86, HitachiSH) or Linux 2.2 (x86)

The key requirements of the UpgradeAgentare:

• TCP/IP stack and connection.

• Real-time clock.

• File system (optional for VxWorks).

• Provision of the main software module’s Csource code (main.c) and a linkable library toenable the integration of the UpgradeAgentinto custom applications.

• Support for embedded JavaScript calls withthe ability to:

- Control the upgrade process

- Load and call C functions to extend func-tionality

- Send additional request data to GoAheadUpgradeServer

- Access GoAhead UpgradeAgent environ-ment variables

Demonstration Design

The demonstration design utilizes the GoAheadFieldUpgrader to upgrade a Xilinx XCS05 SpartanFPGA, which is connected to a popular embed-ded system—a single-board computer runningWind River’s VxWorks® real-time operating sys-tem. This type of system exists in many applica-tions and environments from industrial controlstations to remote monitoring systems. Figure 2shows a diagram of the system.

7

TCP/IP

Field UpgraderServer System(Windows NT 4.0)

Payload Packageupgrade .js

xiprog.otest.bit

Agent System(VxWorks)Single board

486 ComputerField Upgrader Agent

(includes javascriptinterpreter)

Runs upgrade.jsDynamically loads xiprog.o

into VxWorksPrograms XCS05

with test bit

Monitor

Hard disk

Power Supply

Remote System

ParallelCable

Xilinx Demo Board(Spartan XCS05)

Figure 2 - Demonstration system.

This demonstration system includes the follow-ing components:

Processor - The processor is a single-board,Intel 486-based system. The board has 2MB ofRAM, integrated VGA controller, an IDE con-troller, and a parallel interface. A hard disk isused for non-volatile storage other than theBIOS.

Xilinx demonstration board - This board hastwo devices on it: an XC3020A and a SpartanXS05. The Spartan XS05 is a 5000 system gateFPGA that is used in high volume, low-costapplications.

Xilinx Parallel Cable III - This cable runsbetween the single board computer and theXilinx demonstration board. This cable is used toprovide the communication between the com-puter system and the Xilinx FPGA.

Wind River VxWorks - The VxWorks® Real-Time Operating System (RTOS) from Wind RiverSystems is the most widely used RTOS forembedded systems.

The GoAhead UpgradeAgent - This is a real-time embedded application that uses VxWorks’dynamic loading capability to load and executeother real-time embedded applications. In thedemonstration design, this feature of VxWorks isused to dynamically load the object code thatprograms the Xilinx FPGA. This was strictly anarchitectural choice. An alternative and equallyvalid approach is to have the object code thatprograms the Xilinx device be resident on theVxWorks system and not include it as part of theupgrade process, or use a combination of thetwo approaches.

The UpgradeAgent is configured to poll theUpgradeServer once each minute to check forupgrades. When one exists, it downloads theupgrade payload and executes the instructionsincluded in the payload. For demonstration pur-poses, two payloads are published on the

UpgradeServer: one to upgrade the bitstreamand one to downgrade to the original bitstream.This enables the system to toggle between thetwo FPGA configurations.

UpgradeServer - The UpgradeServer is runningon a laptop PC using Microsoft NT4.0. It waitsuntil the UpgradeAgent on the VxWorks systemcontacts it and requests an upgrade. If there isan available upgrade, the server sends theupgrade payload to the VxWorks system acrossthe TCP/IP network.

Demonstration Upgrade Process

The upgrade process used in the demonstrationdesign is illustrated by the flow diagram inFigure 3.

Building a Commercial System

There are several potential field upgradablearchitectures to which the concepts presentedhere apply. However, only one is describedhere—the single board computer running anRTOS with programmable logic, as shown inFigure 4.

In Figure 4, the processor must be one sup-ported by the GoAhead UpgradeAgent. This can

8

Demonstration System Upgrade Process

Upgrade Agent waitson event schedule

Upgrade Agent buildHTTP request

Upgrade Agent sendsrequest to Upgrade Server

IsUpgradeAvailable

?

IsPolicyValid

?Upgrade ServerOperations

Manifest is sent toUpgrade Agent

No

No

VxWorks programs theXS05 through parallel

port using bit file on disk

Upgrade Agent runsupgrade.js javascript

Upgrade Agent unarchives a payload(Xiprog.o, upgrade.js, test.bit)

Upgrade Agent verifies payload

Upgrade Agent rebuildsarchive file

Upgrade Agent fetchesupgrade chunk to disk

AllChunksreceived

?

IsChunkValid

?

Figure 3 - Demonstration system upgrade process.

be either an Intel X86 (or compatible), PowerPC,ARM, or MIPS processor running VxWorks as theRTOS (or a supported Microsoft Windows orLinux configuration as previously listed).

The non-volatile storage can be divided intothree functions:

• Processor Program Memory (Non-VolatileStorage 1) - contains firmware for the micro-processor.

• FPGA Configuration Storage (Non-VolatileStorage 2) - contains configuration data forthe FPGA. The system can be designed so thatthis storage area contains the initial configu-ration data.

• FPGA Configuration Storage (Non-VolatileStorage 3) - contains configuration data forthe FPGA. The system can be designed so thatthis storage area contains the first upgradeconfiguration data.

The system should be designed to alwayshave a last known-good configuration for theFPGA. This is handled by the redundancy of theNon-Volatile Storage 2 and Non-Volatile Storage3. In a usual sequence of events, the FPGA willbe initially configured from Non-Volatile Storage2. When an upgrade is requested, it is down-loaded into Non-Volatile Storage 3. The FPGA isthen reconfigured from this location. The pro-gram controlling the programming of the FPGAthen switches the functions of these two storageareas as Non-Volatile Storage 3 is now theknown-good configuration and Non-Volatile

Storage 2 is ready to contain the next upgrade.Possible selections for the non-volatile memoryare EEPROMS, FLASH memory cards, or theXilinx XC18V00 in-system programmable config-uration PROMs. (See page 62.)

Software

There are two basic software components thatneed to be written for the target processor archi-tecture:

• Firmware to copy the Xilinx programming fileto non-volatile storage.

• Firmware to program the FPGA.

Another approach is to use the Java pro-gramming language either with the firmware oras a complete application (Xilinx supplies a JavaAPI for the Boundary Scan configuration mode).A Java application can therefore be written (andcalled by the UpgradeAgent) to program theFPGA. On Windows platforms, there are severalJava run-time engines (the virtual machine)available. On a VxWorks platform, the applica-tion would need to be developed using PersonalJWorks™ from Wind River.

Conclusion

The purpose of the GoAhead and Xilinx partner-ship is to provide the enabling technology andsolutions for a variety of field upgradable sys-tems. GoAhead FieldUpgrader provides the man-agement, deployment, communications, andsecurity backbone, while Xilinx provides recon-figurable hardware devices and programmingtechnologies. Together, you have the buildingblocks needed to enable the rapid developmentand deployment of a new generation of cost-saving, life-extending, field-upgradable systems.

9

Basic Architecture

ProcessorI/O

XilinxFPGA/CPLD

Non-VolatileStorage 1

Non-VolatileStorage 1

Non-VolatileStorage 3

Figure 4 - Basic system architecture.

For more information see: www.xilinx.com/xilinxonline/partners/goaheadhome.htm

For more information regarding how the Spartan-II family addresses tradi-tional ASIC and ASSP designs, please see the article on page 49.

0Technology Update - CoolRunner

In traditional CPLD architectures, includingthe XC9500 series, the circuits that propagatelogic-level transitions in the product-term

array are derived from the original (old) bipolarPLD designs. These older designs use senseamplifiers at the end of each bit line in the prod-uct-term array to achieve fast propagationdelays. Because CPLD product terms cannot bedecoded (as with memory locations in anEPROM, for example) there must be a senseamplifier for each individual product-term. Thesesense amplifiers must be continuously opera-tional, and will draw continuous supply currenteven when not switching.

The CoolRunner Design Technique

The Xilinx CoolRunner design uses an innovativemethod for implementing the product-termarray. Rather than employing sense amplifiers (abipolar-style circuit), CoolRunner CPLDs use trueCMOS circuitry. In the CoolRunner Fast ZeroPower (FZPTM ) approach represented in Figure1, the AND gates in the product-term array areimplemented using configurable multiplexers(MUXs) attached to the inputs of normal CMOSNAND gates. Each MUX selects an input, it’scomplement, or Vcc (don’t care state.) These

MUXs are programmed using RAM-based config-uration bits.

The full CMOS AND gate shown in Figure 1has a delay of under 0.5 nsec, including thedelay of the input MUXs.

10

by Ron Cline, Director of CoolRunner Product Development, Xilinx, Inc., ron.cline@xilinx.com

CoolRunner CPLDs require very little power yetoperate at very high speeds—here’s how.

Figure 1 - CoolRunner Fast Zero Power AND gate.

A four input ‘AND’ function demonstrates howthe product term is implemented with full-CMOSgates in the CoolRunner CPLDs.

I 1

I 0

I 3

I 2

Output = I 0 & I 1 & I 2 & I 3

Figure 2 - Representation of a 4-input product-term using the CoolRunner FZP design technique.

How CoolRunner CPLDs Minimize System Current Demand

Fast Zero Power(FZP) Technology

Wider AND gates are built using a deMorgantree, as shown in Figure 2. Doubling the inputwidth simply requires the replacement of theinverter in Figure 1 with a 2-input NOR gate.This increases the total delay by less than 0.1nsec.

This design technique can be extended forwider widths, as shown in Figure 3 which showsa re-doubling to eight inputs, at an additionaldelay penalty of less than 0.2 nsec for the NANDgate plus inverter. The inverter can be replacedwith a two-input NOR gate to enable a product-term width of 16 inputs (at an incremental delaypenalty of 0.1 nsec.).

As you can see, the delay penalty per addi-tional input actually decreases as the number ofinputs into each product-term increases. This isin contrast to the traditional sense amplifierapproach, where the delay increases linearly asproduct-term input width is increased.

The gate tree implementation distributes thecapacitance at each product-term, so this capac-itance is no longer lumped on a single node.Furthermore, the switching current behaves in amanner similar to that of random logic in a gatearray; the static current for each gate is small-

about 1 picoamp (pA). The total instantaneousdynamic current is also small, because only thegates in one path of the tree can switch, andthese gates switch in succession rather than allat once.

Conclusion

The advantages of CoolRunner FZP CPLDs arenumerous. Total standby current is under 100microamps—at least 1000 times less than thatexhibited by CPLDs using sense amplifiers. Totaldynamic power is also decreased, relative toexisting CPLDs, by as much as 70% for a devicewhose logic is fully populated with 16-bit coun-ters operating at 50 MHz. Best of all, thesepower savings are realized with little impact onperformance and with no cumbersome power-down circuitry.

Because power consumption is so low, chip-scale packaging options, once considered impos-sible due to thermal limits, are now offered. As aresult, FZP technology is a key technology forCPLDs because it enables very low-power, high-performance applications.

11

The previous example, expanded to implement aneight-input AND function.

Output = I 0 & I 1 & I 2 & I 3 & I 4 & I 5 & I 6 &

I 1

I 0

I 3

I 2

I 5

I 4

I 7

I 6

Figure 3 - Expanding the number of inputs.

12

New Products - Development Tools

Xilinx and Insight Electronics have jointlydeveloped a low power demonstrationboard that allows you to easily experi-

ment with the new CoolRunner XPLA3 architec-ture, using In System Programming (ISP) to con-figure the device. With this board, and the freeXilinx PC-ISP3 Programmer software, you canimmediately begin configuring a CoolRunnerXPLA3 device with your custom design, directlyfrom your PC. If you need a little help gettingstarted, you can get the XPLA3 Demo BoardUser’s Manual or the VHDL/Verilog tutorial fromthe Xilinx Application Note website.

The XPLA3 CoolRunner family (Figure 1) hasthe lowest power consumption of any CPLD fam-ily on the market. The entire CoolRunner XPLA3Development Board, with its pre-programmed“CoolrunnEr” scrolling marquee pattern, drawsonly 60 µA. Since the board contains other com-ponents that also draw current, such as the on-board low power oscillator and LCD, theCoolRunner CPLD actually draws less than60 µA. Because the CoolRunner product linerequires so little power, it does not need a power

down mode and is the only CPLD family deliver-ing both high performance and ultra low powerconsumption.

Key Features

The development board, shown in Figure 2, isdesigned to demonstrate the low power require-ments and the advanced features of theCoolRunner architecture. The board uses theXilinx XCR3256XL, a 256-macrocell device in aTQ144 package, which can be programmed viathe JTAG ISP port using the provided Xilinx

The CoolRunner XPLA3 Development Kit, from Xilinx and InsightElectronics, is the perfect way to get started using the most efficient, lowpower CPLD on the market.

by John Hubbard, Application Engineer, Xilinx, Inc.,john.hubbard@xilinx.com

CoolRunner XPLA3Development Kit

Draws Only

Figure 1 - The XPLA3CoolRunner family.

60µA

13

Parallel Download Cable III; any JEDEC file thattargets the XCR3256XL can be downloaded.

To power the board you can use either:

• A 3.3V user regulated input.

• A 10.0V maximum input, regulated to 3.3Vusing the on-board regulator.

• A 6.0V AC adapter input regulated to 3.3Vusing the on-board regulator. This AC adapteris included with the CoolRunner XPLA3Development Kit.

Two clock sources are available to theCoolRunner CPLD:

• The on-board, low power 32.768 kHz oscilla-tor.

• Any external clock source with an impedanceof 50 ohms (to match the 50 ohm on-boardtrace impedance).

A prototyping area is also provided, and alldevice I/Os are available for your prototypeeither via the user access headers that surroundthe CoolRunner device or via the 20 through-hole connections routed to specific I/Os. Thetwo-digit seven-segment LCD (shown in thelower left corner of the board in Figure 2) is con-nected to specific I/Os so you can quickly and

visually verify your design; it can be discon-nected from the device if you choose. Controlpins are also included so you can easily imple-ment the Xilinx Watch Tutorial which is availablefor download from http://www.xilinx.com/apps/epld.htm#tutorials.

Conclusion

You can quickly and easily become an XPLA3CoolRunner guru by using the CoolRunnerXPLA3 Development Kit; and it’s available todayfrom Insight Electronics.

Figure 2 - The CoolRunner XPLA3 Development Kit uses only 60 µa (powered here by six grapefruit).

Order the CoolRunner XPLA3 Development Kit from the Insight websiteat: http://www.insight-electronics.com/xcellence/scalable/kit/.The part number is DS-XPLA3-PAK and the price is $95.00.

Download the free PC-ISP3 Programmer software from the XilinxWebPACK website at http://www.xilinx.com/products/software/webpowered.htm.

Visit the XPLA3 CoolRunner website, for the latest CoolRunner information, at: http://www.xilinx.com/products/xpla3.htm.

Get the XPLA3 Demo Board User’s Manual or the VHDL/Verilog tutorial from the Xilinx Application Note website at:http://www.xilinx.com/apps/appsweb.htm.

14

Products - CoolRunner CPLDs

T he 8B/10B data transmission scheme hasbecome the standard for high-speedserial links today. This encoding scheme

translates byte-wide data of random ones andzeros into a 10-bit serial data stream. The8B/10B encoding rules create a DC balancedcode that provides optimum coding efficiency,clock recovery, error detection, and suitability forring or point-to-point topologies.

The 16B/20B transmission scheme incorpo-rates the idea of the 8B/10B transmission codeby combining two 8B/10B modules side-by-side.With 16B/20B encoding, a 16-bit word can beencoded and transmitted serially as shown inFigure 1.

Main Function

Figure 2 shows the block diagram for each8B/10B encoding module. The 8B/10B transmis-sion code includes both data and control charac-ters. Parity is monitored in each data byte sentand determines the encoded data. Each byte of

data is broken into 5B/6B and 3B/4B encodingfunctions. The parallel byte of data to encode[0:7] is referenced A through H, respectively. Thedata is then transmitted serially with controlcharacters i and j.

CPLD Implementation

The 16B/20B encoder module or 20B/16Bdecoder module is targeted to a CoolRunnerXPLA3 CPLD. CoolRunner CPLDs not only pro-vide the lowest power solution today, but enter-ing a design is simple with the WebPOWEREDsoftware tools available. WebPACK™ andWebFITTER™ allow for easy design entry as wellas simulation and implementation. TheWebPOWERED software tools can be down-loaded for free from the Xilinx website, or bygoing to www.xilinx.com/products/software/webpowered.htm

by Jennifer Jenkins, Applications Engineer, Xilinx Inc., jennifer.jenkins@xilinx.com

Implementing a 16B/20B

Encoder/Decoderin a

CoolRunner Encoder/Decoder

16

16

Protocol Device

Serial Data Out

Serial Data In

16B/20B Encoder

16B/20B Decoder

8B/10B 8B/10B

8B/10B8B/10B

CoolRunner CPLD

Figure 1 - 16B/20B block diagram.

Parallel byte of data

Control

6B Bit Control

DisparityControl

4B Bit Control

A

B

C

D

E

F

G

H

A

B

C

D

E

F

G

H

5B Functions5B Functions

3B Functions

10 binary linesto serializer

a

b

c

d

e

i

f

g

h

j

5B/6BEncoding

Switch

3B/4BEncoding

Switch

Figure 2 - 8B/10B encoder logic block diagram.

More Information: For a complete 8B/10B code description and VHDLimplementation, look at XAPP336 “Design of a 16B/20BEncoder/Decoder using a CoolRunner CPLD” on the Xilinx website,www.xilinx.com or by contacting Xilinx Technical Support at 1-800-255-7778.

Here’s an overview of a complete design that youcan download from the Web.

Copper

Performance

Many high-performance applications in net-

working and video processing require large

amounts of on-chip RAM. To meet this

demand, Xilinx recently announced the Virtex™-E

Extended Memory (Virtex-EM) FPGA family that is the

first in the industry to provide over one megabit of

True Dual PortTM Block RAM and is also the first to

offer copper interconnect for optimized performance.

FeaturesThe Virtex-EM family builds on the highly successful

Virtex architecture and includes the following:

• Two devices: XCV405E and XCV812E.

• Over 1-Mbit of True Dual-Port RAM (XCV812E).

• Leading edge 0.18 micron, 6-layer metal siliconprocess.

• New copper interconnect used for top two layers:

- Top layer for uniform on-chip power distribution

- Second layer for clock signals - minimizes clock skew

• Support for 20 I/O standards, including LVDS, BusLVDS, and LVPECL differential signaling standards.

• Over 311 Mbps single-ended I/O performance.

• 622 Mbps differential I/O performance.

• Complete hierarchy of memory resources.

• Eight DLLs for over 311 MHz clock management.

• Direct interface to high-performance externalmemory.

Applications Virtex FPGAs are used in communications, network-

ing, and video image processing applications, where

the inherent flexibility of the architecture allows you

to efficiently implement powerful data path and digital

signal processing (DSP) operations.

Xilinx primarily developed the Virtex-EM family to

address the application requirements of our large net-

working customers. The unique combination of block

RAM and logic, along with copper interconnect,

allows increased data bandwidth and greater integra-

tion; this gives networking companies a very efficient

and reliable platform for their 160 Gbps switch fabrics.

The Virtex-EM family also addresses high-end

video processing, which uses DSP engines to improve

image quality and implement video compression and

decompression algorithms. By using the large block

RAM capacity, both the line buffer memory and either

a video processing engine or a DSP function can be

accommodated on the same Virtex-EM device, which

greatly enhances the overall system bandwidth.

Availability and PricingSamples of the XCV812E are available now, and the

XCV405E will be sampled in June. Both devices are

expected to be in full production in third quarter this

year. The XCV812E and the XCV405E devices are

priced at $235 and $101, respectively for 50,000 units

in Q4 2000.

15

New Products - FPGAs

by Rob Schreck, Product Manager, Xilinx, rschreck@xilinx.com

Virtex-EM FPGAs

Over 1-Mbits of

For more information on the Virtex-EM FPGA family see:http://www.xilinx.com/products/ virtex/ss_virem.htm.

Xilinx extends the Virtex family; new FPGAs use copper interconnect technology for optimized performance.

RAMNEW

New Products - Software

Programmable logic design has entered anera where device densities are measuredin the millions of gates, and system per-

formance is measured in hundreds ofMegaHertz. Given these new system complexi-ties, the critical success factor in the creation ofa design is your productivity. Version 3.1i of theXilinx development systems were created withyour goals in mind-harnessing your creativeengineering talent to the greatest extent possi-ble.

Maximizing Productivity - Keeping YourWeekends Free

Creating your programmable logic design isprobably only part of your job. You may alsohave to complete the board design, verify thedesign in the lab, or help create your productdemonstration. We understand that Xilinx cancontribute to your success by ensuring that theXilinx design flow is as productive as possible.The 3.1i tools include the following improve-ments, making it easier than ever to finish yourprogrammable logic design on time:

• Faster runtimes (2x).

• Faster clock Speeds (2x).

• Advanced HDL synthesis and optimization.

• Improved timing analysis and error naviga-tion.

• Integrated logic analysis.

Runtimes

The 3.1irelease ofXilinxdevelop-ment sys-temsdeliver runtime improve-ments that once again cut place and route run-times in half. This is the fourth consecutive soft-ware release with 50% runtimes reductions,which means that the Xilinx solution is complet-ing designs 16X faster than 4 years ago, asshown in Figure 1. It is important to note thatthese runtime improvements are independent ofcomputing platform, and achieved even whenplacing and routing today’s more complexdevices. Improvements like these are why Xilinxis able to help keep you productive even whenyou are designing with a multi-million gateVirtex device.

Quality of results

To be most productive,you also need placeand route tools thatreliably converge onyour design’s timingrequirements. Xilinxinvented TimingDriven Place and Route for programmable logic

16

by Craig N. Willert, Software Marketing Manager, Xilinx, cnw@xilinx.com

Xilinx Software R&D delivers new version 3.1i software tools that empoweryou to maximize your productivity, while leveraging your creativity.

Figure 1 - Runtime improvements overconsecutive releases.

0

0.2

0.4

0.6

0.8

1

1.3 1.4 1.5i 2.1i 3.1i

Run Time

2X

XilinxDevelopment Systems

Productivity Creativity MeetWhere

in 1992, and through our continued algorithmicinnovations, we remain the leader in deliveringsuperior quality results. In the 3.1i release, youcan achieve 2x performance improvementswhen compared with designs created using thefastest speed grades that were available at thetime of the previous 2.1i release. The industry’smost advanced timing driven place and routetools, coupled with fastest devices, allow you tomeet even the most challenging timing require-ments using Xilinx programmable logic.

Advanced HDL Synthesis and Optimization

Xilinx 3.1i Foundation Series products include anew Block Level Incremental Synthesis (BLIS)capability that enables you to rapidly convergeon your design’s timing requirements. Synopsyshas built this capability exclusively for Xilinx.BLIS is based on the concept of focussing theoptimization of HDL on a module by modulebasis, localizing the changes within a module,and therefore improving the efficiency of guideddesign. BLIS is yet another design methodologythat Xilinx is delivering to help you completeyour design more efficiently.

Error Navigation and Timing Analysis

Having thorough and informative reports on theprocessing of your design also increases yourefficiency. Furthermore, presenting this informa-tion in an intuitive and efficient format is alsoimportant; reviewing the reports is now easierthan ever:

• Error Navigation - For warnings and errorsthat may arise during design compilation,Xilinx provides a direct link to a wealth ofSolution Records that exist on our website(www.support.xilinx.com). These SolutionRecords provide answers to problems as sim-ple as “incorrect pin connections” as well asmore complicated problems like “how toobtain better clock rates using digital DelayLock Loops”.

• Timing Reports - For information on yourdesigns timing, the Xilinx Interactive TimingAnalyzer includes a new and improved hier-

archical browsing capability. The new TimingAnalyzer also includes a powerful “what if”analysis feature that allows for immediateanalysis of your design when targeting differ-ent device speed grades, or using differenttiming constraints. Furthermore, Xilinx hasrewritten its timing analysis algorithms so itrequires substantially less memory and pro-cesses designs far faster. The combination ofthese improvements means it is easier toquickly analyze the performance of yourdesign.

Integrated Logic Analysis

Your job isn’t done until after your design hasbeen incorporated into the production system asillustrated in Figure 2. To assist you in verifyingyour programmable logic device’s behaviorwithin the system, Xilinx now providesChipScopeTM ILA, the Integrated Logic Analyzer.With ChipScope ILA you can perform complexsystem analysis on the behavior of your designas it works in real-time, within the system. TheIntegrated Logic Analyzer allows you to capturethe waveforms of control signals, data buses, orany general logic within your Xilinx FPGA, andeasily analyze their timing and functionalityusing ChipScope’s easy-to-use graphical userinterface. Helping you detect problems in thefunctionality or timing of your design within yoursystem is another example of how Xilinx helpssupport you in becoming successful. (See thecompanion article on page 19.)

17

JTAG

JTAGConnectionMultiLINX Cable

Target Board

PC with Chipscope

Target FPGAwith ILA cores

UserFunction

UserFunction

UserFunction

ILAILA

ILAControl

Figure 2 - Integrated logic analysis.

Emphasizing Creativity - How GoodDesigns Become Great

Mainstream design flows enable you to enteryour design’s functional and timing requirementsand then “hand them off” to the layout tools tocomplete the job. Xilinx development systemsare engineered to simplify the process of com-municating your expert knowledge to ouradvanced design algorithms.

The 3.1i release includes new and improved ver-sions of the following implementation tools:

• Xilinx Core Generator.

• Xilinx Constraints Editor.

• Xilinx High Level Floorplanner.

This powerful collection of tools will helpmake the process of creating your next pro-grammable logic design the most efficient andproductive yet.

Core Generator

By allowing you to easily reuse IntellectualProperty, built elsewhere within your organiza-tion or by a 3rd party provider, the Xilinx CoreGenerator allows you to focus your creativeenergies on creating the unique aspects of yourdesign, ensuring your products’ success in themarketplace. The 3.1i release of the CoreGenerator delivers improvements in the graphi-cal user interface, design flows, plus there is ahost of new cores. See the IP Centerhttp://www.xilinx.com/ipcenter/index.htm tolearn about the Intellectual Property that is avail-able for your use.

High LevelFloorplanner

In the 3.1i release,the XilinxFloorplanner hasbeen enhanced todeliver the benefits

of true modular design. The 3.1i floorplannermay be used in conjunction with the Xilinx

Modular Design tools to enable the independentTiming Driven layout of functional modules of adesign. Another benefit of the new Floorplanneris the new pin layout capability, which makes itsimple to assign your design’s I/O signals to thedesired device pins.

Xilinx Constraints Editor

The 3.1i Xilinx Constraints Editor is another hugestep forward in timing driven place and routeefficiency. It simplifies the art of defining yourcircuits timing specifications, taking advantageof the industry’s most robust timing constraintlanguage—TimeSpecs™. In 3.1i, the ConstraintsEditor also supports the definition of timing con-straints on a hierarchical basis, thus supportingmodular design.

Furthering the art of logic design

The Xilinx 3.1i release has already been heraldedas the industry’s best programmable logic designtool. In the future, you will enjoy even more pro-ductivity because the Xilinx Software R&D teamis already hard at work inventing tomorrow’sbreak-through design techniques. While many ofthese inventions won’t be available for main-stream use until our next major software release,some of these advancements will be includedwithin our regular quarterly software updates.Please stay tuned for further announcementsabout your state-of-the-art programmable logicdesign system.

Conclusion

By focussing our resources on the challenges ofproductivity, Xilinx enables you to spend moretime on the creative aspects of your design. Thishelps you get to market faster, and deliver amore robust product to your customers. TheXilinx 3.1i development systems deliver superiorpush-button, interactive, and state-of-the-artdesign methods. The 3.1i release will begin ship-ping to all registered, in-maintenance customersthis spring. To learn more, please visit the Xilinxweb site www.xilinx.com.

18

19

Software

The need for thorough de-bugging capabili-ties in today’s multi-million gate FPGAdesigns is critical, and verifying logic

externally, by probing package pins or boardtraces, is becoming increasingly difficult. Tosolve this problem, Xilinx has created a solutioncalled ChipScope ILA™ that integrates the verifi-cation capability into the silicon itself. The newChipScope Software, combined with theIntegrated Logic Analysis (ILA) and theIntegrated Control (ICON) cores, allows you tohave real-time, full speed access to any node orbus in the chip, with an easy-to-use GUI inter-face. With these powerful tools, you will spendless time verifying chip functionality and shortenyour time-to-market for Virtex, Virtex-E, andSpartan-II FPGA designs.

Xilinx Partners with Agilent Technologies

Xilinx developed ChipScope ILA with AgilentTechnologies, the industry leader in LogicAnalysis. Output from the ChipScope ILA tool iscompatible with the Agilent 16700 series logic

analyzers, as well as other industry standards.Using the Agilent analyzers along withChipScope ILA output gives you the possibility ofexpanding analysis to the board and systemlevel.

The Advantages of Programmability inLogic Analysis

Programmable logic provides many uniqueadvantages for on-chip logic analysis comparedto fixed logic (ASIC ) solutions. Since ChipScopeILA cores compiled into a device can beremoved after analysis is complete, customerssave silicon overhead by not having to perma-nently lodge test structures on their die. In addi-tion, the cores can be modified and re-placed onthe device depending on the signals chosen foranalysis. Only a programmable solution allowsthe user to change the physical silicon. In anASIC, if similar cores were included and a subse-quent change was required, a new mask set,additional NRE, prototype leadtime and engi-neering time would be required. For ASIC proto-

by Shelly Davis, Sr. Product Marketing Manager, Xilinx,sdavis@xilinx.com

with ChipScope ILA

On-chip, Real-timeLogic Analysis

The need for thorough de-bugging capabilities in today’smulti-million gate FPGA designs is critical.

typying, ChipScope ILA provides a highly accu-rate analysis vehicle that can speed up ASICdevelopment time. For programmable systems,it is truly an innovative method to speed up veri-fication and get to market quickly.

How it Works

ChipScope ILA cores are generated through theWeb, and the ChipScope software can be quicklydownloaded to your PC. Once the ILA and ICONcores are integrated into your FPGA design, theChipScope software leads you through the pro-cess of downloading control information to theFPGA, modifying trigger and set-up functions,and displaying the captured waveforms. The

Integrated Logic Analyzer core (ILA) provides thetriggering and trace capturing functions, and theIntegrated Control core (ICON) communicates tothe dedicated FPGA JTAG pins. A MultiLinx cableprovides a USB/RS232 interface for communica-tion between the FPGA and the ChipScope soft-ware. This is illustrated in Figure 1.

The process works as follows, and is illustratedin Figure 2:

1. The ILA and ICON cores are generatedthrough the Web using a Java application.

2. You insert the cores into your HDL code andconnect them to the internal busses and sig-nals that you want to monitor.

20

JTAG

JTAGConnectionMultiLINX Cable

Target Board

PC with Chipscope

Target FPGAwith ILA cores

UserFunction

UserFunction

UserFunction

ILAILA

ILAControl

Figure 1 - Integrated Logic Analyzer (ILA) block diagram.

Generate ControlCore and ILA Corethrough the Web

Insert Controland ILA Coresinto HDL Code

Connect Bussesand Internal Signals

Synthesize Designusing

Xilinx DesignTools

Place and Routethe Design with

ILA Cores

Download Bitstream,View and AnalyzeUsing ChipScope

Software

Figure 2 - ChipScope ILA flow.

3. You synthesize your design,and place and route it usingeither the Xilinx FoundationSeries or Alliance Seriestools.

4. You download the final bitstream to theFPGA.

5. Your design can then be analyzed through theChipScope software.

Features

The ChipScope ILA tools are powerful and accu-rate, and they provide everything you need tothoroughly verify your logic and make your jobeasier, including:

• User selectable data channels (from 1 to 256channels) - Accurately captures wide data busfunctionality.

• User selectable sample size (from 256 to 4096samples) - The large sample size increasesaccuracy and the probability of capturinginfrequent events.

• Separate bus trigger (with user selectablewidth of 1 to 64 bits) - Separate trigger busreduces the need for sample storage.

• All data and trigger operations are syn-chronous to your clock (up to 155 MHz) -Capable of high speed data capture.

• Triggers are in-system changeable withoutaffecting your logic - No need to signal stepor stop your design for logic analysis.

• Writes waveforms to VCD and FBDF format -Compatible with Agilent Technologies andother waveform viewers.

• Easy to use graphical interface - Makes learn-ing the software very easy; it guides you

through selecting the correctoptions.

• Up to 15 independent ILAcapture cores per device - Cansegment logic and test smaller

sections of a large design for greater accu-racy.

• Multiple trigger settings - Records durationand number of events along with matchesand ranges for greater accuracy and flexibility.

• Downloadable from the Xilinx website -Software and cores easily accessed anddownloadable through the Xilinx XpressoCafe e-commerce site.

And More to Come

In the following months, additional verificationtools will be available for use within theChipScope suite. The Internal PerformanceAnalyzer (IPA) core will allow you to log andcapture events, and the Integrated Self-Testmodule (IST) will provide self test capability atthe device level. In addition to being availablethrough the Xilinx Xpresso Cafe e-commercesite, the tools will be integrated into the Xilinx3.1i series software tools.

Conclusion

On-chip, full speed, full-featured logic analysis isnow a reality. With ChipScope ILA, your designswill be up and running faster than ever and withless effort. For more information see www.xil-inx.com or purchase the tools from the Xilinx e-commerce site at www.xilinx.com.

21

Co-Developed with AgilentTechnologies

The ChipScope software and ILA core

were developed in partnership with

Agilent Technologies, today’s market

leaders in logic analysis, and the FBDF

format output from ChipScope is com-

patible with the Agilent Technology

16700 series analyzer. Visit Agilent at

www.agilent.com

JTAG

New Products - Software

In the new Xilinx JTAG Programmer v3.1 soft-ware there are significant modifications thatimprove your productivity and aid in quickly

bringing up chains of Boundary Scan (JTAG)devices. Here are some of the new features:

• Chain Integrity Test - This allows you toverify the integrity and robustness of theBoundary Scan chain to determine its electri-cal integrity. This is the first step in analyzingwhy devices in the chain may not be configur-ing correctly. This test repeatedly reads theIDCODE register to identify issues related toelectrical noise. You can choose the devicethat will be addressed and then select thenumber of times to loop and read the IDCODEregister. A visual pass-fail indication tells youwhether the chain is working properly. Byincreasing the number of times the deviceloops through this sequence you can get anidea of the robustness and relative noiseimmunity of the Boundary Scan chain.

• Readback Capability - This function readsthe contents of the FPGA configuration mem-ory and compares it against the bitstream file.You can use this to verify the correctness ofthe configuration operations as well as todetermine that the appropriate bit stream filewas downloaded.

• BSDL Files are Not Required - Now youhave the ability to use third-party BoundaryScan devices with the JTAG programmer soft-ware without having their associated BSDLfiles. All you need to do is indicate the size ofthe instruction register, which is readily avail-able from the device datasheet. If you havethe BSDL file, you can use it as before.

• New Devices Added - Xilinx has paved theway for fully JTAG-compliant PROMs with theintroduction of the new XC1800 series. TheseIRL-enabling ISP PROMS feature a BoundaryScan input for downloading along with paral-lel load (byte-wide) output capability for con-figuring Spartan devices in Express mode orVirtex devices in SelectMAP mode. TheXC1800 Proms are all now supported in JTAGProgrammer.

As Boundary Scan grows in importance,push-button, easy-to-use configuration ofdevices is quickly becoming a necessity. Xilinxhas added several new features to the latest edi-tion of JTAG programmer to make BoundaryScan chain debugging and device programmingmuch easier.

22

PERFORMANCEENHANCEMENTS

by Frank Toth, Marketing Manager ConfigurationsSolutions, Xilinx, frank.toth@xilinx.com

For the latest version of JTAG Programmer, please go to the WebPACKsite at: http://www.xilinx.com/sxpresso/webpack.htm.

Programmer v3.1

for

As Boundary Scan becomes more important as a method for accessing PLDs for programming, robust JTAG tools become essential.

23

CSoftware - FPGA Synthesis

As FPGA densities soar past the million-gate level, there are enough transistorsto put entire systems on a single device.

To help manage these complex designs andreduce simulation time, large systems are typi-cally prototyped, tested and debugged in soft-ware that is usually written using the C program-ming language. C code can execute 10 to 100times faster than code written in either VHDL orVerilog HDL, and for complex communicationssystems C simulation is the often the only alter-native.

For hardware implementation, C-languageprototypes are usually migrated to an FPGA toenable optimum flexibility and reconfigurability.The Frontier Design A|RT Designer efficiently andaccurately maps a large software design (such asa DSP algorithm written in C code) onto an opti-mized hardware architecture (FPGA). A|RTDesigner is ideal for creating a processor-likearchitecture for DSP algorithms such as speechcompression, image processing, and for themajor blocks in communications systems suchas GSM, W-CDMA and IS-136.

Implementing C Code in a HardwareArchitecture

Algorithms and systems written in C code aresets of sequential operations that have no regardfor resources, parallelism, or timing. Thesequential nature of software means that clock-ing and parallelism are not considerations. Toget a piece of software into dedicated hardware,specific hardware resources, such as ALUs, mul-tipliers, adders, RAM, ROM, and registers, mustbe created and the various operations assignedto them. The operations must then be scheduledso that data dependencies are accounted for.The only way to arrive at the optimum architec-ture is to look at how the operations are exe-cuted on a variety of architectures until the bestsolution is found.

Until now, there have been no EDA tools thatsupport the exploration of alternative hardwarearchitectures. There was no way to engage in anintermediate architectural exploration betweensoftware and silicon. Writing the design in ahardware description language (HDL) requiresan explicit architecture because an HDL is a

by Doug Johnson, Business Development Manager, FrontierDesign Inc., doug_johnson@frontierd.com

Architectural Synthesisfrom Behavioral

Codeto Implementation in a Xilinx FPGA

The Frontier Design A|RT Designer product efficiently maps a softwaredesign into a hardware description language implementation suitable forFPGA synthesis.

24

description of the actual register transfers in aspecific architecture. Writing a complex design ina hardware description language is too difficultand time consuming to do more than once.

Design Flow Using the A|RT Tools

The EDA software tools from Frontier Designbridge the gap between the complex system asdescribed in C code and it’s final implementationin optimum hardware architecture. FrontierDesign has applied its 15 years of experience intransforming DSP algorithms (written in C code)into working silicon, to create a methodologythat is called “Algorithm to Register Transfer,” orA|RT.

The focal point of the design flow shown inFigure 1 is the A|RT Designer tool that takes theC code and transforms it into synthesizableVHDL and Verilog HDL that is suitable for drivingFPGA synthesis tools. A|RT Designer automati-cally synthesizes hardware architectures directlyfrom behavioral-level C-language programs and

then generates a register-transfer-level HDLdescription.

With A|RT Designer, you can interactively addor remove resources, re-assign operations oralter their scheduling, and then analyze theresulting performance characteristics. A|RTDesigner is not constrained by parameters suchas clock rate or silicon area, so multiple archi-tectures can be explored very quickly. A|RTDesigner automatically generates a reconfig-urable datapath architecture, plus a VLIW (VeryLarge Instruction Word) processor andmicrocode to direct and schedule operations.

Interactive Architectural Synthesis

Although A|RT Designer can be used to automat-ically synthesize a push-button architecture withminimal intervention by the user, it has beendesigned with an interactive paradigm from thebeginning. A wide variety of reports are avail-able to help you analyze the characteristics ofthe design. Based on the design constraints, youhave a variety of optimization options, plus avariety of directives that you can use to refinethe architecture. Design iterations can take aslittle as a few minutes, so you have the freedomto explore multiple processor architectures veryquickly.

Using A|RT to Target Optimum FPGAImplementation

A|RT Designer converts the C behavioral modelof an algorithm into an RTL netlist. The resultinghardware architecture consists of a set of datapath blocks that are controlled by a microcode-based controller. The datapath blocks are funda-

A|RT Library C SourceCode

C/C++ SimulationEnvironment

A|RT Designerand

A|RT Builder

Reference Vectorsand Stimuli

HDL SimulationRTLHDLCode

FPGASynthesis

Xilinx FPGAAlliance Tools

1.5is2

Pre-DefinedLibrary

Generator

Figure 1 - A|RT design flow.

25

mental DSP building blocks such as multipliers,ALUs, register files, RAM, and ROM. Figure 2 is asimplified illustration of the processor architec-ture used by A|RT Designer.

One of the most powerful capabilities of theA|RT methodology is the ability to target pre-defined, optimized components in the C code,such as those created by the Xilinx CoreGenerator and those in the Xilinx LogiCORElibrary. By exploiting these predefined buildingblocks, a highly optimum, silicon-efficient imple-mentation of the architecture is possible. Foreach of the LogiCORE blocks, it suffices to createa simple model file for the resource, containinginformation on the I/O pins, the cycle-level tim-ing, the instructions available on the resource,and the C functions that can be mapped to thoseinstructions. In addition, A|RT Designer performs

resource sharing. This means that the tool canreuse the same resource within several clockcycles. For implementation in Xilinx FPGAs, theLogiCORE blocks can be resources A|RTDesigner uses to build the datapath. The data-path will optimize silicon area and achieve high-est performance since they are already opti-mized for the FPGA architecture.

Conclusion

The benefits to the communications systemengineer and DSP algorithm designer and hard-ware engineer are enormous because theLogiCORE and Core Generator blocks are nowusable by both the system engineer and thehardware engineer. The system engineer cannow incorporate pre-defined hardware function-ality directly in C code. The hardware engineergets a VHDL or Verilog HDL model from A|RTDesigner that directly instantiates area and per-formance-optimized LogiCORE and CoreGenerator DSP building blocks.

Also, a DSP algorithm typically requiresextensive memory such as register files or blockRAM and the tools can be directed to target theblock RAM capabilities of the Spartan and Virtexdevices extending the efficiency of the targetFGPA.

A|RT Designer is supported for PC Windows/NT 4.0, for HP-UX 10.20,and for Sun/Solaris 2.7. For more information, please see the FrontierDesign website at www.frontierd.com.

ALUMULTMAC 0 .. n

RAMROMACU 0 .. n

ASU

0 .. n

AutomatedArchitectureGeneration

Resource Sharing Architectural Exploration

Automated Controller Generation

ASU=> Application Specific UnitAn ASU is a user defined processing block that can

perform an operation such as an FFT butterfly

Automatic Sceduling

Instruction ROM

Status and BranchFSM

PC

Figure 2 - A|RT designer processor architecture.

26

New Products - Cores

by Amit Dhir, Sr. Engineer, Strategic Applications, amit.dhir@xilinx.com

As more companies conduct businessover the Internet, transaction security isa major concern. Therefore, to help pave

the way for secure e-commerce, Xilinx andXentec, Inc. recently announced the availabilityof two new core products for Virtex, Virtex-E,and Spartan-II FPGAs. The Xentec encryptioncores, along with the inherent flexibility of XilinxFPGAs, makes it easier for you to create securedata transmission systems.

NIST Certification

The National Institute of Standards andTechnology (NIST) currently recommends theuse of Data Encryption Standard (DES) andtriple DES (3DES) cryptographic algorithmsfor data security. The DES functionencrypts 64-bit data using a 64-bitsecret key. Authorized users can onlydecrypt data with the same key.Triple DES is a cascaded chain ofthree single DES functions to fur-ther enhance the security.

Xentec’s X_DES core is certified by NIST toconform to the FIPS 46-3 and ANSI X9.52 specifi-cations. (See http://csrc.nist.gov/cryptval/des/desval.htm for more information). Both theX_DES and X_3DES cores contain encryptionand decryption functions selectable by internalcontrol. In secure data communications, thesame core is used at both transmit and receiveends.

The X_DES core supports all four standardDES modes: Electronic Code Book (ECB), CipherBlock Chaining (CBC), Cipher Feedback (CFB),and Output Feedback (OFB). The X_3DES triple

DES core supports the most popular ECB modewhile customization is available for othermodes. Both cores process a new encryption

or decryption every 16 clock cycles.

New DES and Triple DES cores meet the requirements for high-performance systems as well as smart cards, cable modems, andBluetooth wireless systems.

“Systems which require flexibility and high-performance integration will benefit from theVirtex series version, while cost-sensitive, high-volume consumer applications will benefit fromthe Spartan-II versions” said Vincenzo Liguori,design manager of the multimedia group atXentec.

27

Use the Virtex Series forHigh PerformanceSystems

Virtex series FPGAs are wellsuited for high-performanceapplications due to their highclock speeds, large gate den-sities, and system-level fea-tures. The X_DES core runs atan effective bit rate of about 500 Mbits/sec inXilinx Virtex-E devices.

You can easily integrate the small DES andtriple-DES cores with other Xilinx IP solutions tobuild large complex systems in Virtex seriesFPGAs. These include Internet, intranet, andextranet networks facilitating secure business-to-business transactions, satellite digital cinema,secure satellite broadcast, secure video surveil-lance, and space imaging systems.

Use the Spartan-II Series for ConsumerApplications

The DES and triple-DES cores are very compact.The cores targeted for the Spartan-II FPGA familyoffer a low-cost solution that you can use incombination with other Xilinx IP solutions todevelop consumer appliances that include e-commerce security enabled PCs and cablemodems, set-top boxes, wireless LAN andBluetooth wireless systems, prepaid smart cards,and personal banking systems.

Pricing and Availability

The cores are sold and supported by XilinxAllianceCORE™ partner, Xentec, Inc. of Ontario,Canada. The X_DES and X_3DES cores are

immediately available for usein Xilinx Virtex series andSpartan-II FPGAs. The netlistversions of the X_DES andX_3DES triple DES cores listat $7,500 and $10,000 respec-tively. All Xentec productscan be purchased directlyfrom Xentec; the data sheetscan be downloaded from the

Xilinx IP Center (www.xilinx.com/ipcenter), acomprehensive resource for system-level intel-lectual property and services.

Conclusion

Whether you are creating low-cost, high-volumeconsumer equipment or high-cost, high-perfor-mance systems, its very easy to incorporate ahigh level of data security into your designs. Thecombination of Xentec DES cores and XilinxFPGAs gives you a very flexible solution that willget your secure products to market as soon aspossible.

About Xentec

Xentec, Inc. provides comprehensive ASICand FPGA design services, integration exper-tise, and technology for the product develop-

ment requirements of the world’s leadingelectronics companies. Founded in 1995,

Xentec’s mission is to be the leading providerof analog/digital integrated circuit designservices and Intellectual Property used in

System-on-Chip (SoC) based integrated cir-cuits for all facets of the electronics industry.The company is headquartered in Oakville,Ontario and is privately funded. More infor-mation about the company, its products, and

services may be obtained from the WorldWide Web at www.xentec-inc.com. For

inquiries regarding Xentec cores and servicesplease contact sales@xentec-inc.com.

m0

m1

m2

c0

c1

c2

000001010011100101110111

000001010011100101110111

Data Encryption Cores

28

New Products - Cores

Xilinx and Xentec recently announced newAllianceCORE products for Image pro-cessing. These cores include a

discrete/inverse discrete cosine transform (DCTand IDCT) and a JPEG codec. The DCT/IDCT coresupports Virtex, Virtex-E, and Spartan-II devices,and is a critical building block in Dolby AC2 andAC3, JPEG, and MPEG compression systems. TheJPEG codec supports Virtex and Virtex-E devices,and provides a fully integrated encoder-decoderpair used in image compression and decompres-sion applications.

Target applications for the new cores includeimage storage, data and video compression,medical imaging, and industrial systems. Xentecdeveloped these very compact image compres-sion cores by using the versatile DSP features inthe Spartan-II and Virtex architectures.

DCT and IDCT Solution in a $10 FPGA

The DCT/IDCT core enables high-speed hard-ware implementation of the forward and inversediscrete cosine transform functions. DCT andIDCT (Inverse DCT) functions are the building

blocks of JPEG, MPEG, and ITU-T H261 stan-dards-based codecs that are used in many imageprocessing applications.

A DCT function is a key element in a com-pression system that splits still-image pixels intosmaller data blocks. It calculates a value to rep-resent each block that can be used to reduce thestorage space required for the overall image. TheIDCT function operates in reverse and recon-structs the image from compressed data.

Xentec’s DCT/IDCT core performs both DCTand IDCT functions and is ideally suited for sys-tems that require both image compression anddecompression. It supports both DCT and IDCTon 8x8 image pixel data. DCT or IDCT mode isselected by means of a control signal. The corefits in a single XC2S100 Spartan-II FPGA thatcosts just $10 in high volume.

“Digital imaging applications typically needthe power of 32-bit processors for implementingthe computationally intensive DCT/IDCT func-tions in software,” said Robert Bielby, XilinxDirector of Strategic Applications. “By movingthe DCT/IDCT function into a cost-effective

These new cores target JPEG, MPEG, DSP, and imageprocessing applications.

by Antolin Agatep, antolin@xilinx.com, Systems Architect, Embedded Systems

Spartan-II device, designers can now usecheaper eight-bit microcontrollers and cut downthe overall system costs.”

Integrated JPEG Codec Solution

JPEG is an image compression technique forreducing image file sizes without a noticeabledifference in image quality. The Xentec X_JPEGcodec core conforms to the ISO/IEC 10918-1JPEG baseline specification and performs bothcompression and decompression functions. Thefull-featured core includes support for stallingand the ability to handle four-color components.It is extremely flexible, including four pro-grammable quantization and four programmableHuffman tables that allow you to specify quanti-zation, Huffman table, and the quantity of pixelblocks assigned for each color component.

“The memory hierarchy in the Xilinx Virtex-EFPGAs enabled us to develop an extremely smallJPEG core,” said Xerxes Wania, President andCEO of Xentec. “We used distributedSelectRAM™ to build ROM-based Huffman tablesthat are distributed across the design andembedded block SelectRAM for the largeDCT/IDCT, quantization, and zig-zag codingtables. The end result is a flexible, optimizedcodec solution that includes both logic andmemory in a single medium-density FPGA.”

Spartan-II FPGAs

The Spartan-II family delivers 100,000 systemgates for under $10 at speeds of 200 MHz andbeyond, and provides unmatched design flexibil-ity. These low-power 2.5-volt devicesfeature I/Os that operate at 3.3 voltswith full 5-volt tolerance. Spartan-IIdevices also feature multiple DelayLocked Loops (DLLs), on-chip RAM(block and distributed), and the versa-tility of SelectI/O™ technology sup-porting over 16 high-performanceinterface standards, in a device that

offers unlimited programmability and can beupgraded in the field.

Virtex-E FPGAs

The Virtex-E family has made significantimprovements in the areas of capacity and per-formance over the original Virtex series. Thefamily features devices with 3.2 million gates,832 Kbits of True Dual-Port internal block RAM,eight digital Delay Locked Loops (DLLs) capableof over 300 MHz clock frequency for system tim-ing, and three new differential signal standards.The Virtex-E FPGAs are the first programmablelogic devices delivered on 0.18-micron processtechnology, which Xilinx jointly produced withTaiwan’s UMC Group. The improved processdirectly contributes to the 30 percent perfor-mance gain for all internal functionality. Also,the Virtex-E family represents the industry’s firstprogrammable logic architecture with 210 mil-lion transistors on a single device.

Availability and Pricing

The X_JPEG and X_DCT_IDCT cores are immedi-ately available from Xentec, Inc. The DCT andIDCT core is available for use in Spartan-II,Virtex-E, and Virtex FPGAs, and lists at $10,000for the netlist version. The JPEG codec is avail-able for use in Virtex-E and Virtex FPGAs, andlists at $30,000 for the netlist version. All Xentecproducts can be purchased directly from Xentec.The datasheets can be downloaded from theXilinx IP Center (www.xilinx.com/ipcenter), acomprehensive resource for system-level intel-lectual property and services.

Conclusion

Xilinx FPGAs, along with the Xenteccores, provide a complete solutionfor creating image processing appli-cations. This combination helps youquickly get your products to market,saving you time and money.

29

Success Story - Cores/QPRO

CelsiusTech Electronics AB specializes inadvanced electronic military systems. InMay 1999, they evaluated the feasibility

of using FPGAs and IP modules for their newdesigns. Five microcontrollers were evaluated,and the Dolphin Flip8051-PR AllianceCORE prod-uct along with Xilinx Virtex QPRO FPGAs wereselected as the perfect solution.

Dolphin’s Flip8051-PR is available for use inthe Xilinx Virtex, Virtex-E, Virtex QPRO, andSpartan-II devices. The Virtex QPRO family isfully qualified for military use and offers a widerange of devices up to 2-million gate densities.The Flip8051-PR 8051 microcontroller core isknown as the fastest 8051 Virtual Component forASIC applications, running an average of eighttimes faster than the legacy i8051, and it givesyou enormous flexibility, something a standarddevice can’t offer. This combination of speed,flexibility, density, ease of use, and military quali-fication was an easy choice.

Developing a Radar Warning Receiver

One of the systems currently being developed byCelsiusTech is a Radar Warning Receiver (RWR)system, used in a supersonic combat aircraft

(see Figure 1). The system receives, detects,identifies, and warns the pilot of hostile radarsignals without warning the enemy. The front-end unit of the RWR system needs a compactand reliable IP module control processor, such asthe 8051 family microcontroller. Since this front-end unit is mounted external to the supersonicaircraft, it is subjected to severe mechanical,thermal, and electromagnetic conditions.

The RWR system includes the RWRW front-end unit, Central RWR Computer, and GroundMaintenance Computer (see Figure 1). The front-end unit is composed of:

• FLIP8051-PR IP module with internal ROMand RAM integrated into the FPGAs usingblock RAM and distributed RAM features.

• Microwave Receiver Subsystem, DSP Functionblock.

• Two serial links: a standard 8051 UART andan in-house High Speed SerialTransmitter/Receiver module.

Easy Integration of the Core

The Flip8051-PR core was easy to implement ina Virtex XCV300 FPGA and it was successfullyintegrated with all the sub-modules of the RWR

30

Using an 8051Core and

Virtex QPROFPGAs in

by Oscar Blanquez, Project Manager, Dolphin Integration, S.A., logic@dolphin.fr, Lars Albihn, Sr. Design Engineer, CelsiusTech Electronics, AB, lral@celsiustech.se,Anil Telikepalli, Sr. Technical Marketing Engineer, Xilinx, Inc., anil@xilinx.com

A Swedish company develops unique military products using XilinxVirtexXCV300 FPGAs and a high speed 8051 core.

MILITARYAPPLICATIONS

31

system within a short time. The core providedkey advantages such as:

• Code compatibility with legacy i8051.

• Easy access to Special Function Register (SFR)space.

• Demultiplexed address/data bus for memoryinterface.

• Choice of bidirectional/unidirectional I/O.

• Bus Monitor function for simulation.

The design team at CelsiusTech found thecore’s SFR Bus Interface especially helpfulbecause it allowed them to easily add peripher-als to the core (see Figure 2). The SFR bus givesa lot of flexibility, especially when designing sys-tems that include many on-chip peripherals.

CelsiusTech has also used the FLIP8051-PR inseveral other applications, incorporating highlyapplication-specific peripheral functions.

Using the Bus Monitor forCore Validation

Before implementing the applica-tions in the FPGAs, the systemswere fully simulated and verifiedusing a Bus Monitor function pro-vided by Dolphin. The Bus Monitorinteracts with a simulation tool suchas Model Technology’s V-System

and generates text messages of disassembledinstructions so errors can be observed and easilyfixed (see Figures 3 and 4).

The Flip8051-PR core has a dedicated portused by the Bus Monitor behavioral model fortracing code execution and disassembly in realtime. In addition, the dedicated port monitors themicrocontroller interrupt status.

Once simulations were verified, the designwas downloaded into the Xilinx Virtex V300FPGA and integrated into the evaluation board(see Figure 5). The core worked successfully onthe first attempt and the CelsiusTech team wasable to incorporate additional peripherals on thesame evaluation board.

Data to Peripherals

Datafrom

peripherals

SFRAddress

WR enable

Flip8051-PR

Mux

Figure 2 - SFR Bus Interface.

SimulationEnvironment

Bus Monitor PortAddress

DataMemory control

Program code

Disassembled Instructionsand micro-controller status

display in simulator

Flip8051-PR

Bus Monitor

Program

Data

Memory

Memory

Figure 3 - Typical use of the Bus Monitor functionality.

Test

ThreatInformation

Data

High-speedserial lnks

Information fromother sensors

RWR Front-end Unit

Antenna

ControlTest

ControlCountermeasures

Control

GroundMaintenance

Computer

Medium-speedLink

MicrowaveReceiver

SubsystemADC

DSPFunctions

FLIP8051-PRControl

Processor

Central RWRComputer

Figure 1 - Radar Warning Receiver (RWR) system.

“The need for support from Dolphin has beenless than originally anticipated, mainly becausethe FLIP8051-PR has proved to be a maturedesign of high quality,” said Lars Albihn, seniordesign engineer at CelsiusTech. By using aproven AllianceCORE product from Dolphin in aXilinx FPGA, CelsiusTech was able to save bothtime and money while benefiting from the tech-nical expertise of Dolphin.

Software Tools

Dolphin has partnered with Raisonance(www.raisonance.fr) to provide a full softwaretool suite, the Flip8051-Rkit. The tool suite con-sists of a C compiler, an assembler, a linker, areal time OS, a ROM monitor, and a simulator.

The simulator facilitates simulation of both stan-dard 8051 peripherals and user specific peripher-als.

Conclusion

Based on the successful evaluation and deploy-ment of the Flip8051-PR core in their systems,CelsiusTech concluded that using IP modules isthe best method for their system design onFPGAs. Thanks to features such as high-speedexecution, SFR Bus Interface, and Bus Monitor,the FLIP8051-PR in a Xilinx FPGA has proved tobe a reliable, flexible and easy to use VirtualComponent. It is an ideal solution that adds theexpertise from Dolphin to the flexibility and sys-tem level features of Xilinx FPGAs thus, reducingthe overall time-to-market.

32

Figure 5 - CelsiusTech Evaluation Board.

For more information and a datasheet of the Flip8051-PR core, see theXilinx IP Center, a comprehensive resource for system level intellectual

property and services: www.xilinx.com/ipcenter

Dolphin Integration, is a Xilinx AllianceCORE partner in Europe withexpertise in digital, analog, and mixed signal circuits. They provide IP

solutions for processors, telecom, and multimedia systems.

Dolphin Integration, 39, Avenue du Granier, BP 65 Zirst, F-38242 MEY-LAN Cedex, FRANCE, www.dolphin.fr

CelsiusTech Electronics AB, Nettovägen. 6, JAKOBSBERG, SE-175 88JÄRFÄLLA, SWEDEN, www.celsiustech.se/electronics

Figure 4 - Screen dump of Bus Monitor Model Technology’s V-System.

“The need for support from

Dolphin has been less than origi-

nally anticipated, mainly because

the FLIP8051-PR has proved to be

a mature design of high quality,”

33

Nallatech Ltd. recently announcedanother new addition to its DIMEStandard family, a revolutionary new

module named “Ballyderl” that provides an intel-ligent, dynamically reconfigurable platform withhigh speed off-board communication. Basedupon the DIME plug-and-play capability, thismodule harnesses the Virtex system-level fea-tures and enables you to quickly build multipleFPGA systems.

Using the latest data transmission technolo-gies, you can attain clocking rates over 311 MHz,collectively allowing a data transmission andreception rate of 2.4 Gbytes per second. Thiscomplements the 2.5 Gbytes/sec capability thatis currently available on other DIME modules.

DIME: DSP and Image Processing Modulefor Enhanced FPGAs.

The Ballyderl module incorporates a wide rangeof Virtex and Virtex-E FPGAs, from the XCV600to the XCV2000E, giving maximum flexibility thatis further enhanced by a variety of digital I/Otransmission options and two independent 64Mbytes banks of SDRAM, as illustrated in Figure 1.

The module features two build options fortransmitting and receiving the 64 digital I/O sig-nals:

• Low Voltage Differential Signaling (LVDS).This option allows you to pass your data overlong distances at high rates while maintaining

low power consumption and low susceptibil-ity to common mode noise and EMI effects.

• Single ended. This option allows you to inter-face with standard LVTTL (TTL for Virtexbuild) enabling this module to communicatewith other systems that do not support LVDS.

If you need 5-V tolerance or support for thecurrent Xilinx DRL technologies such as JBitsand XVPI, you can also specify a standard Virtexdevice, instead of a Virtex-E device.

Conclusion

The easy to use Ballyderl DIME module allowsyou to configure designs in minutes, and pro-vides high performance reconfigurable comput-ing and data processing with unrivalled efficiency.

New Products - High Speed DRL

5 Gbytes/sec digital I/O DIME Module now supports DRL technologies.

by Derek McAulay, Design Engineer, Nallatech Ltd, d.mcaulay@nallatech.com

LVDS or Single Ended

Driver Selection

LVDS or Single Ended

Receiver Selection

Data Out

Clock Clock

Data In

16M x 32 (64Mbytes)SDRAM

16M x 32 (64Mbytes)SDRAM

180 I/O

DRL Bus

Data Out Data In

32 32

4

DIM

E M

odul

eI/O

Status LEDs

Virtex / VirtexE FPGA

XCV600 up to

XCV2000E

For more information on Ballyderl, or other DIME products,contact Nallatech at: www.nallatech.com.

Other DIME Modules include:Ballyblue: Dual 2 million VirtexE DIME Module.Ballyvision: Analog video I/O DIME Module.Ballysharc: VirtexE, Dual Hammerhead SHARC DSP DIME Module.Ballyriff: 4 Channel 105MSPs 12bit ADCs, VirtexE DIME Module.

Figure 1 - Ballyderl block diagram.

New Products - Support

34

PCI 64/66 Design Kit

by Per Holmberg, Product Marketing Manager IP Solutions,Xilinx, per.holmberg@xilinx.com

Xilinx recently announced The Real 64/66PCI™ Design Kit, which includes accessto the proven Xilinx LogiCORE PCI 64/66

and PCI 32/33 cores, a 3.3-V/5-V universal 64-bit/66-MHz PCI prototyping board, Windowsdriver development tools, and several PCIReference Designs. The kit provides the onlycomplete solution for developing 64-bit, 66-MHzfully compliant PCI add-in boards for the PC,server, and workstation markets.

When Xilinx introduced The Real64/66 PCI in March, last year, it wasthe industry’s first general-purpose64-bit, 66-MHz PCI solution. This newPCI standard has until now mainlybeen adopted by companies develop-ing embedded applications. However,with new high-performance PC moth-erboards entering the market withsupport for 64-bit/66-MHz PCI, add-inboard manufacturers for PCs, Servers,and Workstations started developingproducts using this new PCI standard.

With this design kit, Xilinx extendsits solution to include all toolsrequired to support this emergingmarket of high-performance PCs with

64/66 PCI capabilities. Not only will the Real64/66 PCI Design Kit accelerate your time-to-market, but it also addresses the emerging needfor concurrent support of 5-V PC motherboardsand the next generation, high-performance 3.3-VPC motherboards.

To provide a complete solution and industryleading expertise, Xilinx has partnered withCompuware, the leading provider of software

Includes a prototyping board, driver development tools,and reference designs.

New

driver development and debugging tools, andNallatech, a member of the Xilinx third-partyXPERTS consulting program, providing PCIdesign services and the prototyping board.

The NuMega SoftICE Driver Suite

With The Real 64/66 PCI design kit, you receivea production version of Compuware’s NuMegaSoftICE Driver Suite. These tools accelerate thedevelopment and debugging of Windows devicedrivers, offering a full-featured solution for basicdriver development and debugging in Windows2000, Windows NT, and Windows 95/98 plat-forms. A standard license for the Compuwaresuite is included.

“NuMega SoftICE Driver Suite addresses acritical need for driver developers seeking high-quality development tools to increase their pro-ductivity,” said Joe Wurm, vice president and labdirector for the NuMega product line. “Thisrelease of the SoftICE Driver Suite enhances thedebugging and testing capabilities of the suite tofully encompass Windows 2000 driver develop-

ment. The SoftICE Driver Suite is a key elementof Compuware’s comprehensive strategy forhelping corporations deploy reliable Windowsdevice drivers.”

The PCI64 prototyping board

The Nallatech 64/66 PCI prototyping boardallows you to quickly evaluate the performanceof the Xilinx core in your system. In addition, the

3535

“Not only will the Real 64/66

PCI Design Kit accelerate your

time-to-market, but it also

addresses the emerging need

for concurrent support of 5-V PC

motherboards and the next gen-

eration, high-performance 3.3-V

PC motherboards.”

board demonstrateshow to build a univer-sal PCI board thatautomatically changesthe I/O characteristicsas needed to supportboth 3.3V and 5V PCI.Additionally, this boardshows how to meetthe stringent PCI speci-fication requirementsfor sub-100ms PCIreset timing withFPGAs.

An SDRAM interface to a Small OutlineDIMM (dual inline memory module), using theintegrated digital Delay Locked Loops of theXilinx Virtex FPGAs, demonstrates how to builda single-chip solution. With Virtex FPGAs, board-level DLLs are not required because the FPGAcan handle clock management, both on and offthe chip.

The Xilinx Real64/66 PCI Core

The Real 64/66 PCIcore from Xilinxenables you to designfully compliant PCI businterface systems,using Xilinx Smart-IPtechnology to guaran-tee the critical mini-mum, maximum, andhold timing requiredfor a true zero wait-state burst operationat 66 MHz. PCI v2.2

compliance is verifiedthrough hardware test-ing, device characteri-zation, and regressiontesting using the Xilinxinternal test bench thatsimulates more thansix million uniquecombinations of PCItransactions.

With its LogiCOREofferings, Xilinx hasenabled thousands of

32-bit and 64-bit PCI designs. This translates tomore than twice the revenue generated by theleading chip-set competitor. This is a significantmilestone that underscores the inherent benefitsof standard FPGAs on the most advanced pro-cesses. More important, The Real 64/66 PCIsolution allows you to integrate very high-perfor-mance, high-density 66-MHz PCI systems tai-lored to your specific needs.

Conclusion

It’s now easier thanever to design fullycompliant PCI-compat-ible systems. The PCIdesign kit with theNallatech prototypingboard and Compuwaresoftware is availablenow for $17,995 fromXilinx distributors. Formore information seewww.xilinx.com/pci.

About Compuware

With trailing 12-month revenues of more than $2 billion,

Compuware is a world leader in the practical implementation

of enterprise and e-commerce solutions. Compuware produc-

tivity solutions help 14,000 of the world’s largest corpora-

tions more efficiently maintain and enhance their most criti-

cal business applications. Providing immediate and measur-

able return on information technology investments,

Compuware products and services improve quality, lower

costs, and increase the speed at which systems can be devel-

oped, implemented and supported. Compuware employs

more than 15,000 information technology professionals

worldwide. For more information about Compuware, please

contact the corporate offices at 800-521-9353. You may also

visit Compuware on the World Wide Web at www.com-

puware.com. For information on Compuware’s SoftICE Driver

Suite please visit www.compuware.com/drivercentral.

36

About Nallatech

Nallatech is a leading electronic systems design company

that specializes in the development of highly complex DSP

and image processing systems for its customers. Nallatech

has also developed a modular approach to the construction

of highly complex systems using their innovative DIME (DSP

and Image processing Module for Enhanced FPGAs)

Products. Founded in 1993 and headquartered in Scotland,

Nallatech is bringing the advantages of the FPGA directly to

system engineers, allowing them to construct complex sys-

tems with a minimum of risk. DIME and Xilinx have finally

brought to hardware design the flexibility that software has

enjoyed for many years. For more information, visit the

Nallatech website at http://www.nallatech.com.

The Configurator from Configurator, Inc.,shown in Figure 1, provides a large FLASHmemory to store configurations for all of

the Xilinx FPGAs. It also includes an intelligentlink to your PC along with control software, soyou get enough storage space for multipledevices and multiple configurations with fast andeasy file management.

The Configurator supports all XC3000,XC4000, XC5000, Spartan, and Virtex deviceswith 8-, 16-, and 32-Megabit models available.The Configurator is programmable in-systemusing a Windows application program communi-cating over a 115k Baud serial port connection.It’s available now in a 32-pin DIP package foreasy integration into circuit card designs.

Memory Allocation

The Configurator allocates each output of theFLASH memory to a Xilinx FPGA, permitting upto eight FPGAs to be configured at once. If fewerthan eight FPGAs are to be configured, theConfigurator will automatically use more thanone data bit for storage for each FPGA, therebyincreasing the bitstream file storage space avail-able.

The selection of a Configurator model’s flashmemory size is based on the number of FPGAsto be configured and the size of each FPGAs bit-stream file. For example, a Configurator-8M (8megabits) can configure up to eight FPGAs witheach one having a maximum bitstream filelength of less than one megabit. However thesame Configurator-8M will automatically inter-leave bits of data so that if only four FPGAs needto be configured on the card, the maximum bit-stream file length is increased to two megabitseach.

Table 1 illustrates a subset of the storagecapabilities provided by a single Configurator. Touse this table:

1. In the left hand column select the largestFPGA you will be configuring.

2. Go right across the top selecting the numberof FPGAs and the number of configurationplanes.

37

New Products - Support

MASS STORAGE

by Greg Clifford, Marketing, Configurator, Inc.,clifford@fpgaConfigurator.com

for XilinxFPGAConfiguration

The Configurator is a micro-controller with Flash memory,allowing configuration of up to eight FPGAs in parallel.

Figure 1 - Configurator 32-pin DIP module.

3. Where row and column intersect is theConfigurator model you will need. If you havean odd number of FPGAs to configure or anodd number of configuration planes round upto the next power of two.

For example, if you have four FPGAs to con-figure, the largest of which is a Virtex XCV50,and you want three different configurationplanes, go down the left side until you get to theXCV50 row then across to the “4 FPGAs/ 4planes” column indicating that a Configurator-8M would satisfy your requirements.

Configuration Control

The Configurator adds on-board configurationcontrol to FPGA designs by providing the capa-bility to store custom configuration informationin the flash memory. The date, path, and file-name are stored automatically and user informa-tion such as design version, firmware numbers,and so on, may be stored with each bitstreamfile and are user configurable. This configurationinformation is especially helpful during FPGAdevelopment to identify revisions of bitstreamfiles.

The Configurator also minimizes fieldupgrade costs by providing in-system re-pro-grammability, a simple RS-232 serial port inter-face, and configuration information to help fieldservice personnel determine and update therequired bitstream file changes.

Internet Reconfigurable Logic

The Windows GUI communicates with theConfigurator module using ASCII character pro-tocols providing an easy method of performingremote bitstream file updates. The formatted bit-stream files are also text files that are easily dis-tributed. The communication link could be anInternet connection permitting hardware updatesfrom anywhere in the world.

Windows User Interface

The Configurator Windows GUI as shown in

Figure 2 runs on Windows 95/98/NT systemsand provides an easy interface to theConfigurator. To download new bitstream files tothe Configurator, connect to a serial port, selectthe .bit files, then select “Program.” The GUI willdownload the configuration files at 115K bits persecond, saving the data to FLASH memory. Forexample, if an additional signal probe is neededduring debugging, the power may be turned off,the probe attached, and when the power isturned back on the Configurator module will re-configure the FPGAs without the need foranother download.

Re-configurable Computing Applications

The Configurator has the ability to store configu-ration files in up to eight different planes. Eachplane can have one configuration file for up toeight FPGAs. The planes are selectable from thehost card’s hardware to support re-configurablelogic applications. This feature permits multiple

38

Figure 3 - Configurator example schematic.

Figure 2 - Windows configurator user interface.

functions to be implemented for the design uti-lizing the same hardware.

For example, one plane could have a built-inself-test function, while the next plane mighthave a data process function, and the third planebeing a data compression function. Having mul-tiple planes simplifies the design since all of thefunctions do not need to be accommodated in asingle FPGA design and a smaller and fasterFPGA size is realized. The Configurator has threededicated input pins to allow for the configura-tion plane selection, the planes are selected bysetting the RECONFIG[2:0] inputs to the desiredplane followed by resetting the device.

Configurator Integration Options

Adding the Configurator to your designs is easy,and even existing designs can use a Configuratorif the design has an Xchecker cable connection.The Configurator typically replaces both serialPROMs and the Xchecker cable connections on aboard for up to eight FPGAs. The sample

schematic in Figure 3 shows a Configurator con-nected to Virtex, XC4000, and XC3000 FPGAs.

You can buy a self-contained module toinstall on each board or the Configurator can beintegrated into your board design by purchasingjust the pre-programmed Configurator micro-controller. The Configurator Starter Kit is $459,which includes a Configurator Module, a serialinterface cable, sample schematics and theConfigurator Windows GUI. Individual 32-pin DIPmodules are available in 8-, 16- and 32-M bitmodels and pre-programmed micro-controllersare available for higher volume applications.

Conclusion

The Configurator makes it very easy to programXilinx FPGAs and it supports the Xilinx InternetReconfigurable Logic capability allowing you toremotely reconfigure Xilinx FPGAs, over theInternet, anywhere in the world.

39

For further information, visit the Configurator, Inc. website atwww.fpgaConfigurator.com.

Table 1 - Configurator storage capability.

40

Applications -Virtex

Xilinx FPGAs have always had combina-tions of Look-up Tables (LUTs) and flip-flops, combined into Configurable Logic

Blocks (CLBs). With the introduction of theXC4000 family, the Xilinx LUTs also have RAMand ROM capability. Now, with introduction ofthe new Virtex architecture, LUTs can also beused as shift registers.

The Virtex LUT

The Virtex LUTs have four inputs and one out-put, and can be used as RAM, ROM, or SerialShift Registers (SSRs):

• Used as a look-up table the LUT can con-tain (up to) any four-input function.

• Used as RAM or ROM the LUT can have a1X16-address configuration.

• Used as an SSR the LUT can be used as a16-bit shift register.

Creating Counters in LUTs

A counter, whether it’s binary, Johnson ring, orLFSR, is a sequence of repeating patterns. If youprogram that sequence into a set of Look-up

Tables, then you can easily create fast, simple,and large counters. Here are several examples.

A 4-Bit Binary Counter

A 4-bit binary counter has 16 possible stateswhich can be stored in a Look-up Table. Bycycling through the addresses you can generatethis binary counter pattern as shown in Figure 2.

When we initialize an SRL16 with these val-ues and cycle the shift register, the output willbehave as a counter. However, the shift registerwill be empty in 16 clock cycles so you need toconnect the input to the output to make thecounter repeat the cycle. It’s also possible to give

LOOK-UPTABLESThe Virtex Look-up Tables have some interestingcapabilities that allow you to create very fast andefficient designs.

by Marc Defossez, FAE, Xilinx BeNeLux,Marc.Defossez@xilinx.com

RAM16X15

DWE WCLKA0A1A2A3

DWE CLKA0A1A2A3

SRL16E

A0A1A2A3

O

O QLUT

ROM16X1

Figure 1 - LUTs used as RAM, ROM, or SSR.

Using the Virtex

41

this counter a terminal count. To do this, use thecarry chain as a wide AND gate and combine allthe outputs to create the desired terminal count,as shown in Figure 3.

Using four LUTs, configured as an SRL16shift register, can make a small 4-bit counterwith a full and repeatable sequence.

You can also make a counter or sequencerthat generates any count sequence you like, asshown in Figure 4. By initializing the SRL16 witha sequence, so that the counter starts countingat a specific value and stops at another value,then you only need to set the address of theSRL16 to the correct number of stages.

SRL3

SRL2

SRL1

SRL0

Vcc

0 1

0 1

0 1

0 1

TC

Figure 3 - Creating a terminal count.

LUT

LUT

LUT

LUT

LUT

LUT

0

1

2

3

4

5

TC

Carry Chain

Figure 2 - 4-bit binary count sequence.

Figure 4 - A 6-bit counter.

Binary Counting Sequence

0000 00001 10010 20011 30100 40101 50110 60111 71000 81001 91010 A 101011 B 111100 C 121101 D 131110 E 141111 F 15

00

00

00

01

00

10

00

11

01

00

01

01

01

10

01

11

10

00

10

01

10

10

10

11

11

00

11

01

11

10

11

11

When we turn this counting sequence, then we get:

A LUT, RAM or SRL is 1 bit by 16.

Here we have i4 bits by 16.

So we have 4 LUTs that can be INITialized withhard coded values:

LUT 3 gets 00FF = Q3LUT 2 gets 0F0F = Q2LUT 1 gets 3333 = Q1LUT 0 gets 5555 = Q0

TC TC

42

A 5-Bit Binary Counter

To create a 5-bit counter, initialize the extra LUT(SRL16) to “0” and feed it’s output back to it’sinput via an inverter. Then for the first 16 cyclesthe LUT/SRL will give a zero at the output, whileloading a “1” into the SRL/LUT. For the next 16cycles the counter will produce a “1” as the highorder bit.

A 6-Bit Binary Counter

To create a 6-bit counter, first create a 5-bitcounter as previously described. Then, to createthe sixth bit, initialize the LUT to all zeros.Connect the output of the SRL to it’s input via aninverter and then connect the enable of the SRLto the output of the previous bit, as shown inFigure 4.

The sequence for both upper bits will then beas follows:

1. Both upper bits will be “0.”

2. After 16 clock cycles, bit 5 will become a “1”and bit 6 stays “0.”

Figure 6 - Example of an LFSR counter.

D Q D Q D Q D Q D Q D Q D Q

D QD QD QD Q

D Q

A

D Q

A

D Q

A

D Q

A

1 2 3 4 20 21 22 23

39 55 56 57 64 65 66

F F 7

56576566

D

CEC

O

SRL16E

D

CEC

O

SRL16E

D

CEC

O

SRL16E

D

CEC

O

SRL16E

D

CEC

O

SRL16E

D

CEC

O

SRL16E

L

TC

Carry ChainFigure 5 - A loadable counter.

TC

3. The LUT of bit 6 will be enabled for the next16 clock cycles.

4. The LUT of bit 6 will output 16 zeros and thenload a “1.” Bit 5 will load “0” while the outputis “1.”

5. After 16 clock cycles, bit 5 will become “0”and bit 6 will be a “1.”

The simulated counter is shown in Figure 7and Figure 8.

A Loadable Counter

Figure 5 shows how to create a loadablecounter. A load operation will take 16 clock

cycles, and you can load the counter while it iscounting.

A Large LFSR Counter

An LFSR counter is a shift register with it’s inputfed back (XORed) from the bits of the differentstuck states that can appear in the sequence. Inthe Virtex architecture we have the SRL16 ele-ments that represent 16 flip-flops, thus largeLFSR counters with only certain outputs of inter-est can be made efficiently.

43

Figure 7 - Simulated counter waveforms.

Figure 8 - Simulated counter waveforms, zoomed in.

For more information see Application note (Xapp052) on “EfficientShift Registers, LFSR counters, or see Xcell 35 article on “PseudoRandom Noise Generators.”

44

The PROBE capability within theFPGA_Editor application (included in allXilinx Foundation Series and Xilinx

Alliance Series development systems), allowsyou to quickly identify and route any internal sig-nal to an unused I/O pin. Once routed to the pin,you can then view that signal’s real-time activityusing normal lab test equipment such aslogic/state analyzers and oscilloscopes. PROBEis very easy to use and it makes your lab debugcycles as quick and efficient as possible.

PROBE gives you a simple, natural way toobserve any internal signals in your design andanalyze their switching behavior with essentiallyno impact on design performance. The signalsare viewed in real-time, so you are sure to havethe most accurate picture possible on how yourdesign is functioning in it’s actual operating formand environment.

Your HDL design effort only needs to focuson the device’s primary intended functionbecause all of PROBE’s power can be accessedautomatically during the lab-debug phase of yourproject design cycle—there is no need to guessbefore lab debugging which signals you wish toanalyze. PROBE easily guides you through thedebug phase, so you can pick which signals needto be observed at any time during the process,and changes to the signal list can be madeinstantaneously.

Using PROBE

The PROBE function can be used either in man-ual or automatic mode.

Manual Mode

As shown in Figure 1, using PROBE is as simpleas loading the design into FPGA_Editor andclicking on the “PROBES” button on the UserToolbar.

Using PROBE

by Davin Lim, Software Technical Marketing Engineer,Xilinx, Davin.Lim@xilinx.com

Application - Software

You can easily view internal signals byrouting them to device pins.

EFFICIENTDEBUGGING

45

Once the PROBES dialog box appears, all youneed to do is pick the signal to be analyzed andassign it to an unused I/O pin, as shown belowin Figure 2.

This is the most commonly used modebecause most of the time you will know whichI/O pins are best to use for connection to exter-nal logic analysis equipment. Usually, and espe-

cially in cases where ball-grid array(BGA) packages are involved, you willconnect test points on your PC board tospecific FPGA device pins. In such cases,you’ll know exactly which unused I/Opins are most convenient to use forPROBE connections, and the manualmode is the best choice.

When reserving the I/O pins youwish to use as test points, you canincrease the effectiveness of PROBE byselecting at least one I/O pin on eachside of the FPGA (as viewed in theFloorplanner or FPGA Editor). This way,no matter where on the FPGA the inter-nal signal to be probed exists, there will

be a test I/O pin located nearby.

Automatic Mode

In automatic mode, PROBE automaticallychooses an unused I/O pin that will incur theleast amount of routing delay when connected tothe signal you want to monitor. To use the auto-matic mode, simply select “Automatic” under the“Method” selection box. Once the signal, pin list,and pin selection method have been chosen,pressing the OK button will complete the PROBEoperation.

Displaying PROBE Results

The Probe list window lists all signals that havebeen assigned to PROBE I/O pins. This list canbe sorted by any of the headings simply by click-ing on the desired column’s heading. It will oftenbe important for you to know how much routingdelay is incurred to route the signal to the I/Opin. This delay amount is listed in the PROBE list

Figure 2 - Assigning signals to probes.

Figure 1 - How to access PROBE.

Step 3:AssignPROBE name

Step 4:Choose signal toPROBE

Step 5:Assign to unusedI/O pin

46

under the “Slack” heading. In the exampleshown in Figure 3, there is 3.6ns of routing delayto route the signal “mult4/ADDER_01” to theexternal I/O pin.

Controlling Probe Execution Time andRouting Delay

If your design has timing constraints which spec-ify timing requirements for items such as clockperiods and I/O timing, the default routing algo-

rithms used by PROBE will account forthose timing specifications and work toensure that all timing constraints are stillmet after the probe signal has beeninserted. FPGA_Editor accomplishes this byreading timing constraints from thedesign.pcf physical constraints file.

The amount of route delay on theactual probed signals is often not critical tothe debug task at hand. As long as youknow what the route delay is, you canaccount for that amount in the analysisprocess, and therefore it may not be neces-

sary to always optimize the route delay toachieve minimum delay. If this is the case for thesignals you are probing in your design, you cansignificantly quicken the PROBE execution pro-cess by simply ensuring that the .pcf file is notread in when the design is originally loaded intoFPGA_Editor. This is accomplished by makingsure the Physical Constraints File field is leftblank, when completing the File->Open dialogbox as shown in Figure 4.

Conclusion

To quickly and effectively get through thelab-debug phase of your FPGA design, youwill need tools that are fast, easy to use,and work with a minimum of fuss. ThePROBE capability within the FPGA_Editorapplication directly addresses this need.PROBE provides you with direct access tothe internal signals of your design, with theabsolute minimum impact on the design’sperformance and resource utilization.

Figure 3 - Routing delay of probed signal.

Speed up PROBErouting time byloading designwithout PhysicalConstraints File(.pcf).

Make sure thisfield is blank.

Figure 4 - Omit the PCF file to speed routing times.

47

Applications - Software

LeonardoSpectrum is the FPGA Synthesis Tool

from Exemplar Logic, used to Synthesize RTL

HDL code and target Xilinx Virtex devices.

Using Attributes and VariablesLeonardoSpectrum’s optimization engine can be con-

trolled globally (using global optimization variables) or

at the netlist level (using attributes).

Global optimization variables affect the optimiza-

tion of every block in the design. The lut_max_fanout

variable provides a good example. If this is set to a

value of 12 then all nets will be optimized with a

fanout no greater than 12.

Attributes provide a way to make a modification

to a specific net, cell, or instance. An attribute is a

property assigned to an object, which affects the opti-

mization of only that object. You can set attributes

prior to RTL synthesis by using a standard VHDL

attribute statement or Verilog attribute comment

statement as follows:

• Setting Attributes in Verilog://Exemplar attribute <signal name> <attribute name> <attribute value>

• Setting Attributes in VHDL:ATTRIBUTE <attribute name> : <attribute VHDL type>;ATTRIBUTE <attribute name> of <signal name> :signal is <attribute value>;

Attributes can also be set on objects after synthe-

sis using the set_attribute command as follows:usage : “set_attribute” [<object_list>] <netlist object><attribute name> <value>

For example:set_attribute u1 -instance -name dont_touch -value TRUE

Controlling Clock Buffers

Virtex and VirtexE FPGAs contain 4 BUFG cells per

device, which are primarily used to drive clock lines.

Often, all of these cells are not required for primary

clocks. LeonardoSpectrum will automatically identify

high fanout internal clocks and insert all unused

global buffers into those nets. This functionality is

enabled by default and controlled by the global vari-

able:> set insert_bufs_for_internal_clock true

There may be situations where you want to force

a BUFG cell onto a net or prevent the automatic

buffering of a high-fanout net. Attributes can be used

in both of these cases to control optimization.

Use the following command to force a BUFGcell into an internal net:

> set_attribute netname -net -name PAD -value bufg

Use the following command to prevent automatic

BUFG insertion on particular net:> Set_attribute netname -net -name NOBUF -value TRUE

Controlling Virtex Low Skew Lines

If high-fanout clock nets still exist after all the clock

buffers have been exhausted, LeonardoSpectrum will

use the Virtex secondary global lines to minimize

skew by applying an attribute called “MAXSKEW” to

each individual, high-fanout clock net. You can

instruct LeonardoSpectrum to perform this operation

automatically on the entire design by setting the sys-

tem variable virtex_apply_maxskew to a specified

by Tom Hill, Technical Marketing Manager, Exemplar Logic, tom.hill@exemplar.com

How to Control Virtex DesignOptimization

USING VARIABLES AND ATTRIBUTES

With Exemplar’s LeonardoSpectrum, you can easilycontrol every aspect of your design.

Argument Set_attribute Switch Description

Netlist object -port | -net | -instance Indicates the type of netlist object

Attribute Name -name Name of the attribute

Attribute Value -value Value of the attribute

Table 1 - set_attribute command arguments.

48

maximum skew value as follows:> Set virtex_apply_maxskew 7

The “maxskew” attributes can be used to specify a

maximum skew on a particular net. Use the following

command to limit skew on a particular net:> Set_attribute <internal netname> -net -name MAXSKEW -value 7

If you set a very low skew value, one that the

Xilinx Alliance Series software is unable to meet, then

an error will be issued during place and route. For that

reason it is important not to over constrain the skew

value.

Controlling Fanout

Fanout, which is usually controlled globally, is set to a

default of 64 in LeonardoSpectrum, for Virtex devices.

This is generous but usually gives good results. If tim-

ing is difficult to meet in the place and route environ-

ment, especially if large routing delays are the culprit,

then you can modify design fanout in certain areas.

Using the lut_max_fanout attribute, LeonardoSpectrum

allows you to override a global fanout specification

with a unique value for a particular block or net. Net

fanout can be specified on a global basis using the fol-

lowing command:> set lut_max_fanout 12

Use the following command to redefine the fanout

on a specific net from 64 (default) to 16:> Set_attribute mynetname -net -name lut_max_fanout -value 16

Controlling IOB Registers

LeonardoSpectrum, by default, does not optimize reg-

isters to the IOB. When loading the Virtex technology,

you are presented with an option to “Map IOB

Registers,” which will set the global optimization

variable:> set virtex_map_iob_registers TRUE

Once set this variable will instruct

LeonardoSpectrum to pull all possible registers into

the Virtex IOB blocks. When a single register is used

to drive more than 1 output port LeonardoSpectrum

will replicate that register once for each additional

port. Often, however, users wish to pull only a few

select registers into the IOB. This can be accomplished

by assigning an attribute called “IOB” to the particular

register instance.

Use the following command to force a register

with an instance name called “reg_state(7)” into the

IOB: set_attribute reg_state(7) -instance -name IOB -value TRUE

You can also use wildcards “*” to set all the regis-

ters of a bus at once. For example: “reg_state*”

Controlling Block RAM

Both global variables and attributes can be used to

control block RAM inferencing. When developing a

single module of a larger device you may wish to allo-

cate all the block RAM resources to another block. In

this case, using the global variable to disable the block

RAM inference makes the most sense. You can do this

by using the following command:> set extract_ram FALSE

When block RAM resources start to run low, you

may choose to disable block RAM inferencing on a

section of the design. You can accomplish this by

assigning the block_ram attribute to the storage signal

used during the RTL RAM inference. You can do this in

the RTL code by setting an attribute on the memory

signal.Verilog Example:Reg [7:0] mem[63:0]//Exemplar attribute mem block_ram FALSEVHDL Example:TYPE mem_type IS ARRAY 0 TO 256 OF std_logic_vector (15 DOWNTO 0);SIGNAL mem : mem_type;ATTRIBUTE block_ram : Boolean;ATTRIBUTE block_ram of mem : signal is TRUE;

The block_ram attribute can also be applied to the

“mem” signal, after synthesis, from the

LeonardoSpectrum command line.

LeonardoSpectrum’s design browser can help you

identify correct signal pathnames for hierarchical

blocks. For flat designs the signal name alone would

be sufficient. Below is an example of using the

set_attribute command to disable RAM inferencing on

a memory signal “mem” that resides within a sub-

block of the design “blockA:”> Set_attribute .work.blockA.rtl.mem* -net -name block_ram -value false

ConclusionWith LeonardoSpectrum, it’s easy to optimize Virtex

FPGA designs. For more information about

LeonardoSpectrum, see www.exemplar.com.

The phenomenal success of the Internetand the universal adoption of the InternetProtocol (IP) are driving profound changes

in the telecommunications industry. Spring TideNetwork’s IP Service Switch 5000 creates a newservice layer for the public Internet Protocol net-work, and they chose eleven Xilinx FPGAs,including SpartanXL and Virtex devices, basedupon the strong set of development tools anddesign flexibility.

“We began working with Xilinx as soon aswe assembled our team. As a start-up, time tomarket was our overriding concern. Workingwith Xilinx was a very simple decision for usbecause Xilinx offered tremendous gate densityand speed,” said Steve Akers, co-founder andchief technology officer. “As a result, we wereable to leverage their product to achieve ourdesign objectives while avoiding the risk associ-ated with an ambitious ASIC project.”

“For our company, it was critical that we getto market in a timely fashion. Embarking on anambitious ASIC program would have introducedtoo much risk to our plan,” said Bob Sullebarger,vice president of marketing for Spring Tide.“We’ve seen several companies make the big bet

on ASIC science projects only to come up emptyand disappoint their investors.”

About Spring Tide

Spring Tide switches are designed to create dedi-cated, secure tunnels between users, ondemand, automatically setting up and tearingdown point-to-point connections as needed.They are the only carrier-class, “any-to-any” data services tunnel switchescapable of full service delivery atline speed. In addition, SpringTide’s hardware and software-

49

Success Story

The Virtex devices are already proving to our customers the time-saving advantages that these FPGAs bring to their design cycle.

by Tamara Snowden, Public Relations, Xilinx, tamaras@xilinx.com

Internet Protocol

SERVICE

“Working with Xilinx was a very sim-

ple decision for us because Xilinx

offered tremendous gate density and

speed... As a result, we were able to

leverage their product to achieve our

design objectives...”

Spring Tide Uses Xilinx FPGAs for a New

based intelligence gives eachflow the service it requires,such as filtering, tagging, clas-sification, queuing, andaddress translation.

The Spring Tide switch’sarchitecture features dedi-cated processors for handlingthe functions of flow classifi-cation and queuing; packetforwarding, routing and ses-sion management, encryption and compression,and key generation. A fully configured IP ServiceSwitch 5000 contains more than one hundredspecial and general-purpose processors, as wellas hundreds of megabytes of memory for contextand state information.

The 5000 processes as many as 100,000simultaneous secure customer sessions in a ser-vice provider’s point of presence, without sacri-ficing Quality of Service or performance goals.Competing switches can process and track onlya small fraction of that number. The 5000switches all flows at line speed, regardless ofany value-added processing (such as encryp-tion), with less than 50 microseconds latency.

The IP Service Switch 5000 contains elevenXilinx devices; 500k Virtex devices are installedin two locations: as a front-end packet schedulerto feed streams to the dual PowerPC processorson the tunnel card, and as a scheduler for thesecurity subsystem. “We went with Xilinx forseveral reasons. First, Xilinx offered thestrongest set of development tools available.Second, Xilinx had the highest device speed,which helps us from a performance perspective.In addition, Xilinx products offered us a great

deal of design flexibility as wearchitected our product,” saidAkers.

Xilinx Technology

The Virtex technology is thecombination of leading-edgeprocess technology, a system-level feature set, and break-through software technology.To build a multi-million-gate

FPGA, specific design optimization of the tech-nology was necessary. The Virtex architecturerepresents aggressive use of an advanced 0.22-micron process to pack millions of gates with fullutilization of five metal layers for an abundanceof high performance routing tracks. The architec-ture is also easily scalable from 50,000 to onemillion system gates to offer the robust featureset across a wide range of densities in ninedevices.

“The Xilinx parts allowed us to optimize theperformance of our system by allowing us to runat 66 MHz,” said Akers. “The overall design isvery flexible and only Xilinx could give us adevice capability supporting between 500,000and 3.2 million gates.”

“The Virtex devices are already proving toour customers the time-saving advantages thatthese FPGAs bring to their design cycle. The den-sity and performance levels, combined with thepopular system-level features and industry-lead-ing FPGA price points make Virtex-E FPGAs aneven more compelling alternative to ASICs,” saidWim Roelandts, Xilinx president and CEO.

50

About Spring Tide

Spring Tide was founded by Stephen

Collins, former vice president of marketing

at StarBurst Communications, and Steve

Akers, former CTO and vice president of

advanced technology development at Shiva

Corporation. Led by President and CEO

Allan Wallack, the company has assembled

a highly experienced product development

team with engineering talent drawn from

many of the leading networking and com-

puter companies in the Boston area. For

more information, visit the Spring Tide web-

site at www.springtidenet.com.

When VisiCom needed a high capacity,high performance FPGA for a real-time video processing board, they

chose the Virtex series FPGAs from Xilinx. Since1997, VisiCom has specialized in using FPGAs torapidly deploy customer-specific real-time imageand video processing systems for a variety ofapplications, including semiconductor processequipment, medical imaging, scientific imaging,factory floor automation and defense/aerospaceelectronics.

About VisiCom

VisiCom’s FPGA-based approach combines thereal-time performance of hardware-acceleratedalgorithms with the ability to modify or upgradethe algorithm without physically changing thehardware. This provides a means to reconfigurehardware and software quickly and efficiently tosuit specific customer requirements, resulting inreduced time to market, significant cost savings,and better lifecycle support. In addition, the useof FPGA technology avoids the non-recurringengineering costs usually associated with fabri-cating ASICs, while still providing most, if not all,of the performance features.

“With the FPGAs used in our earlier projects,we found we were spending a great deal of time‘hand-crafting’ algorithms to make them fit inthe part and achieve timing closure,” stated RonHawkins, chief operating officer of VisiCom’sComputer Products Division. “A lot of effort fromour most experienced engineers was required,tying up valuable engineering resources anddelaying customer deliveries. We realized thiswas unacceptable to us and our customers, andsomething had to change.” VisiCom’s engineersneeded a solution that would allow them tospend more time on design and simulation andless on post route and hardware debug.

51

Success Story

by Tamara Snowden, Public Relations, Xilinx, tamaras@xilinx.com

The combination of the Virtex hard-ware, associated software tools, andengineering process improvements haveproven to be a great success.

Figure 1 - Visicom board.

ImageProcessing

VisiCom Uses Xilinx FPGAs for a Reconfigurable

Module

52

The opportunity to change occurred whenVisiCom was selected to design a customembedded, reconfigurable image processingmodule for a medical imaging system. The sys-tem in question had demanding requirements; itcalled for processing full bandwidth video(“4:4:4” luminance and chrominance bands) inreal-time using several image processing andancillary operations. The processing require-ments included color space conversion,enhancement (convolution), and affine transfor-mation (rotation, scaling, and translation). These

operations represented a significantly higherdegree of integration on silicon than had beenpreviously attempted by VisiCom engineers. Inaddition, the new module was replacing anexisting module that had become obsolete. Thenew module needed to accommodate specificsize and power constraints.

Using the Virtex Series

VisiCom’s engineers chose the largest capacityFPGA available from Xilinx, the million-gateVirtex series, as their solution. Virtex providesmore gates and routing resources, making it eas-ier to achieve timing closure with the synthesistools available. “We bet on two things,” contin-ued Hawkins.

“First, we bet that Moore’s Law would applyto FPGAs, that equivalent gate counts wouldcontinue to increase rapidly, with the cost pergate declining over time. Therefore, we con-cluded that even if the target part did not meetour cost requirements, it would by the time wefielded the product. This meant we could select apart that had plenty of resources to meet ourneeds and still have confidence that our cost tar-gets in production could be met.”

“Second, we bet that the EDA tool vendorswould continue to improve their products toachieve optimum utilization and routing withinFPGAs. We decided that the problem of optimallysynthesizing, placing and routing logic was aproblem for the tool vendors to solve, not us.This assumption meant we could devote agreater percentage of effort to analyzing ourapplication problem and designing a solution,and spend less time getting it to work in thepart. We relied on the EDA tools to handlethis, permitting better use of our engi-neering resources to focus on solvingthe application problem at hand.”

These assumptions proved cor-rect. VisiCom engineers con-verted from schematic design

VisiCom’s FPGA-based

approach....provides a means to

reconfigure hardware and soft-

ware quickly and efficiently to suit

specific customer requirements,

resulting in reduced time to mar-

ket, significant cost savings, and

better lifecycle support.

53

capture to VHSIC Hardware DescriptionLanguage (VHDL). The imaging algorithmdesigns had to be more abstract, modular, andreusable, to meet time-to-market constraints andsupport reuse in future designs. The software-like properties afforded by VHDL, such as encap-sulation and parameterization, offered signifi-cant advantages relative to schematic capture.The support in VHDL for the creation of designlibraries and reusable components was alsoessential to VisiCom’s strategy for rapidly fieldingfuture FPGA-based imaging systems to meet spe-cific customer requirements.

The company’s engineers also placed moreemphasis on establishing a formal designmethodology to guide the work effort from anal-ysis and high level design of the imaging algo-rithm, through VHDL coding, and ultimately, syn-thesis into the Virtex part. The software toolsavailable for the Xilinx Virtex series comple-mented this methodology and the use of VHDL.VisiCom integrated a high-level signal process-ing and analysis tool, MATLAB(tm) fromMathWorks, into the design flow, creating aframework for analyzing and verifying the imag-ing algorithms before beginning VHDL coding.

Extensive use was made of VHDL testbenches for thorough simulation and verificationof the design after it was committed to VHDL. Aprocedure was established for processing videofields with both the MATLAB and VHDL simula-tions, and comparing the results to ensureproper implementation. The methodology alsoincludes use of post-route simulation to ensuretiming closure. As a result of using MATLAB,VHDL, and extensive simulation, relatively littletime was spent debugging the physical hard-ware.

Another benefit of using the Virtex serieswas the high number of usable I/O pins. Thisfeature permitted VisiCom engineers to lock theFPGA pinout early in the project, so the physicalboard design and fabrication could proceed con-currently with the VHDL coding of the imagingalgorithms. The end result was the imagingboard was ready and waiting upon completion ofthe fully simulated imaging algorithm. “The engi-neers downloaded the bitstream, made a fewtweaks, and our imaging board was up and run-ning,” said Hawkins.

The combination of the Virtex hardware,associated software tools, and engineering pro-cess improvements have proven a great successin creating a solid product for use in the cus-tomer’s medical imaging system. VisiCom notonly achieved a faster time-to-market, but alsocompleted a real-time imaging project of signifi-cantly greater scope than had been previouslyattempted. As a basis for comparison, VisiComengineers estimated that seven commercial VLSIimaging chips and SRAM memory would havebeen required to achieve the same results at agreater cost than VisiCom’s solution, which useda single Xilinx XCV-200 part with SDRAM mem-ory.

In the customer’s medical imaging system, asingle Virtex part replaced multiple smallercapacity parts and provided a smaller footprint,lower power requirements, more capability, andlower overall cost. Based on their experienceswith this project, VisiCom’s design team is nowworking on their next real-time imaging designusing the Virtex-E architecture.

For more information, visit the VisiCom website at:www.visicom.com. Or, e-mail: sales@visicom.com

54

Column - Distribution

The market demands for shorter develop-ment cycles have had an effect on everyaspect of the industry, and distribution is

no exception. Over the past ten years distribu-tors have made significant investments in peopleand equipment in an effort to increase theirvalue to you. Their services have ranged fromsimple selection and sorting processes (for spe-cial tolerance parts), to building custom cableassemblies, to creating very sophisticated world-wide logistics programs. However, there are newand growing concerns related to today’s globaleconomy, and distributors are doing all they canto address these concerns.

Engineering Concerns for the Next Three Years

Because device and software technology haschanged dramatically over the past two years ithas been difficult for many customers to keepup. For example, during the “Design Con 2000”show in Santa Clara, California (last February),attendees were asked to list their primary con-cerns for the next three years; the following arethe top four:

• Getting their product to market ahead of thecompetition.

• Keeping up with current market demands.

• Obtaining needed technical expertise.

• Reducing inventory liability.

When asked how they were planning toaddress these concerns, the majority answered:“outsourcing.”

Distributors Become an Important Resource

Distributors still make money the old fashionedway, by selling components, but they also realizethey must now provide design services for theircustomers as well. Thus, they have invested mil-lions of dollars over the past years for facilities,state of the art software, support engineeringstaff, and Intellectual Property (IP) libraries, in aneffort to fill the design needs of their customers.

Xilinx is very fortunate because we havethree distributors that offer various levels ofdesign services and support: Avnet DesignServices, Memec Design Services, andNuHorizons Electronics. Their services includeon site customer seminars, Web-based seminars,training, and full design support from concept tocomplete turnkey solutions. Plus, they havedeveloped their own IP, reference designs, demoboards, and software kits to aid you with yourdesigns.

Conclusion

The Xilinx distributors have taken a very activerole in helping you keep product costs anddevelopment time to a minimum. If you wouldlike to know more about their services, visitthem on the Web at:

by Russ Sinagra, Distribution Marketing Manager HVG, russells@xilinx.com

Distributors continue to add new products and services to meet your needs.

Electronic Distributionis Changing with the Times

* Avnet Design Services: http://www.ads.avnet.com/

* Memec Design Services: www.memecdesign.com/

* NuHorizons Electronics: http://www.nuhorizons.com/

55

Column - Trade Shows

by Darby Mason-Merchant, Trade Show Manager, Xilinx,Inc., darby@xilinx.com

At the 37th Design AutomationConference, Club Xilinx will be the hotspot where you can see why FPGAs and

CPLDs are now center stage in digital design.Stop by and see our New Foundation ISE and3.1i software; an entire suite of design toolsdelivering the first design environment for ournew 10 million gate FPGAs. Also, check out theIP Center for everything you need for designreuse, and catch up on the amazing new devel-opments in Internet Reconfigurable Logic—upgradability via the Internet.

From satellites to cellular, networks to MP3s,routers to cable modems, Xilinx is everywhere.To find out more about Club Xilinx at DAC, go to:www.xilinx.com. For more information aboutXilinx Worldwide Trade Show Programs, pleasecontact one of the following Xilinx team members or see our website at: http://www.xil-inx.com/company/tradeshows.htm

• US Shows: Darby Mason-Merchant at:darby@xilinx.com or Jennifer Makin at:jenn@xilinx.com.

• European Shows: Andrea Fionda at:andrea.fionda@xilinx.com.

• Japanese Shows: Renji Mikami at:renji.mikami@xilinx.com.

• SouthEast Asian Shows: Mary Leung at:mary.leung@xilinx.com.

Xilinx is RED HOT and

E V E R Y W H E R Ewith 10 Million Gates on ISE...

Year 2000 Worldwide Xilinx Trade Show Schedules

Year 2000 North American Trade Show Schedule

May-July Embedded Computing Shows 2000 Southwestern, US

May 23-24 AC Developers Conference 2000 Santa Clara, CA

June 5-7 37th Design Automation Conference Los Angeles, CA

June 18-21 2000 ASEE Conference and Expo St. Louis, MO

June 21-23 WITI Technology Summit 2000 Santa Clara, CA

July 24-28 NSREC 2000 Reno, NV

Sept 6-7 Embedded Internet Conference 2000 San Jose, CA

Sept 26-28 MAPLD 2000 Laurel, MD

Oct 17-18 NCF / InfoVision 2000 Chicago, IL

Oct 18-21 Frontiers in Education 2000 Kansas City, MI

Year 2000 European Trade Show Schedule

Nov 2000 Electronica 2000 Munich, Germany

Year 2000 South East Asian Trade Show Schedule

March 20-21 IIC 2000 Beijing, China

March 23-24 IIC 2000 Guanzhou, China

March 27-28 IIC 2000 Shanghai, China

May 3-4 IIC Taipei Taipei, Taiwan

Oct 2000 EDA&T Hsinchu,Taiwan

Oct 2000 EDA&T Beijing, China

Year 2000 Japanese Trade Show Schedule

Jan 27-28 EDA Techno Fair 2000 Tokyo, Japan

Nov 2000 Micon System Tool Fair 2000 Tokyo, Japan

See Booth #3629 at DAC in Los Angeles, June 5-7th and see just how hot Xilinx is!

56

Column - Customer Education

What’sNew in TRAINING...Xilinx announces a new Advanced FPGA class.

Xilinx Customer Education offers a numberof public classes on-site training coursesand on-line E-Learning modules to help

you quickly learn the latest development tools.Our public courses are held at various locationsaround the world, and our E-Learning modulesare available online, via the Web. On-site classesare scheduled on request.

Online E-Learning Modules

Each E-Learning module is a one-hour sessionthat focuses on specific product solutions, andyou have the ability to ask questions of theinstructor, get answers, and collaborate withother students. Our E-Learning modules areavailable now as live, on-line sessions ($100.00USD per module) and will soon be available inrecorded versions ($70.00 USD per module). Newmodules are added frequently, so check our web-site to see the latest sessions and schedules.

New On-site Advanced FPGA Class

Our new on-site, two-day Advanced FPGA classis designed to help you:

• Get higher performance from your design.

• Optimize your code for the Virtex architecture.

• Take advantage of the more advanced capa-bilities of the implementation tools, such asMulti-pass Place and Route, and re-entrantrouting.

Course topics include:• Targeting Virtex-specific features with

Synopsys FPGA Express and SynplicitySynplify.

• Using advanced timing constraints.

• Using the FPGA Editor.

• Using Xflow.

• Creating Virtex memory applications.

Class size is limited, so enroll early. To learnmore about our classes or to register you cancontact the registrar at 877-XLX-CLASS (877-959-2527), or go to: http://www.support.xilinx.com /support/training/training.htm.

By Renne Ricciardi, Renne@Xilinx.com

Advanced FPGA Class ScheduleMay 9 & 10 San Jose, California

June 8 & 9 Boston, Mass

June 13 & 14 San Jose, California

July 12 & 13 Boston, Mass

July 26 & 27 San Jose, California

Aug 9 & 10 San Jose, California

August 24 & 25 Boston, Mass

Other ClassesJune 6 Alliance 3.1 Update Boston

June 7 Practical Design Boston

June 20-22 Intro to Verilog San Jose

June 27 Foundation ISE Design Entry San Jose

June 28-30 FPGA Design-ASIC User San Jose

July 10 Alliance 3.1 Update Boston

July 11 Practical Design Boston

July 18-20 Introduction to VHDL San Jose

July 18 PCI Basics Boston

July 19-20 Designing w/PCI Boston

57

Reference

Each Virtex family has its own unique fea-tures to meet different application require-ments. All devices have both distributed

RAM and block RAM, and between four andeight DLLs for efficient clock management.

• The Virtex family, consisting of devices thatrange from 50K up to 1 million logic gates,supports 17 I/O standards, and offers 5V PCIcompliance.

• The Virtex-E family offers the highest logicgate count available for any FPGA, rangingfrom 50K up to 3.2 million system gates, andsupports 20 I/O standards including LVPECL,LVDS, and Bus LVDS differential signaling.

• The Virtex-E Extended Memory family

consists of two devices that have a high RAM-to-logic gate ratio that is targeted for specificapplications such as gigabit per second net-work switches and high definition graphics.

The XC4000XLA family is part of the broadspectrum of Xilinx XC4000 FPGA series whichoffers the broadest choice of 5V, 3.3V, and 2.5Vdevices. The XC4000XLA family consists of eightmembers ranging from 30,000 to 180,000 systemgates and features patented SelectRAM dis-tributed RAM that can be used as single-port ordual-port memory.

Virtex Series and XC4000XLA FPGAs

See www.xilinx.com/__________________? for more information.

FPGA Product Selection Matrix

DEVICES KEY FEATURES

XC4013XLA 1368 13K 10K-30K 18K 24x24 576 1536 192 12/24 Y

XC4020XLA 1862 20K 13K-40K 25K 28x28 784 2016 205 12/24 Y

XC4028XLA 2432 28K 18K-50K 33K 32x32 1024 2560 256 12/24 Y

XC4036XLA 3078 36K 22K-65K 42K 36x36 1296 3168 288 12/24 Y

XC4044XLA 3800 44K 27K-80K 51K 40x40 1600 3840 320 12/24 Y

XC4052XLA 4598 52K 33K-100K 62K 44x44 1936 4576 352 12/24 Y

XC4062XLA 5472 62K 40K-130K 74K 48x48 2304 5376 384 12/24 Y

XC4085XLA 7448 85K 55K-180K 100K 56x56 3136 7168 448 12/24 Y

XCV50 1728 21K 34K-58K 56K 16x24 384 1536 180 2/24 Y

XCV100 2700 32K 72K-109K 78K 20x30 600 2400 180 2/24 Y

XCV150 3888 47K 93K-165K 102K 24x36 864 3456 260 2/24 Y

XCV200 5292 64K 146K-237K 130K 28x42 1176 4704 284 2/24 Y

XCV300 6912 83K 176K-323K 160K 32x48 1536 6144 316 2/24 Y

XCV400 10800 130K 282K-468K 230K 40x60 2400 9600 404 2/24 Y

XCV600 15552 187K 365K-661K 312K 48x72 3456 13824 512 2/24 Y

XCV800 21168 254K 511K-888K 406K 56x84 4704 18816 512 2/24 Y

XCV1000 27648 332K 622K-1,124K 512K 64x96 6144 24576 512 2/24 Y

XCV50E 1728 21K 47K-72K 88K 16x24 384 1536 176 2/24 Y

XCV100E 2700 32K 105K-128K 118K 20x30 600 2400 176 2/24 Y

XCV200E 5292 64K 215K-306K 186K 28x42 1176 4704 284 2/24 Y

XCV300E 6912 83K 254K-412K 224K 32x48 1536 6144 316 2/24 Y

XCV400E 10800 130K 413K-570K 310K 40x60 2400 9600 404 2/24 Y

XCV405E 10800 130K 1,068K-1,307K 710K 40x60 2400 9600 404 2/24 Y

XCV600E 15552 187K 679K-986K 504K 48x72 3456 13824 512 2/24 Y

XCV812E 21168 254K 2,569K-3,062K 1414K 56x84 4704 18816 556 2/24 Y

XCV1000E 27648 332K 1,146K-1,569K 768K 64x96 6144 24576 660 2/24 Y

XCV1600E 34992 420K 1,628K-2,189K 1062K 72x108 7776 31104 724 2/24 Y

XCV2000E 43200 518K 1,857K-2,542K 1240K 80x120 9600 38400 804 2/24 Y

XCV2600E 57132 686K 2,221K-3,264K 1530K 92x138 12696 50784 804 2/24 Y

XCV3200E 73008 876K 2,608K-4,074K 1846K 104x156 16224 64896 804 2/24 Y* I/Os are 5V tolerant** 5 Volt tolerant I/Os with external resistorX = Core and I/O voltageI/Os = I/O voltage supported

– – – X– – – X– – – X– – – X– – – X– – X *– – X *– – X *– – X *– – X *– X I/O *– X I/O *– X I/O *– X I/O *– X I/O *– – X *– – X *X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **X I/O I/O **

XC4000 Series:Density

Leadership/High Performance/

SelectRAMMemory

Virtex Family:Density/

PerformanceLeadershipBlockRAM

Distributed RAMSelectI/O

4 DLLs

Virtex-E Family:Density/

PerformanceLeadershipBlockRAM

Distributed RAMSelectI/O+

8 DLLsLVDS, BLVDS,

LVPECL

DENSITY FEATURES

Logi

c Ce

lls

Max

imum

Logi

c Ga

tes

Typi

cal S

yste

m

Gate

Ran

ge

Max

. RAM

Bits

CLB

Mat

rix

CLBs

Flip

-Flo

ps

Max

. I/O

Outp

ut D

rive

(mA)

PCI C

ompl

iant

1.8

Volt

2.5

Volt

3 Vo

lt

5 Vo

lt

FPGA Product Selection Matrix

Say hello to a new level of performance; theSpartan-II family now includes deviceswith over 200,000 system gates, and you

get 100,000 system gates for under $10, atspeeds of 200Mhz and beyond, giving you designflexibility that’s hard to beat. These low-pow-ered, 2.5-V devices feature I/Os that operate atup to 3.3V with full 5-V tolerance. Spartan-IIdevices also feature multiple Delay LockedLoops, on-chip RAM (block and distributed), andversatile I/O technology that supports over 16high-performance interface standards. You getall this in an FPGA that offers unlimited pro-grammability, and can even be upgraded in thefield, remotely, over any network.

Robust Feature Set• Flexible on-chip distributed and block

memory.

• Four digital Delay Locked Loops for efficientchip-level/board-level clock management.

• Select I/O Technology for interfacing with allmajor bus standards such as HSTL, GTL,SSTL, and so on.

• Full PCI compliance.

• System speeds over 200 MHz.

• Power management.

Extensive Design Support• Complete suite of design tools.

• Extensive core support.

• Compile designs in minutes.

Advantages Over ASICs• No costly NRE charges.

• No time consuming vector generation needed.

• All devices are 100% tested by Xilinx.

• Field upgradeable (remotely upgradeable,using Xilinx Online technology).

• No lengthy prototype or production leadtimes.

• Priced aggressively against comparableASICs.

58

Spartan FPGAs

Reference

For more information see www.xilinx.com/products/spartan2

FPGA Product Selection Matrix

DEVICES KEY FEATURES

XCS05 238 3K 2K-5K 3K 10x10 100 360 77 12 Y

XCS10 466 5K 3K-10K 6K 14x14 196 616 112 12 Y

XCS20 950 10K 7K-20K 13K 20x20 400 1120 160 12 Y

XCS30 1368 13K 10K-30K 18K 24x24 576 1536 192 12 Y

XCS40 1862 20K 13K-40K 25K 28x28 784 2016 205 12 Y

XCS05XL 238 3K 2K-5K 3K 10x10 100 360 77 12/24 Y

XCS10XL 466 5K 3K-10K 6K 14x14 196 616 112 12/24 Y

XCS20XL 950 10K 7K-20K 13K 20x20 400 1120 160 12/24 Y

XCS30XL 1368 13K 10K-30K 18K 24x24 576 1536 192 12/24 Y

XCS40XL 1862 20K 13K-40K 25K 28x28 784 2016 224 12/24 Y

XC2S15 432 8K 6K-15K 22K 8x12 96 384 86 2/24 Y

XC2S30 972 17K 13K-30K 36K 12x18 216 864 132 2/24 Y

XC2S50 1728 30K 23K-50K 56K 16x24 384 1536 176 2/24 Y

XC2S100 2700 53K 37K-100K 78K 20x30 600 2400 196 2/24 Y

XC2S150 3888 77K 52K-150K 102K 24x36 864 3456 260 2/24 Y

XC2S200 5292 103K 71K-200K 130K 28x42 1,176 4704 284 2/24 Y

* I/Os are tolerantX = Core and I/O voltageI/Os = I/O voltage supported

Spartan Series:High Volume

ASICReplacement/

High Performance/SelectRAM Memory

DENSITY FEATURES

Logi

c Ce

lls

Max

imum

Logi

c Ga

tes

Typi

cal S

yste

m

Gate

Ran

ge

Max

. RAM

Bits

CLB

Mat

rix

CLBs

Flip

-Flo

ps

Max

. I/O

Outp

ut D

rive

(mA)

PCI C

ompl

iant

1.8

Volt

2.5

Volt

3 Vo

lt

5 Vo

ltFPGA Product Selection Matrix

59

Reference

Xilinx WebPOWERED Software Solutionsoffer yhou the flexibiity to target theXC9500 and CoolRunner Series CPLDs

on-line or on your desktop.

WebFITTER is an on-line device fitting andevaluation tool which accepts HDL, ABEL, ornetlist files and provides all reports, simulationmodels, and programming files.

WebPACK downloadable desktop solutionsoffer free CPLD software modules for ABEL andHDL synthesis, HDL simulation, device fitting,and JTAG programming.

XC9500 and CoolRunner CPLDs

See www.xilinx.com/products/software/webpowered.htm for more information.

Core

Vol

tage

CPLD

Fam

ily

Devi

ces

Key

Feat

ures

Mac

roce

lls

Max

. I/O

Pin-

to-P

inDe

lay

(ns)

Syst

emFr

eque

ncy

Indi

vidu

alO

E Ct

rl

JTAG

Ultr

aLo

w-P

ower

XC9500XL

XPLA3

XPLA-Enhanced

XPLA2

XC9500

XPLA-Enhanced

XC9536XL 36 36 4 200 √ √XC9572XL 72 72 5 178.6 √ √XC95144XL 144 117 5 178.6 √ √XC95288XL 288 192 6 151 √ √XCR3032XL 32 32 5 200 √ √XCR3064XL 64 64 6 166 √ √XCR3028XL 128 104 6 166 √ √XCR3256XL 256 160 7.5 133 √ √XCR3384XL 384 216 7.5 133 √ √XCR3032A 32 32 6 111 √ √(PZ3032A)*

XCR3064A 64 64 7.5 95 √ √(PZ3064A)*

XCR3128A 128 96 7.5 95 √ √(PZ3128A)*

XCR3320 320 192 7.5 100 √ √(PZ3320C)*

XCR3960 960 384 7.5 100 √ √(PZ3960C)*

XC9536 36 34 5 100 √ √

XC9572 72 72 7.5 83.3 √ √

XC95108 108 108 7.5 83.3 √ √

XC95144 144 133 7.5 83.3 √ √

XC95216 216 166 10 66.7 √ √

XC95288 288 192 10 66.7 √ √XCR5032C 32 32 6 111 √ √(PZ5032C)*

XCR5064C 64 64 7.5 105 √ √(PZ5064C)*

XCR5128C 128 96 7.5 100 √ √(PZ5128C)*

Best Pin-LockingJTAG w/ClampHigh PerformanceHigh Endurance

Ultra Low PowerJTAGIncreased LogicFlexibility

Ultra Low PowerJTAG

Ultra Low PowerHigh Density

Best Pin-LockingJTAGHigh Endurance

Ultra Low PowerJTAG

3.3 VoltISP

5 VoltISP

* Philips part number

Density Features

Reference

Xilinx is the leading suppler of High-Reliability programmable logic devices tothe aerospace and defense markets.

These devices are used in a wide range of appli-cations such as electronic warfare, missile guid-ance and targeting, RADAR, SONAR, communi-cations, signal processing, avionics, and satel-lites. The Xilinx QPRO family of ceramic andplastic QML products (Qualified ManufacturersListing), certified to MIL-PRF-38585, provide youwith advanced programmable logic solutions fornext generation designs, and include selectproducts that are radiation hardened for use insatellite and other space applications.

The Xilinx QPRO family addresses the issuesthat are critical to the aerospace and defensemarket:

• QML/Best commercial practices. Commercialmanufacturing strengths result in more effi-cient process flows.

• Performance-based solutions, including cost-effective plastic packages.

• Reliability of supply. Controlled mask sets andprocesses insure the same quality devices,every time, without variation, which remain

in production for an extended time.

• Off-the-shelf ASIC solutions. Standard devicesreadilly available, no need for custom logicand gate arrays.

Being certified to MIL-PRF-35835 QML, com-plemented by ISO-9000 certification, results inan overall product quality platform that makesXilinx a world-class supplier of programmablelogic devices. You can confidently design withXilinx for High-Reliability systems with theassurance that you are getting unsurpassedquality and reliability, and a long-term commit-ment to the aerospace and defense market.

60

QPRO™ QML Certified FPGAs

FPGA Product Selection Matrix

DEVICES KEY FEATURES

XQ4013XL 1368 13K 10K-30K 18K 24x24 576 1536 192 12/24 Y

XQ4036XL 3078 36K 22K-65K 42K 36x36 1296 3168 288 12/24 Y

XQ4062XL 5472 62K 40K-130K 74K 48x48 2304 5376 384 12/24 Y

XQ4085XL 7448 85K 55K-180K 100K 56x56 3136 7168 448 12/24 Y

XQV100 2700 32K 72K-109K 78K 20x30 600 2400 180 2/24 Y

**XQVR/XQV300 6912 83K 176K-323K 160K 32x48 1536 6144 316 2/24 Y

**XQVR/XQV600 15552 187K 365K-661K 312K 48x72 3456 13824 512 2/24 Y

**XQVR/XQV1000 27648 332K 622K-1,124K 512K 64x96 6144 24576 512 2/24 Y

* I/Os are tolerant** XQR and XQVR devices are Radiation HardenedX = Core and I/O voltageI/Os = I/O voltage supported

– – X *– – X *– – X *– – X *– X I/O *– X I/O *– X I/O *– X I/O *

XC4000 Series:Density

Leadership/High Performance/

SelectRAMMemory

Virtex Family:Density/

PerformanceLeadershipBlockRAM

Distributed RAMSelectI/O 4 DLLs

DENSITY FEATURES

Logi

c Ce

lls

Max

imum

Logi

c Ga

tes

Typi

cal S

yste

m

Gate

Ran

ge

Max

. RAM

Bits

CLB

Mat

rix

CLBs

Flip

-Flo

ps

Max

. I/O

Outp

ut D

rive

(mA)

PCI C

ompl

iant

1.8

Volt

2.5

Volt

3 Vo

lt

5 Vo

lt

FPGA Product Selection Matrix

See www.xilinx.com/products/hirel_qml.htm for more information.

XC1736D 36Kb XXC1765D 64Kb XXC17128D 128Kb XXC17256D 256Kb XXQR/XQ 1701L* 1Mb X XXQR/XQ 1704L* 4Mb X X**

* XQR devices are Radiation Hardened.** XQ devices only.

QPRO QML-Certified PROMsPackage

Device Density DD8 SO20 CC44 PC44

On the Xilinx website you can find any-thing you need for configuring XilinxPLDs. Here are some examples of what’s

available:

• Downloadable Java files that allow for cross-product and multi-platform support for In-System-Programming (ISP). http://www.xil-inx.com/products/software/sx/javapi.htm

• Downloadable JTAG tools (from WebPACK). http://www.xilinx.com/isp/toolbox.htm

• Download cable information (Xilinx Paralleland High-Performance MultiLINX USB cable). http://www.xilinx.com/isp/toolbox.htm

• Design considerations for In-System-Programming. http://www.xilinx.com/isp/toolbox.htm

• Embedded micro-controller support for per-forming JTAG operations, and using JTAGserial vector format (SVF) files for embeddedprocessors. http://www.xilinx.com/isp/ess.htm

• Boundary Scan tutorials and information onthe new IEEE1532 specification which enablesyou to generate programming algorithmsusing only BSDL files.http://www.xilinx.com/isp/standards.htm

• Machine level language translators forGenrad, H-P, and Teradyne among others. http://www.xilinx.com/isp/ate.htm

• Information on the industry leading program-mers from BP Microsystems and Data I/Oalong with many other popular models. Alsocovers the Xilinx HW130 programmer and

device adapters. ttp://www.xilinx.com/sup-port/programr/ps.htm

• Boundary Scan tools from six of the industry-leading tool suppliers, with details on theXilinx device certification program as well asdetails of each tool that can be used for testand debug as well as programming.http://www.xilinx.com/isp/3ptytools.htm

• Order cables on line. Compare the features ofeach of the cables Xilinx has to offer, andchoose the cable that meets your needs.http://www.xilinx.com/support/programr/cables.htm

• Register here for all the latest information onany programming algorithm changes Xilinxmakes to non-volatile (CPLD and PROM)product offerings.http://www.xilinx.com/isp/acn.htm

• Overview of Xilinx PROMS (one time (OTP)and In-System-Programmable).http://www.xilinx.com/products/configsolu.htm

61

Reference

Xilinx ConfigurationSolutions on the WEB

See www.xilinx.com/isp/isp.htm for complete information on all Xilinx Configuration Solutions.

Reference

Xilinx offers a full range of configurationmemories optimized for use with XilinxFPGAs. Our in-system re-programmable

XC18V00 family provides a feature rich, fast con-figuration solution unmatched by any other con-figuration PROM available today, and provides acost-effective method for reprogramming andstoring large Xilinx FPGA bitstreams. Our low-cost XC1700 and XC17S00 families are an idealconfiguration solution for cost sensitive applica-tions.

Our PROM product lines are designed tomeet the same stringent demands as our highperformance FPGAs and CPLDs, taking fulladvantage of our advanced processing technolo-gies. They were developed in close cooperationwith Xilinx FPGA designers for optimal perfor-mance and reliability.

62

PROMS

See www.xilinx.com/products/configsolu.htm or more information

Device Density PD8 SO20 PC20 PC44 VQ44 JTAGISP

XC1765EL(X) 64Kb X X X XXC17128EL(X) 128Kb X X XXC17256EL(X) 256Kb X X XXC17512L 512Kb X X XXC1701L 1Mb X X X XXC1702L 2Mb X XXC1704L 4Mb X XXC18V128 128Kb X X XXC18V512 512Kb X X X XXC18V01 1Mb X X X XXC18V02 2Mb X X XXC18V04 4Mb X X X

Note: XC1700EL parts are marked with an “X” instead of “EL”

3.3V Configuration PROMs

Device Configuration Bits PROM Solution PD8 VO8 SO20XCS05XL 54,544 XC17S05XL X X XCS10XL 95,752 XC17S10XL X XXC2S15 197,696 XC17S15XL X XXCS20XL 179,160 XC17S20XL X XXCS30XL 249,168 XC17S30XL X XXC2S30 336,768 XC17S30XL X XXCS40XL 330,696 XC17S40XL X X* XXC2S50 559,232 XC17S50XL X XXC2S100 781,248 XC17S100XL X XXC2S150 1,041,128 XC17S150XL X XXC2S200 1,335,872 XC17S200XL X X* In development

3.3V Configuration PROMs for Spartan-XL/Spartan-II

Configuration XC17xx/XC18VxxDevice Bits Solution PD8 PC20 SO20 PC44 VQ44

XCV50 558,048 01 X* X X X**XCV100 780,064 01 X* X X X**XCV150 1,038,944 01 X* X X X**XCV200 1,334,688 02 X XXCV300 1,750,656 02 X XXCV400 2,544,896 04 X XXCV600 3,606,816 04 X XXCV800 4,714,400 04 + 512 X XXCV1000 6,126,528 04 + 02 X X* Available on XC17xx only

** Available on XC18Vxx only

Configuration PROMs for Virtex

Configuration XC17xx/XC18VxxDevice Bits Solution PD8 PC20 SO20 PC44 VQ44

XCV50E 630,048 01 X** X X X***XCV100E 863,840 01 X** X X X***XCV200E 1,442,106 02 X XXCV300E 1,875,648 02 X XXCV400E 2,693,440 04 X XXCV405E 3,430,400 04 X XXCV600E 3,961,632 04 X XXCV812E 6,519,648 04+04 or 08* X XXCV1000E 6,587,520 04+04 or 08* X XXCV1600E 8,308,992 04+04 or 08* X XXCV2000E 10,159,648 04+08* or 16* X XXCV2600E 12,922,336 16* X XXCV3200E 16,283,712 16* X X

* In development** Available on XC17xx only*** Available in XC18Vxx only

Configuration PROMs for Virtex-E

XC18V00, XC1700,XC17500 FPGA

Why limit yourself to choosing between a DSP processor or an ASIC when you can have

the best of both worlds? Like the world of DSP processors, Xilinx® gives you the flexibility of

reconfigurable off-the-shelf devices. Like the world of ASICs, we also give you high performance

in a single chip.

Xilinx DSP provides the IP cores and tools you need to take you from definition to

implementation. Build your system using our LogiCORE™ products— ranging from parameterizable

adders and multipliers to FIR, DDS, FFT, and FEC. Use our GUI-based CORE Generator™ system to

automatically generate optimal implementations, and use our new MATLAB SIMULINK interface

for system simulation and HDL generation.

To complement the Xilinx solution, you have access to our AllianceCORE™ and XPERTS™

partners providing additional IP cores, prototyping tools, and design services.

All enabled by our powerhouse Virtex™ , Virtex-E, and Spartan™-II product families, it’s a

total solution that guarantees your time to market success in bringing your product to the world.

The Programmable Logic CompanySM

© 2000, Xilinx, Inc. All rights reserved. The Xilinx name and the Xilinx logo are registered trademarks, AllianceCORE, Core Generator, LogiCORE, Spartan, Virtex, and XPERTS aretrademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc. All other trademarks and registered trademarks are the property of their respective owners.

64

2100 Logic DriveSan Jose, CA 95124-3450

First Class Presort

U.S. Postage

PAID

Permit No. 2196

San Jose, CA

Q200

www.xilinx.com