The Future ofSemiconductor System Level Integration

Dr. Peter J. ZdebelVice President and Chief Technical Officer

ON Semiconductor5005 East McDowell Road, Phoenix, AZ 85008

Semiconductor Industry Productivity Drivers- Four Curve Maturity Model -

Carrier Focus

Matu

rity

(1) SemiconductorManufacturing

(2) EDA Driven Product Design

~ 70%

~ 85%

~ 30%

e-SPS

ContentFocus

(3) Software Driven System Solutions(4) IP Driven Market Access

~ 10%

2010 20201970 1980 1990 2000

Moore’s Law and Fab Investments

1980 1985 1990 1995 2000 2005 2010 0.01

0.10

1.00

100

1,000

Micr

ons

Fab

–Bui

ld –

Cost

(M$

)

Years of Introduction

3.00 um

2.00 um1.50 um

1.00 um

0.60 um0.50 um

0.40 um

0.35 um0.25 um

0.18 um0.15 um

0.13 um0.09 um

0.065 um

0.045 um

0.03 um

20.000 transistors

200.000 transistors

100.000.000 transistors

Today

~4,000

7.000.000 transistors

10.00 10,000

Debate over Moore’s Law and Economics

Intel’s co-founder Gordon Moore accurately predicted the number of transistorson a chip to double every 18 months

Moore’s Law appropriately applies to transistor size affecting the area of Silicon,which a transistor occupies

To further execute Moore’s Law, fundamentally new processes need to bedeveloped, adding huge additional costs for the industry

No exponential progress continues forever. However, it is technically entirelyfeasible to develop the next four to five technology nodes

Economics will potentially drive a slower rate of Moore’s Law. Cumulative industryrevenues are replacing time as the factor for tracking Moore’s Law

Moore’s Law today is more about wafer costs as compared to integrating moretransistors per chip over the past decade

Moore’s Law remains relevant; It is just a matter of affordability of investments

300 mm Wafer Fab Indices

Fab Indices Low End Typical High End Unit Wafer Diameter 300 300 300 mm Line Width 90 65 45 nm Number of Transistors per Chip 25 100 400 Million Supply Voltage 1.0 0.8 0.5 Volt Chip Size 35 50 100 mm2

Wafer Capacity 6,000 8,000 10,000 Wafers/week Process Cycle Time 30 40 60 Days Production Volume in Units 500 Million/year Production Volume in Value 2 5 10 Billion $ Average Selling Price 10 $ Cost of Mask Set 0.6 1.0 2.0 Million $ Fab Investment 2 4 6 Billion $

Increasingly higher mask costs require extremely high unit volumes to amortize costsIncreasingly higher process complexities stretch process cycle times

Digital versus Analog Integration Progression10.00

Oper

atin

g Vo

ltage

3.00 um

2.00 um1.50 um

1.00 um

0.60 um0.50 um

0.40 um

0.35 um0.25 um

0.18 um0.15 um

0.13 um0.09 um

0.065 um

0.05 um

0.03 um

Integration Density DrivenDigital Progression

Operating Voltage LimitedAnalog Progression

< 2.5V

< 3.3V

< 6.0V

< 10V

< 20V

< 500V

< 1.0V

1.00

Micr

ons

0.10

0.011980 1985 1990 1995 2000 2005 2010

Years of Introduction

Analog Separation from Digital IntegrationTechnology Conflicts: Analog and digital functions cannot always be co-integrated

Scaling Separation: Analog integration does not scale like digital integration, deepsub-micron devices degrade in analog performance characteristics

Signal-to-Noise Ratio: Voltage scaling presents limits to required analog S/N ratios

Signal Integrity: Digital signals interfere with low level analog signals

Signal Resolution Limits: Decreasing digital supply voltage levels will result in thedisintegration of some analog and mixed-signal functions from the Digital Integration Space

Digital Product Vulnerability: Deeply scaled device dimensions associated with smallerline width increase susceptibility and vulnerability of digital integrated products toelectrical upset events, i.e. ESD

Digital Product Protection: Analog devices can protect against larger than 20KV ESDevents, scaled digital devices are destroyed at a few hundred volts

Black Art: Analog integration has been lagging digital integration for one decade

The Mix: Most analog solutions are a mix of ICs, discrete components, power devices

Translation Layers between Analog Signal Transportand Digital Signal Processing

Signal ConditioningSignal ConditioningIncoming SignalsIncoming Signals

Signal ConditioningSignal ConditioningOutgoing SignalsOutgoing Signals

Analog Signal TransportOutside the ElectronicSystem in various Media:

WiresCablesFibersAir (Wireless)

Analog & Mixed-SignalProcessing Space

Practically Every Electronic SystemRequires Analog and Mixed-SignalProcessing Functions to ConditionAnalog Signals for Digital Processing

01000100100100100100100010

1101100011111100001010101000100100010100001111100101001001001011010

0010100010100010100100100100100010010010101010001000100010001011100010100001000100100

100010010001000001001000100100100100100010001011001110010100001110110001111110000101010100010001 111000010100010100010100100100100100010010010110010101000100010001000101110001010000100010010000 1110000101000101000101001001001001000100100101

0101010001000100010001011100010100001000100100100010010001000001001000100100100100100010001011100101000011101100011111100001010101000100

10010001010000111110010100100100101010100101000100100101 1001001001000100010

1011000111111000010101010001001100101001010010101010

1010

Digital SignalDigital SignalProcessingProcessing

SpaceSpace

Most Signals Are AnalogOut Here:

Signal Strength:From uV to KV

Signal Frequency:From DC to Optical

Analog Super-Integration Around the Digital Space

Functions for OutgoingAnalog Signals:

ProtectionFiltering

AmplificationPower Conversion

Frequency ConversionVoltage/Current Regulation

Signal ModulationD/A Signal Conversion

Functions for IncomingAnalog Signals:ProtectionFilteringAmplificationPower ConversionFrequency ConversionVoltage/Current RegulationSignal Processing & SamplingA/D Signal Conversion

DigitalDigitalSpaceSpace

AUTOMOTIVE:Power Train

Body Electronics

PORTABLE:Cell Phone,DSC, PDA

COMPUTING: Desktop & NotebookPOWER SUPPLY:

AC/DCDC/DC

Analog & MixedAnalog & Mixed--SignalSignalSpaceSpace Value Proposition:

Highly IntegratedAnalog & Mixed-SignalSolutions

Examples of Analog Content inPortable Power Management Products

AC-DC Conversion

LDO Voltage Regulation& Voltage

Supervisory

Power Management Unit

(PMU) ASSPs

Protection & Filtering

Battery Charging SIM/Smart Card

Interface

RF Power Amplifier Control

White LED Driving

DC-DC Conversion

Audio Amplification

Curve 2:How Have Design Methodologies Changed?

Year

2005

2000

1995

1990

1985

1980

1975

1970

# Transistors

100,000,000

10,000,000

1,000,000

100,000

10,000

1,000

100

10

HW SystemHW System

Behavioral Level

Layout Level

Transistor Level

RTL Level

GATE Level

Algorithmic LevelEntry

RTLRTL

Gate LevelGate Level

High Level Language

Machine Language

ASM Level

OO Language

SW SystemSW System

Advanced HW System Design FlowSystem Architecture DesignPhysical System DesignBehavioral System SynthesisHW/SW System Co-SimulationSystem Partitioning (Subsystems)Multiple-path Designs (Subsystems)High Level HDL EntryCustom Coded, Legacy & Core BlocksData Path CompilationRAM & ROM CompilationLogic Synthesis & Scan InsertionLogic compilationRTL FloorplanningRTL Power AnalysisRTL Static Code AnalysisRTL & Accelerated SimulationRTL Dynamic Coverage AnalysisStatic Timing AnalysisClock Tree SynthesisLogic Floorplanning, Placement, RoutingAutomatic Test Program GenerationFault GradingFormal verificationGate Level SimulationGate Power AnalysisTransistor Power AnalysisDelay CalculationRC Parasitic ExtractionSignal Integrity CheckingElectrical Rule CheckingDesign Rule CheckingLayout vs. Schematic CheckingIC Mask Generation

BEHAVIORAL SYNTHESISHW/SW CO-SIMULATION

FLOORPLANNING, PLACE & ROUTESTATIC TIMING ANALYSISRC PARAMETER EXTRACTIONBUFFERSIZING, BACK ANNOTATIONINCREMENTAL SYNTHESISTEST VECTOR GENERATIONDRC, LVSMASK PREPARATION

IC COMPONENTPROCUREMENT

SYSTEM HARDWARE INTEGRATION & ASSEMBLY

LINKS TO HIGHER LEVEL

FLASH - ROM - RAMMEMORY DATAPATH STANDARD

CELL LOGIC

PartitionedSubsystemIC DesignsWhere SOCIs Not Feasible

90% Effort of MostDigital Designs STRUCTURED

VHDL, VERILOG

Primary Design Steps

IC MANUFACTURING

Curve 2:EDA Driven Product Design

Evolution of Highly Automated and Synthesized Design Flows:

Synthesized Register Transfer Level (RTL) design methodologyAvailability of proven and qualified library componentsPortability of designs to alternative IC manufacturing processesAutomated formal verification methods

Curve 3:Software Driven System Solutions

Systems on Chip (SoC) Design Dictates a New Order:

The longest cycle, namely SOC design, is becoming a bigger andbigger fraction of what is going into applicationsAll HW and SW levels are derived from application specificationsVirtual Prototyping is needed with application flows modeled atthe highest level (cost of design error is prohibitive)All SW development will require a common languageHW development will have to be completely automatedAll software and hardware engineers will have to communicateSoftware, not Hardware, will provide IP leverage in the future

Integrated Design System from SW to HW

• Widely Untapped DesignApproach Today

• Missing Links BetweenSW and HW Offers StrategicMarket Opportunities

Software System Design UsingObject Oriented Code (C, C++, Java, etc.)

High Level Synthesis, Generally UsingOne-step Compiler Structures/processes

For HW/SW System Co-simulation

Behavioral System SynthesisSystem Partitioning (Subsystems)

Hardware System Design onIC, SoC, MCM, Integrated Module, PCB LevelHa

rdwa

re S

ynth

esis

from

Sof

twar

e Def

initi

on

Level 1

Level 2

Level 3

Level 4

Manufacturing

TraditionalIC Products

System on Chip (SoC)Products

Multi-Chip-ModuleSystem Level Products

Integrated ModuleSystem Level Products

Curve 4:Intellectual Property Driven Market Access

Implications of IP on the Semiconductor Industry:

Content (knowledge, software, end-applications) will beincreasingly separated from carrier (silicon delivery channel)Vertically integrated structures will be challenged by open andnetworked organizational structuresMore and more internet-centric companies will be fablessSystems-solution providers will build on IP Driven Market Access Cycle time will be reduced by purchasing outside IP at all levelsSynthesis tools are needed to generate new IP and new productsThe creation of IP as a product will drive company market value

Design Engine and Marketable IP Generator

Design Mapping to Technologies

EDA Design Implementation

Behavioral C++ Level Design

S/W Applications Design

Client Inputs forIntegrated System Solution

RTL Level Design

Behavioral HDL Level Design

System Level Design

IP Input:Any Format Any SourceAny Design Level

IP Output:IP WrappingAny Design LevelTotal SolutionStandard FormatInternet Portable

Sell IP

Acquire IP

Semiconductor Production

Semiconductor Industry Productivity Drivers- Four Curve Linkage -

Matu

rity

(1) SemiconductorIC Manufacturing

(2) EDA Driven Product Design

~ 70%

~ 85%

~ 30%

Link And Hand-off

MechanismsAre CriticalElements!

(3) Software Driven System Solutions(4) IP Driven Market Access

~ 10%

Information

2010 20201970 1980 1990 2000

Summary and Outlook

Below the Inflection Points:Invest In Technology And Networked Businesses By Year 2010, 95% Of All Systems Shipped Will Use IP ProcuredFrom Outside Sources (Source: Dataquest)

Near The Inflection Point:Dominate The Space Or Exit!

Above The Inflection Point:Reduce Or Abandon R&D InvestmentsCreate Partnerships And Relationships For Outsourcing

Connecting All Four Maturity Curves:The Prosperity Of The Semiconductor Industry Depends On The Effective Linkage Of All Disciplines On All Four Curves With Value-added Distribution And Access To The MarketWith Many Different Suppliers In This Food Chain, The Development Of A Well-established Data and Information Flow Is Essential