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The Future of Microprocessors and TiledArchitecturesMulti-Core Architectures and Programming

Stephan Seitz, Daniel Iuhasz, Michael Stauber

Hardware/Software Co-Design, University of Erlangen-Nuremberg

May 15, 2014

Overview

The Future of MicroprocessorsDevelopment of Processors in the HistoryMoore’s Law and Dennard-ScalingPhysical Problems in the FutureModels for Future Multi- and Many-Core Architectures

Tiled Architectures: The Tilera ArchitectureMotivationArchitectureResults

Tiled Architectures: The GreenDroid ArchitectureMotivationArchitectureResults

Conclusion

The Future of Microprocessors

Overview




Conclusion

Stages of Processor Evolution

Picture source: [3]

May 15, 2014 — Stephan Seitz, Daniel Iuhasz, Michael Stauber — Hardware/Software Co-Design — The Future of Microprocessors and Tiled Architectures 4

Single-Core Stage

Execution model:• Naturally serial execution model• Internal parallel instruction execution via pipeline• Hardware multi-threading emulated (e.g.

Hyper-Threading)

Performance increase is frequency increase

, but islimited by:• Physical factors• Stability/reliability• Energy requirements

→ Need another approach to get performance gain

Picture source: [7]


Single-Core Stage

Execution model:• Naturally serial execution model• Internal parallel instruction execution via pipeline• Hardware multi-threading emulated (e.g.

Hyper-Threading)

Performance increase is frequency increase, but islimited by:• Physical factors• Stability/reliability• Energy requirements

→ Need another approach to get performance gainPicture source: [7]


Multi-Core Stage

Offers a solution for:• Performance cap of single-core processors• Energy requirements of mobile devices

But only with good parallel algorithms

Picture source: [5]


Many-Core Stage

Picture source: [1]


Many-Core Stage

Keep on scaling by:• Aggressive use of smaller compute cores• Breaking down the problem in individual parallel tasks

Solve power budget limitation by:• Running individual cores at lower frequency• Keeping cores cold when not in use (dark silicon)


Moore’s law and Dennard-Scaling

Moore’s Law:

• Number of transistors on a chip doubles every 2 years

→ Transistors get smaller

Dennard scaling:

• Energy-efficiency ∼ (transistor size)2

→ Total energy consumption stays constant!


Physical Problems in the Future

End of Dennard scaling:

• Transistor reach quantum physicsdimensions:

→ Additional leakage currents due totunnel effect

Dark Silicon:

• Fixed power budget:

→ Larger portion of chip must remain inactiveor driven at lower frequency

22nm-transistors from Intel

Picture source: [4]


Models for the Future

• Evolution prediction is based onmodels

• Use the evolution trend to build themodels

• Try to account for as many factors aspossible

→ Multiple elements go into the recipe


Device Scaling Model (M-Device)

• Has the transistor as a central element• Considers the roadmap from 45nm to 8nm

(2008 onward)• Optimistic or Realistic points of view

Picture source: [16]


Core Scaling Model (M-Core)

• Predicts the single-core evolution• Measures maximum performance for a

given power budget• “Best case” analysis of a range of factors

Picture source: [6]


Multi-Core Scaling Model (M-CMP)

How will a multicore look like?

Symmetric multi-core




Asymmetric multi-core




Dynamic multi-core




Composed multi-core


Tiled Architectures: The Tilera Architecture

Overview




Conclusion

Motivation for the Tilera Processor Architecture

• Current development: Increasing number of cores on a chip• Goal: Powerful, energy-efficient and programmable Many-Core platform

architecture• Tilera’s approach: using multiple general purpose homogeneous cores

(tiles) on a processor connected with five (six) 2D mesh networks (iMesh)



Overview of the Tilera Architecture

The mesh network of the interconnected chips on the Tilera TILE64Pro

Picture source: [19]May 15, 2014 — Stephan Seitz, Daniel Iuhasz, Michael Stauber — Hardware/Software Co-Design — The Future of Microprocessors and Tiled Architectures 17


One tile on the Tilera TILE64Pro processor




• iMesh consists of five (six)different physical networks:• Static network• User network• I/O network• Memory network• Tile Dynamic Network• (Cache Coherent Network)

• iMesh provides fast inter-corebandwidth: 160 GB/s

• Since TILEPro series: DDC(Dynamic Distributed L3 Cache)



Further information

• The Tilera architecture is officially supported by theLinux kernel since 2.6.36 as well as by otherOpen-Source projects like GCC

• Tilera additionally provides Software components:iLib, MDE, ZOL

• Since the Tilera Gx family: On-Chip Acceleratorsfor specific functions



Performance

• TILE64Pro: performs up to 166BOPS at 866 Mhz (32 bit)

• Memory bandwidth of 25.6 GB/s• Energy-Efficiency: Tilera Gx

processors consume less than 500mW per core

Picture Source: [19]


Applications

• Networking: Server applications,Cloud-Computing

• Wireless: UMTS stations• Multimedia: Video Conferencing,

Video encoding/decoding

Picture Source: [19]


Tiled Architectures: The GreenDroid Architecture

Overview




Conclusion

Motivation for the GreenDroid Architecture

Requirements for future mobile architectures:• Lower power consumption• Even higher computational capabilities• Fast execution of repeating key tasks

[2]

Idea: Usage of highly specialized co-processors• More efficient execution (performance and power consumption)• Larger portion of chip can stay dark

→ GreenDroid is an tiled architecture and OS based on that idea


Overview of the GreenDroid Architecture

Many repeating tasks shared among apps:

• Rendering of graphics (2D, 3D)• Decoding and encoding of images, videos and sound• Decompression of files• Dalvik virtual machine• etc.

→ Run key functions on specialized energy-saving cores (conservation cores)

Remaining code executed less frequently (mainly for control flow)

→ Run on CPUs that control the conservation cores



CPU and conservation cores (C, C-core) on a tile




Design of the conservation cores• Focus on energy-efficiency and performance• Coverage of the most run static code• Automatic synthesis

• Hardware implementation of a C-function• Directly callable by CPU• Translation from C/C++ to synthesizable Verilog-code

• Partial reconfiguration possible



Energy savings introduced by the conservation cores (C-cores)




GreenDroid’s tiled architecture

• GreenDroid is a tiled architecture• Tiles can interact tightly

• on-chip-network• shared L2-cache

• Every tile has different c-cores

→ Flexibility and energy-efficiency



Results

• Research prototype does not exist yet• Simulations show a 7.6× higher total energy efficiency over traditional

architecture with equal performance• Work continues on full-system emulation, timing closure and physical

design

→ Promising approach for future cell phone generations


Conclusion

Summary and Conclusion

• Models for future Many-Core architectures strictly depend on application• Due to importance of energy efficiency in future technologies, Many-Core

architectures will become more and more relevant• Useful approaches for solving the Dark Silicon problem already exist


Thank You For Your Attention!


References I

[1] Creative cow image library.

http://library.creativecow.net/articles/kaufman_debra/NVIDIA-VGX/assets/NVIDIA-Kepler-GK110-Block-Diagram_l.jpg,accessed on 05/14/2014.

[2] Greendroid – official website.

http://greendroid.ucsd.edu/, accessed on 05/14/2014.

[3] Hardware und computer nachrichten.

http://ht4u.net/news/21307_intel_forscht_an_many-core-cpus_-rock_creek_mit_48_kernen_vorgestellt/,accessed on 13/05/2014.

[4] Intel 22nm 3-d tri-gate transistor technology.

http://newsroom.intel.com/docs/DOC-2032, accessed on 05/14/2014.


http://library.creativecow.net/articles/kaufman_debra/NVIDIA-VGX/assets/NVIDIA-Kepler-GK110-Block-Diagram_l.jpg

http://library.creativecow.net/articles/kaufman_debra/NVIDIA-VGX/assets/NVIDIA-Kepler-GK110-Block-Diagram_l.jpg

http://greendroid.ucsd.edu/

http://ht4u.net/news/21307_intel_forscht_an_many-core-cpus_-rock_creek_mit_48_kernen_vorgestellt/

http://ht4u.net/news/21307_intel_forscht_an_many-core-cpus_-rock_creek_mit_48_kernen_vorgestellt/

http://newsroom.intel.com/docs/DOC-2032

References II

[5] Notebook check.

http://www.notebookcheck.net/Processor-Performance-and-Games.23238.0.html, accessed on05/11/2014.

[6] Picture of the intel 80486.

http://en.wikipedia.org/wiki/File:Intel_80486DX2_bottom.jpg, accessed on 05/14/2014.

[7] Sound on sound - audio technology.

http://www.soundonsound.com/sos/jan08/articles/pcmusician_0108.htm, accessed on 05/13/2014.

[8] Wikipedia article about tilera.

http://www.en.wikipedia.org/wiki/Tilera, accessed on 05/14/2014.

[9] Tile processor architecture overview for the tile pro series.

2013.


http://www.notebookcheck.net/Processor-Performance-and-Games.23238.0.html

http://www.notebookcheck.net/Processor-Performance-and-Games.23238.0.html

http://en.wikipedia.org/wiki/File:Intel_80486DX2_bottom.jpg

http://en.wikipedia.org/wiki/File:Intel_80486DX2_bottom.jpg

http://www.soundonsound.com/sos/jan08/articles/pcmusician_0108.htm

http://www.soundonsound.com/sos/jan08/articles/pcmusician_0108.htm

http://www.en.wikipedia.org/wiki/Tilera

References III

[10] Patrick Griffin David Wentzlaff.

On-chip interconnection architecture of the tile processor.

2007.

[11] Emily Blem Hadi Esmaeilzadeh.

Dark silicon and the end of multicore scaling.

2012.

[12] Emily Blem Hadi Esmaeilzadeh.

Power challenges may end the multicore era.

2013.

[13] The Inquirer.

Tilera releases a second 64-core chip.

www.theinquirer.net/inquirer/news/1006963/tilera-releases-core-chip, accessed on 05/06/2014.


www.theinquirer.net/inquirer/news/1006963/tilera-releases-core-chip

www.theinquirer.net/inquirer/news/1006963/tilera-releases-core-chip

References IV

[14] Si Li Jaekyu Lee.

Design space exploration of on-chip ring interconnection for a cpu-gpu architecture.

[15] Jack Sampson Nathan Goulding-Hotta.

The greendroid mobile application processor: An architecture for silicon’s darkfuture.

2011.

[16] E. Fred Schubert official page.

http://homepages.rpi.edu/~schubert/Educational-resources/,accessed on 05/11/2014.

[17] M.B. Taylor.

Is dark silicon useful? harnessing the four horsemen of the coming dark siliconapocalypse.

In Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE, pages1131–1136, June 2012.


http://homepages.rpi.edu/~schubert/Educational-resources/

References V

[18] M.B. Taylor.

A landscape of the new dark silicon design regime.

In Energy Efficient Electronic Systems (E3S), 2013 Third Berkeley Symposium on,pages 1–1, Oct 2013.

[19] Tilera.

Website of tilera.

[20] Ganesh Venkatesh, Jack Sampson, Nathan Goulding, Saturnino Garcia, VladyslavBryksin, Jose Lugo-Martinez, Steven Swanson, and Michael Bedford Taylor.

Conservation cores: Reducing the energy of mature computations.

SIGARCH Comput. Archit. News, 38(1):205–218, March 2010.

[21] V.V. Zhirnov, R.K. Cavin, J.A. Hutchby, and G.I. Bourianoff.

Limits to binary logic switch scaling - a gedanken model.

Proceedings of the IEEE, 91(11):1934–1939, Nov 2003.


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Conclusion

Additional Slides

Design of GreenDroid’s conservation cores1

1Picture source: [20]


Additional Slides

GreenDroid’s C-to-hardware toolchain 2



Additional Slides

Patching of GreenDroid’s conservation cores 3



Additional Slides

pics/tilera_codeexample.png

Code example for using Tilera’s iLib C-library4



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