Microelectronics Reliability 51 (2011) 524–528

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Microelectronics Reliability

journal homepage: www.elsevier .com/locate /microrel

The effect of a post processing thermal anneal on pre-existing and stressinduced electrically active defects in ultra-thin SiON dielectric layers

Robert O’Connor ⇑, Greg HughesSchool of Physical Sciences, Dublin City University, Dublin 9, Ireland

a r t i c l e i n f o a b s t r a c t

Article history:Received 16 November 2009Received in revised form 14 September2010Accepted 14 September 2010Available online 13 October 2010

0026-2714/$ - see front matter � 2010 Elsevier Ltd. Adoi:10.1016/j.microrel.2010.09.019

⇑ Corresponding author. Tel.: +353 17005732.E-mail address: roc@physics.dcu.ie (R. O’Connor).

In this work we demonstrate the effects of a post processing high temperature anneal on the reliability ofultra-thin SiON layers fabricated into both nmos and pmos devices in terms of the initial gate leakage cur-rent, stress induced leakage current (SILC), and the time dependent dielectric breakdown behaviour. Thedevices under consideration were annealed at several temperatures up to 500 �C. We show that differentmechanisms dominate the leakage behaviour at different temperatures by examining the relative leakagein the low voltage range. In particular for pmos devices, the emptying of electron traps induced by tem-perature and subsequent annealing of these traps alters the leakage current profiles significantly, depen-dent on anneal temperature. We show that annealing improves the time dependent dielectric breakdown(TDDB) lifetimes of nmos devices and examine the reasons for this.

� 2010 Elsevier Ltd. All rights reserved.

1. Introduction

In recent large-scale complementary metal oxide semiconduc-tor (CMOS) process technologies, the conventional SiON gatedielectric layer has been replaced by a high-k stack to stem thegate leakage current issues that arise with an ultra-thin layer ofSiON. However, most high-k stacks generally still include an ul-tra-thin interlayer of SiON between the high-k and the silicon sub-strate to take advantage of the high quality interface which can beformed between Si and SiON [1]. For this reason, further under-standing the electrical properties of an ultra-thin SiON layer isdesirable, particularly as there is to-date still a controversy overwhether it is the electrical characteristics of the SiON layer or thehigh-k layer which dominates the reliability of the overall stack [2].

In this work, we examine the changes in the electrical proper-ties of MOSFETs with an SiON gate dielectric following post pro-cessing anneals at a variety of temperatures from 300 to 500 �C.The analysis is carried out on both p- and n-MOSFET devices.Firstly, we examine the effects of an anneal on the entire leakagecurrent profile of the device following an electrical stress at con-ventional accelerated lifetime oxide field conditions, and the abil-ity of a thermal anneal to reverse the damage caused.

We measure the leakage across the entire Vg range, as measur-ing at a single gate voltage primarily takes into account the gener-ation kinetic of one type of defect which is aligned with the siliconFermi level at that particular gate voltage and does not give a com-plete picture of the defect generation during electrical stressing.This allows us to monitor the response of several defect levels inthe SiON bandgap to the anneal.

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Analysis of the data shows that annealing can in fact reduce thegate leakage to levels below that of a virgin device at certain partsof the leakage spectrum, indicating that pre-existing as well asstress-induced defects can be repaired. Subsequently, we examinethe effect of annealing on the leakage current profile across the lowVg range for fresh devices at several temperatures and comparewith the changes observed in a stressed layer in an attempt to dis-tinguish between pre-existing and stress-induced defects in theSILC profile. We also discuss the reversibility of the passivationprocess and examine the rate at which defects are ‘re-activated’during a number of stress–anneal–stress cycles. Finally, the effectof pre-stress annealing on the TDDB characteristics of the layersare discussed in terms of lifetime extrapolations, voltage accelera-tion and the Weibull slope of the TDDB distribution, which gives usdetailed information about the defect generation rate in the layer.

2. Experiment

The devices used for these experiments were square gatedpmos and nmos capacitors on an active area with polysilicon gatesand an area of 4 � 10�8 cm2

. The devices were fabricated on a300 mm test wafer at IMEC and the gate dielectric was an SiONlayer with 1.2 nm EOT grown in situ steam generated SiO2 withsubsequent nitridation and a poly-Si gate. All anneals in this workwere carried out by placing the die under evaluation in a standardfurnace in a nitrogen atmosphere for a time of 30 min unless other-wise stated.

For the leakage current measurements featured in this work, wemeasure across the entire low gate voltage range from �2 V to 2 V.As previously explained [3], this allows us to evaluate the

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contribution of several defect levels in the SiON bandgap to theleakage profile, rather than measuring at a single point whichmay or may not be favourable for trap-assisted tunneling. Thechange in leakage following a stress or anneal is used as a relativemetric for defect generation/passivation and was defined as the ra-tio of the change in leakage current at a given voltage to the initialtunnel current at that voltage (DI/I0). In the case where the leakageof fresh devices is evaluated pre and post-anneal, a total of 44 sam-ples were measured in each case to give a reliable distribution,while accounting for thickness variation. Similarly, where leakagecurrent profiles for stressed devices are shown, they are taken froman average of the SILC across a minimum of five devices to isolatethe reproducible effects of the stress and anneal cycles.

For the TDDB evaluation both nmos and pmos devices werestressed under constant voltage stress in inversion. In both cases,four voltage conditions and 15 samples per voltage were used fora total of 60 devices used to calculate the Weibull slopes. The de-vices were stressed until hard breakdown which we define as asudden significant increase in the gate current, but the statisticalanalysis was also carried out for the case of soft breakdown usinga current jump of 3 lA in each case. Using such a low current stepas the breakdown trigger ensures that we are still in the trap gen-eration phase and not in the progressive wear-out mode where aleakage path from anode to cathode has already formed. Using aTDDB trigger in the progressive wear-out phase can lead to over-estimations of the Weibull slope and subsequently, incorrectassumptions about the defect generation in the layer and the truesoft-breakdown lifetime extrapolation [4].

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Fig. 1. SILC as a function of sensing gate voltage following a stress–anneal–stresssequence in (a) nmos and (b) pmos devices at 2.6 V and �2.8 V respectively.

3. Annealing of defects in the dielectric

Fig. 1 shows the effect of a post stress anneal on both (a) nmosand (b) pmos devices. In both cases, the devices are stressed ininversion at 2.6 V and �2.8 V respectively, for a time of 50 s. Fol-lowing the stress, the die is transferred to the nitrogen atmospherewhere it undergoes a 30 min anneal at 300 �C. We can see clearlythat in both cases from the post-anneal IV curve (at room temper-ature), significant reversal of the SILC is visible indicating that thedefects generated during the stress have been passivated by theanneal. When comparing the spectra for the nmos and pmos de-vices, they have a common feature in the peak between Vfb andVt corresponding to a mid-gap state. The nmos devices show a de-fect band deep in the bandgap below the silicon valence band, andthe pmos devices show a state which is very shallow, above the Siconduction band. The mid-gap defect which is common to both de-vices show less recovery than the other peaks and when the de-vices are stressed subsequent to the anneal, these defects arequickly re-activated as evidenced by the rapid growth of this peakin comparison with the others. Substrate hot carrier injection(SHCI) measurements were performed on the layers to establishthe physical position (either at the interface or in the ‘bulk’) ofthe defects corresponding to each peak. The SHCI technique makesthis possible by preferentially degrading the Si/SiON interface withhigh-energy electrons and noting the SILC peaks which grow mostrapidly in the spectrum during the degradation [5]. In this case, thepeaks at the bottom and top of the bandgap are found to corre-spond to interface states as shown by Fig. 2.

When we look at this in the context of the anneals, we see thatthese two peaks are the ones most effectively passivated duringthe anneal and can conclude that the interface states show themost improvement. Examining the behaviour under stress afterthe anneal in Fig. 1, it seems this improvement is more ‘robust’than the case for the bulk defects.

After annealing, the subsequent stress induced generation of de-fects involves three mechanisms. The regular generation of defects

which is common to constant voltage stresses, the re-activation ofstress-induced defects passivated during the anneal, and finallythe re-activation of pre-existing defects passivated during the anneal.If we look at Fig. 1a, in the negative Vg range we see that post-annealthe leakage is in fact lower than for the virgin device indicating thatwe are indeed annealing out process induced defects as well as thosebrought about by stress. The effect is also visible in the I–t traces ofboth nmos and pmos devices as shown in Fig. 3 where those whichunderwent voltage stress after an annealing step showed lower ini-tial leakage than those which had not, indicating that significantreduction of pre-existing defects has taken place.

The de-coupling of the three effects requires examining the ex-tent to which pre-existing defects are annealed to further under-stand the effect on stress-induced defects. To quantify this effect,fresh IV profiles were measured on several hundred structures be-fore and after subjecting them to anneals at various temperaturesup to 500 �C. It was then possible to construct a distribution of leak-age current data for each point in the SILC spectrum as a function ofannealing temperature for both the nmos and pmos structures.

Fig. 4 shows sample datasets for 300 �C and 500 �C anneals for(a) nmos devices sensed at �1 V and (b) pmos devices sensed at1 V. In the case of the 300 �C anneal, the nmos devices show almostno recovery, but the distribution for pmos devices on the otherhand shows a reduced slope indicating an increase in the leakagein these devices. As the temperature involved is too low to create

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Fig. 2. Comparison of substrate hot carrier and constant voltage stresses for (a)nmos and (b) pmos devices. The peaks which grow more rapidly under SHCIcorrespond to interfacial defects.

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Fig. 3. I–t traces of fresh (a) nmos and (b) pmos devices subjected to a voltagestress. The devices which have undergone a 30 min anneal at 500 �C prior tostressing show a lower initial leakage current indicating the annealing of pre-existing defects takes place.

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new defects in the dielectric, we speculate that the annealing de-traps negative charge in the oxide which gives rise to the increasedleakage at these moderate temperatures. If we examine the changein leakage across the entire sense Vg range as shown in Fig. 5, wesee that for the pmos layers, the increase is present across the Vg

range. In the above explanation, the absence of the negative chargewould leave sites which can take part in the trap-assisted tunnel-ing process for both polarities thereby increasing the overall leak-age across the Vg range. If the effect was mostly Coulombic innature we would not see such symmetry. Note also that there isa small increase in the nmos layers in the positive voltage rangehowever it makes up a small percentage of the overall leakage inan nmos device in such a band alignment.

If the anneal temperature is increased to 500 �C, the results arequite different. There is a clear decrease in leakage for both nmosand pmos devices as illustrated in Fig. 5. The broadening of theleakage distribution caused by the de-trapping process is still pres-ent for the pmos devices, while concurrently the distribution isshifted toward lower leakage by a similar recovery process seenin the nmos devices.

To confirm the change in slope of the distribution in the pmosdevices was due to charge removal effects, pre- and post-annealIDVG curves were examined. The result of the anneal is an increasein pmos Vt and a lower sub-threshold slope while the effects are re-versed in the nmos devices, confirming a removal of near-interfacenegative charge.

To examine the effects of annealing on stress-induced defectsalone, we annealed several samples at 500 �C for 30 min beforestressing the devices so as to anneal the pre-existing defects. Afterthe stress a further anneal can then be used to observe the re-sponse of only these defects created during the stress. The deviceswere stressed for 100 s at 2.5 V for nmos and �2.8 V for pmos sam-ples, then allowed to relax for 1 h to remove the transient SILCcomponent before the anneal. Fig. 6 shows the results for bothsamples (averaged over five devices). In both cases the anneal issuccessful in removing the remaining stress-induced defects andfor most peaks in both device types, up to 75% of the damage is re-versed. In the case of the deep interfacial defect seen in nmos de-vices at a gate voltage of ��1 V it is fully recovered. Note alsothat the anneal seems to create a new defect band in the pmos de-vices, visible at �0.2 V.

4. Time dependent dielectric breakdown

The ability of a post processing anneal at 500 �C for 30 min toreduce the median leakage current in an ultra-thin layer by up to30% brings about the possibility that such a layer might exhibitlonger TDDB lifetime due to increased integrity at the beginningof its operational life. To explore this possibility, we carried out aTDDB study on devices as-received, and devices which underwenta 300 �C and a 500 �C anneal respectively.

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Fig. 7a shows the breakdown distributions (with a breakdowncriterion of a 10 lA increase in gate leakage current) for the nmosdevices. The distribution for the non-annealed case is comparedwith that for the 500 �C anneal in the plot. Note that the data ob-tained for 300 �C is not plotted for reasons of clarity, but is compli-ant with the observations outlined in the following paragraphs.The distribution shows that there is indeed a general trend towardslonger tBD values for the devices which have been annealed. The tBD

statistics also show that there is an increase in Weibull slope from1.23 to 1.56 in the devices which have been annealed. The in-creased Weibull slope results from the removal of pre-existing de-

fects which can ‘link-up’ with stress-induced defects to form apercolation path which triggers the breakdown. When these de-fects are passivated by the anneal, they effectively make the layerslightly thicker from the point of view of the trap generation andbreakdown statistics [6].

The combination of higher Weibull slopes and increased time-to-breakdown at the stress conditions following the anneal leadsto an appreciable increase in device lifetime as shown in Fig. 7b.The graph shows the lifetime extrapolation for the devices scaledto 0.1 cm2 and 0.01% device failure rate. The extrapolation is madeusing the worst-case linear extrapolation model and yields a 0.38 Vincrease in maximum operating voltage for a 10 year lifetimecriteria.

A corresponding analysis of the pmos layers shows quite differ-ent results. As noted in the last section, the de-trapping of negativecharges caused by the annealing results in a higher trap-assistedtunneling component in the gate current. This effect is evident inthe TDDB distributions for the pmos devices shown in Fig. 8a.The time-to-breakdown is reduced at the stress fields consideredand there is also a reduction in Weibull slope which can be attrib-uted to the higher instance of trap-assisted tunneling sites in theannealed pmos devices. The scaled lifetime extrapolation for thepmos devices is shown in Fig. 8b. The combination of reduced tBD

at stress conditions and lower Weibull slope leads to an overallreduction in device reliability, though this is offset slightly by ahigher measured voltage acceleration in the pmos devices. Overalla reduction in maximum operating voltage of 0.25 V is observed. If

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we compare this with the initial leakage current data from the pre-vious section we see that even though the initial leakage is im-proved across most of the Vg range by a 500 �C anneal, the tBD

behaviour is worse. This suggests that the defects responsible forthe breakdown are the very shallow defects around +1.5 V inFig. 1b, where there is no improvement in leakage after the anneal.

The TDDB analysis was also carried out for the case of soft break-down, where a 3 lA current step trigger was used. The reason for thisis that the hard breakdown distribution includes the wear-outphase, where the percolation path has formed from anode to cathodebut does not carry an appreciable current as it begins to grow andwear-out. Depending on the length of this wear-out phase in com-parison with the time taken to generate the path, this can affectthe accuracy of the Weibull statistics [4]. The soft breakdown distri-bution isolates the trap generation phase of the breakdown process.Our results show the same trends for the soft breakdown distribu-tions, indicating that for these devices the wear-out phase doesnot impact significantly on the hard breakdown distributions.

5. Conclusion

The effect of a post processing anneal on the electrical charac-teristics of ultra-thin SiON layers are presented. Annealing shows

effective passivation of both stress-induced and pre-existing de-fects at 500 �C. pmos devices also show electron de-trapping.Resultant TDDB distributions show improved lifetime for nmos de-vices and degraded lifetime in pmos devices.

Acknowledgements

This work is funded by the Irish Research Council for Science,Engineering and Technology (IRCSET) under the Embark Initiativeand by Science Foundation Ireland under the FORME Strategic Re-search Cluster. The authors wish to acknowledge the IMEC, Bel-gium for sample processing and Dr. Thomas Kauerauf and Dr.Robin Degraeve for helpful discussions.

References

[1] Wilk et al. J Appl Phys 2001;89:5243.[2] Bersuker et al. In: IEDM Tech Dig. San Francisco, USA; 2008.[3] O’Connor et al. In: Proc IRPS Phoenix, USA; 2007.[4] Kaczer et al. In: IEDM Tech Dig. San Francisco, USA; 2004.[5] O’Connor et al. J Appl Phys 2008;103:064503.[6] Degraeve et al. Trans Elec Dev 1998;45(4):904.