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THE BEAN:
A PULSE PROCESSOR FOR A
PARTICLE PHYSICS EXPERIMENT
A DISSERTATION
SUBMITTED TO THE DEPARTMENT
OF ELECTRICAL ENGINEERING
AND THE COMMITTEE ON GRADUATE STUDIES
OF STANFORD UNIVERSITY
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
Angel Abusleme
May 2011
http://creativecommons.org/licenses/by-nc/3.0/us/
This dissertation is online at: http://purl.stanford.edu/pj537bm6926
© 2011 by Angel Abusleme. All Rights Reserved.
Re-distributed by Stanford University under license with the author.
This work is licensed under a Creative Commons Attribution-Noncommercial 3.0 United States License.
ii
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Bruce Wooley, Primary Adviser
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Boris Murmann
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Gunther Haller
Approved for the Stanford University Committee on Graduate Studies.
Patricia J. Gumport, Vice Provost Graduate Education
This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file inUniversity Archives.
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iv
A mi adorada mama, que hace mucho tiempo hizo crecer en mı la pasion por la
electronica, y que desde el Reino de los Cielos me ha guiado para poder sacar
adelante mi doctorado. Sin ella, nada de esto hubiese sido ni remotamente posible.
A ella dedico esta tesis, en agradecimiento por su amor y su entrega, y con la
esperanza de que se sienta orgullosa de mı en su morada eterna.
Abstract
The International Linear Collider (ILC), a next generation particle accelerator, will
smash electron and positron bunches at up to 500GeV (1000GeV after a planned
upgrade). The 31-km long collider’s experiments will help scientists to understand
the fundamental constituents of matter.
Located at the ILC detector’s forward region, the BeamCal is a highly segmented
(> 90,000 channels) calorimeter that will serve three main purposes: ensure hermetic-
ity of the detector for low polar angles, reduce the backscattering from pairs into the
detector center, and provide a low-latency signal for beam diagnostics. The BeamCal
specifications in terms of radiation tolerance, noise suppression, signal charge, pulse
rate and occupancy pose unique challenges for the front-end and readout electronics
design.
Designed for the 180-nm TSMC mixed-signal technology, The Bean – BeamCal
Instrumentation IC – is a 32-channel front-end and readout ASIC that will address the
BeamCal instrumentation requirements. By employing a charge-sensitive amplifier
and a switched-capacitor reset circuit, the Bean will process the input charge signals
at the ILC pulse rate. Each channel will have a 10-bit successive approximation
register analog-to-digital converter and digital memory for readout purposes. The
Bean will also feature a fast feedback adder, capable of providing an 8-bit, low-latency
output for beam diagnostics purposes.
This work presents the design and characterization of The Bean prototype, a
3-channel ASIC that proves the principle of operation described.
vii
Acknowledgments
Through these few lines, I wish to acknowledge everyone who contributed in making
my experience as a Stanford student so formative and unforgettable.
First of all, I would like to express my most sincere words of gratitude to my
advisor, Professor Bruce Wooley. Through these years, his knowledge, ideas and
wisdom enlightened my work. He always surprised me with insightful comments and
questions, showing me a different way or suggesting me to look a bit further. I am
eternally indebted to him.
I would also like to thank my associate advisor, Professor Boris Murmann, for his
infinite patience through hours of insightful discussions on circuit design, and for his
support during difficult times in my period as a Stanford student. He always treated
me as one of his own students.
I want to thank my research supervisor at SLAC, Dr Gunther Haller, for his strong
support through these years. I admire his professionalism and project management
abilities. Following his example, I will become a better engineer.
I want to express my deepest gratitude to my friend, Dr Angelo Dragone. He
shared with me his vast expertise on instrumentation for particle physics through
countless discussions that allowed me to obtain a functional circuit. His help was
crucial during both, design and test phases. I also thank him for the moral support
when there seemed to be no light at the end of the tunnel.
It has been a great honor to have Professor Martin Breidenbach as my advisor at
SLAC and as my orals chair. He is simply brilliant and his fruitful discussions always
show unexpected points of view.
I want to show my gratitude to Professor Tom Lee, for sharing his passion for how
viii
things work and for being supportive during the most difficult time of my life.
I want to show my appreciation to Dr Dietrich Freytag for his help and support,
which was very important during early stages of my research. I also thank Ryan
Herbst, who helped me with the test setup of my first chip. He showed me what was
possible, setting a high standard for my final circuit test setup.
I wish to thank all the SLAC lab staff, especially Mark, Lupe, Yolanda, Tan and
Tyson, for the willingness and technical support provided during all the testing phase.
Their help was crucial in obtaining meaningful data from my circuit.
I would like to thank Dr Albert Lin, for his help with the scanning electron
microscope, which showed me that my first chip design was on the right track. I also
thank Patrick from EAG Labs, who was the main surgeon of my circuit.
I want to express my gratitude to Ann Guerra, whose support went beyond her
administrative tasks and pulled me through difficult times, and Traci Kawakami,
Natasha Haulman and Natasha Newson, for all the administrative support provided.
I also express my gratitude for the support received from past and present Woo-
ley’s group and Murmann’s group students, especially Mohammad, Maryam, Rox-
ana, Nasrin, Xinying, Sakshi, Je-Kwang, Hyunsik, Robert, Sang-Min, Pouya, Scott,
Sotirios, David, Manar, Pedram and Alireza. I would like to thank Katelijn, whose
help was fundamental when I was starting my design.
I also wish to thank other EE friends at Stanford for their support, especially
Srikant, Arjang, Henrique, Quique, Juan Manuel, Eduardo, Stephen, David, James,
Nathan and Fernando.
I would like to thank all the Stanford Spanish mass choir members, VIVIS, Guiller-
mo, Mauricio, Barbara, Paco, Marıa, Lucıa, Adriana, Maida, Mery Jo, Olivier and
Trangdai, for their support through these years. I also thank my courtyard friends
Rodrigo, Pilar, Juan, Pachi, Ryan, Kerry, Jon, Jenny, Jose and Pao, for being always
there.
I want to thank my South American friends at Stanford, especially Pelao, Pablo,
Nancho, Lucy, Silvia, Cristobal, Caro, Nico, Josefa, Rafa, Mauricio, Nicole, for all
the great moments we shared.
I want to express my gratitude to Jean and Gene Mohler, our first friends in the
ix
USA, for being always so close and making us feel at home.
I want to express my gratitude to all my friends from Chile, especially those who
never gave up cheerleading me: Carola, Stephen, Choe, Raul, Carmen, Jose Luis,
Eduardo and Keno.
I also wish to thank my family in Los Angeles, for always being so close no matter
how far.
I would like to express my deepest gratitude to my family members, my mother
Angelica, my father Amador, my brother Patricio and my sisters Karen and Cynthia.
I also thank my extended family members Isabel, Arturo, Marıa Isabel, Constanza,
Camila, Andres, Charles, Ignacio, Eduardo, Rosa. I would have not succeeded with-
out their support.
Finally, I want to thank my son Juan Pablo, my daughter Sofıa and my wife
Marıa Jose for their love and unconditional support. My wife embarked with me in
this uncertain trip, resigning from her own goals and dreams, and without any clue
or warranty on how or when this would end, if ever. No words can express the level
of gratitude I feel for her logic-defying support.
x
Contents
Abstract vii
Acknowledgments viii
1 Introduction 1
1.1 Particle physics experiments . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Electronics for particle physics experiments . . . . . . . . . . . . . . . 5
1.2.1 Instrumentation for particle physics experiments . . . . . . . . 5
1.2.2 Detector technologies . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.3 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.4 Filter and discriminator . . . . . . . . . . . . . . . . . . . . . 9
1.2.5 Memory arrays . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Noise minimization in circuits for particle physics . . . . . . . . . . . 10
1.4 Thesis content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Problem Definition 13
2.1 The International Linear Collider . . . . . . . . . . . . . . . . . . . . 13
2.2 The ILC forward calorimeter . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 BeamCal instrumentation ASIC specifications . . . . . . . . . . . . . 16
3 Noise Analysis in Pulse Detectors 18
3.1 Classical noise analysis in pulse processors . . . . . . . . . . . . . . . 18
3.1.1 Noise models . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.2 Equivalent noise charge . . . . . . . . . . . . . . . . . . . . . . 21
xi
3.1.3 Noise coefficients . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.4 Normalized noise coefficients . . . . . . . . . . . . . . . . . . . 26
3.1.5 Noise analysis in time-varying systems . . . . . . . . . . . . . 27
3.2 gm/ID extension of noise analysis . . . . . . . . . . . . . . . . . . . . 30
3.3 Noise minimization in particle physics experiments . . . . . . . . . . 32
3.4 Noise analysis and switched capacitors circuits . . . . . . . . . . . . . 38
4 System-Level Design 40
4.1 Signal, noise and rate considerations . . . . . . . . . . . . . . . . . . 40
4.2 Signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3 Power and noise budget . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4 Block and timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . 46
5 The Bean Prototype: Circuit Design 51
5.1 Charge-sensitive amplifier design . . . . . . . . . . . . . . . . . . . . 51
5.2 CSA precharger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3 Filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.4 ADC design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.5 Adder design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.6 Signal buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.7 Rail-to-rail buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6 The Bean prototype: Implementation 72
6.1 Floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.2 MOM capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7 Test Results 82
7.1 Test methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.2 ADC test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.3 The Bean prototype test results . . . . . . . . . . . . . . . . . . . . . 90
7.3.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.3.2 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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7.3.3 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.3.4 Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.3.5 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.3.6 Weighting function measurements . . . . . . . . . . . . . . . . 102
7.3.7 Noise measurements . . . . . . . . . . . . . . . . . . . . . . . 107
7.3.8 Fast feedback adder . . . . . . . . . . . . . . . . . . . . . . . . 110
7.4 Summary of design flaws . . . . . . . . . . . . . . . . . . . . . . . . . 112
8 Conclusion 113
8.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.2 Suggestions for future work . . . . . . . . . . . . . . . . . . . . . . . 115
A The Bean and ADC pinout 118
Bibliography 128
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List of Tables
2.1 BeamCal instrumentation ASIC specifications summary. . . . . . . . 17
4.1 Channel noise budget. . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.1 Charge amplifier specifications. . . . . . . . . . . . . . . . . . . . . . 52
5.2 CSA design values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3 Filter amplifier design values. . . . . . . . . . . . . . . . . . . . . . . 63
5.4 Comparator design values. . . . . . . . . . . . . . . . . . . . . . . . . 68
5.5 Signal buffer design values. . . . . . . . . . . . . . . . . . . . . . . . . 69
5.6 Rail-to-rail buffer main design values. . . . . . . . . . . . . . . . . . . 71
7.1 Unit capacitance values and estimated mismatch for the three different
ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.2 The Bean prototype current dissipation, measured and simulated. . . 91
7.3 Reset-release schemes used in the DCal mode. . . . . . . . . . . . . . 103
7.4 Series noise coefficients from measured weighting functions. . . . . . . 108
7.5 Adder gain from all channels. . . . . . . . . . . . . . . . . . . . . . . 111
A.1 The Bean pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
A.2 ADC pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
xiv
List of Figures
1.1 SLAC National Accelerator Laboratory. Reprinted from SLAC web-
site, 2011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Electron-positron traces in a cloud chamber . . . . . . . . . . . . . . 3
1.3 BaBar detector at SLAC. Reprinted from SLAC website, 2011. . . . . 4
1.4 Single channel generic block diagram . . . . . . . . . . . . . . . . . . 6
1.5 Charge-sensitive amplifier (CSA) using common-gate stage. . . . . . . 8
1.6 CSA using voltage amplifier. . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Pulse train structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 ILC detector’s cross section . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 BeamCal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Equivalent representation of a linear circuit’s internal noise sources,
referred to a single port. . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Schematic for noise analysis. Two noise sources are considered: detec-
tor shot noise and amplifier noise, represented as voltage and current
noise. This includes both, white and flicker noise. . . . . . . . . . . . 22
3.3 Example of normalized noise curves. . . . . . . . . . . . . . . . . . . 32
3.4 Example of ENC due to series white noise for a PMOS input device
and a 41-fF constant capacitance at the input node. . . . . . . . . . . 35
3.5 Example of ENC due to series white noise for a PMOS input device
and a 41-fF constant capacitance at the input node. . . . . . . . . . . 36
3.6 Example of ENC due to series white and flicker noise, PMOS input
device and 41 fF constant capacitance at input node. . . . . . . . . . 37
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3.7 Comparison between two weighting functions. The switched-capacitor
portion has a 2 : 1 ratio in switching frequency. . . . . . . . . . . . . 39
4.1 ENC series noise contribution as a function of input device’s ID, for
different values of gm/ID. . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2 Signal path block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3 The Bean block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4 The Bean prototype block diagram. . . . . . . . . . . . . . . . . . . . 48
4.5 Timing diagram in SDT mode. . . . . . . . . . . . . . . . . . . . . . 48
4.6 Timing diagram in DCal mode. . . . . . . . . . . . . . . . . . . . . . 49
4.7 Simulated weighting function in DCal mode, for a switched-capacitor
integrator and slow reset-release technique. . . . . . . . . . . . . . . . 50
5.1 The Bean block diagram, including one channel and the fast feedback
adder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2 Schematic of a single-ended, NMOS-input folded-cascode amplifier. . 54
5.3 CSA simplified small signal static model. . . . . . . . . . . . . . . . . 55
5.4 CSA dynamic model. . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.5 CSA feedback network. . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.6 Schematic of CSA precharger circuit. . . . . . . . . . . . . . . . . . . 60
5.7 Filter simplified schematic. . . . . . . . . . . . . . . . . . . . . . . . . 60
5.8 Class A/AB filter’s OTA schematic. . . . . . . . . . . . . . . . . . . . 61
5.9 Class A/AB filter OTA common-mode feedback circuit schematic. . . 62
5.10 OTA small-signal half circuit model. . . . . . . . . . . . . . . . . . . 62
5.11 Charge-redistribution switched-capacitor DAC network. . . . . . . . . 64
5.12 ADC comparator schematic. . . . . . . . . . . . . . . . . . . . . . . . 67
5.13 Adder schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.14 Level-shifting signal buffer. . . . . . . . . . . . . . . . . . . . . . . . . 70
5.15 Rail-to-rail buffer schematic. . . . . . . . . . . . . . . . . . . . . . . . 71
6.1 Floorplan of the Bean prototype core. . . . . . . . . . . . . . . . . . . 73
6.2 Channel layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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6.3 Charge-sensitive amplifier layout. . . . . . . . . . . . . . . . . . . . . 75
6.4 Signal buffer layout, including level-shifting capacitor. . . . . . . . . . 75
6.5 SC filter layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.6 Buffer layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.7 SAR ADC layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.8 Layout of adder for fast feedback operation. . . . . . . . . . . . . . . 78
6.9 The Bean prototype layout. . . . . . . . . . . . . . . . . . . . . . . . 79
6.10 Unit MOM capacitor layout. . . . . . . . . . . . . . . . . . . . . . . . 80
6.11 3D view of the single-layer MOM capacitor array. . . . . . . . . . . . 81
6.12 3D bottom view of the single-layer MOM capacitor array. . . . . . . . 81
7.1 ADC’s testbench printed circuit board layout. . . . . . . . . . . . . . 83
7.2 The Bean prototype testbench printed circuit board layout. . . . . . . 84
7.3 MIMCap ADC linearity test results. . . . . . . . . . . . . . . . . . . . 86
7.4 Dual-layer MOMCap ADC linearity test results. . . . . . . . . . . . . 87
7.5 Single-layer MOMCap ADC linearity test results. . . . . . . . . . . . 88
7.6 The Bean prototype current distribution. . . . . . . . . . . . . . . . . 92
7.7 Filter differential output, running at half speed. . . . . . . . . . . . . 93
7.8 The Bean prototype linearity test results, SDT mode and full-scale
input range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.9 The Bean prototype linearity test results, SDT mode and input range
of 108% of full scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.10 The Bean prototype linearity test results, DCal mode and full-scale
input range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.11 The Bean prototype linearity test results, DCal mode and input range
of 116% of full scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.12 Crosstalk effects of Channel 1 input ramp on Channels 2 and 3, SDT
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.13 Crosstalk effects of Channel 1 input ramp on Channels 2 and 3, DCal
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.14 Bandwidth test result, SDT mode. . . . . . . . . . . . . . . . . . . . 100
xvii
7.15 Bandwidth test result, DCal mode. . . . . . . . . . . . . . . . . . . . 101
7.16 SPICE-simulated weighting functions, SDT mode. . . . . . . . . . . . 104
7.17 Measured weighting functions, SDT mode. . . . . . . . . . . . . . . . 104
7.18 SPICE-simulated weighting function, DCal mode, no filter. . . . . . . 105
7.19 Measured weighting function, DCal mode, no filter. . . . . . . . . . . 105
7.20 SPICE-simulated weighting function, DCal mode. . . . . . . . . . . . 106
7.21 Measured weighting function, DCal mode. . . . . . . . . . . . . . . . 106
7.22 Measured weighting function with CDS scheme, DCal mode. . . . . . 107
7.23 Measured noise as a function of total input capacitance, for three dif-
ferent signal paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.24 Adder test results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.25 Supply-insensitive bias circuit used in the Bean prototype. The pad
connection is shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
A.1 The Bean bonding diagram. . . . . . . . . . . . . . . . . . . . . . . . 124
A.2 Dual-layer MOMCap ADC bonding diagram. . . . . . . . . . . . . . . 125
A.3 Single-layer MOMCap ADC bonding diagram. . . . . . . . . . . . . . 126
A.4 MIMCap ADC bonding diagram. . . . . . . . . . . . . . . . . . . . . 127
xviii
Chapter 1
Introduction
1.1 Particle physics experiments
Particle physics, also called High Energy Physics “is a branch of physics that studies
the elementary constituents of matter and radiation, and the interactions between
them”[1].
The main tools used by particle physicists are particle accelerators, which accel-
erate subatomic particles to nearly the speed of light. These accelerated particles,
focused in a thin beam traveling along the beamline, collide against a fixed target or
other particles in the same beamline moving in the opposite direction. As a result,
colliding particles break into decay products that scatter from the collision point.
The study and post-processing of the results from the collisions provides information
on the nature of elementary particles.
Particle physics experiments have allowed humankind to gain an understanding
of the structure of matter and use that understanding in technological development.
However, starting with the famous experiments by Rutherford on metal foil ion bom-
bardment in 1909, particle physics is requiring ever-increasing energies to explore
deeper into matter, as well as improved detection technology to find elusive particles
and reconstruct their trajectories precisely for a better identification and understand-
ing. In order to achieve the required energies, particles are nowadays accelerated in
kilometer-scale accelerators, which are among the most ambitious engineering projects
1
2 CHAPTER 1. INTRODUCTION
Figure 1.1: SLAC National Accelerator Laboratory. Reprinted from SLAC website,2011.
ever undertaken. Examples of these enormous instruments are the Large Hadron Col-
lider (LHC) at Organisation Europeenne pour la Recherche Nucleaire (CERN), the
Tevatron at Fermilab, and the PEP-II Accelerator at SLAC National Accelerator
Laboratory. Figure 1.1 shows a picture of the latter laboratory, where the research
presented in this work has been conducted. The three-kilometer long linear accelera-
tor, in the picture’s top right quadrant, is the longest in its class.
As the beam energy has increased over time, the instrumentation systems have
also improved in sensitivity, rate, resolution and processing capabilities, allowing the
measurement of more information, more precisely and in a shorter time. Rutherford
used a simple zinc-sulfide screen, an early scintillation detector that produces a local-
ized glow where an alpha particle hits it. Popular choices in later decades were cloud
and bubble chambers that produce 3-D traces of particle trajectories in a gaseous or
liquid volume. In order to study the event, a photography of the fading trajectories
described had to be opportunely taken. As an emblematic example, a cloud chamber
was the detector that proved the existence of the positron, or electron antiparticle.
1.1. PARTICLE PHYSICS EXPERIMENTS 3
Figure 1.2: Cloud chamber showing electron-positron traces in 1932. This was thefirst time that positrons were detected. Reprinted from Wikipedia website, 2011.
The result from this famous test is shown in Figure 1.2. Electronic systems were later
introduced, improving sensitivity and providing an effective means of implementing
multichannel measurement systems.
During the decade of 1980s, CMOS technology changed the trend of electronic
instrumentation for particle physics from printed circuit boards (PCBs) to custom
integrated circuits, improving integration and allowing on-site electronics with a min-
imum of mass added to the detector system. The current trend is to include more
channels, increased processing capabilities, lower noise, and better radiation hardness,
all within the power budget available [2], [3], [4], [5]. Another interesting research
topic is to include the detector and electronics in the same die [6], [7].
A typical modern detector system for collider (particle-particle) experiments is
cylindrical shaped. The cylinder axis coincides with the beamline, and different lay-
ers on the cylinder body and bases constitute different detectors, intended to detect
particles with different penetration depths or with different scatter patterns. Some de-
tector systems are designed with hermeticity in mind, capable of stopping practically
all decay products from a collision. Hermetic detectors consist of: a tracking cham-
ber, which is the innermost region of detector, highly segmented to detect particle
trajectories; an electromagnetic calorimeter, to stop and measure energy of electrons,
positrons and photons; a hadron calorimeter to stop and measure energy of hadrons;
and a muon chamber to detect muons. Since neutrinos can travel long distances with-
out interacting with matter, including the detectors, their presence is inferred from
energy imbalance.
4 CHAPTER 1. INTRODUCTION
Figure 1.3: BaBar detector at SLAC. Reprinted from SLAC website, 2011.
Each layer in the detector system can have thousands of pixels or channels (a high
level of segmentation, [8]), providing better spacial resolution and noise performance.
The entire detector system is subject to a strong magnetic field provided by an en-
closing magnet, which curves the path of charged particles and makes it possible to
infer momentum and charge from the radius of curvature. Figure 1.3 is a photograph
of the BaBar particle detector at SLAC during its construction.
Only a small percentage of all particle collisions will produce the most elusive
particles. To improve the odds, particle physics experiments are conducted at very
high collision rates (MHz) and during very long periods (months). The beam consists
of bunches of particles arranged in pulse trains, with a high pulse rate during the
short, active part of the cycle, followed by a longer, silent period. Data captured from
collision outcome is continuously generated by the detectors and analyzed statistically
in a computer network.
The main topic of this thesis, and an important component of all contemporary
detector systems for particle accelerators, is the front-end electronics integrated circuit
(IC), needed to acquire, filter and deliver the information of collisions captured by the
detector array. Important considerations and tradeoffs in the IC design are electronic
1.2. ELECTRONICS FOR PARTICLE PHYSICS EXPERIMENTS 5
noise, power, collision rate, resolution, and input range. Particularly, electronic noise
represents the fundamental limit for resolution, whereas power and collision rate play
a role in the noise limits.
This thesis deals with the design and characterization of a front-end ASIC for one
of the detectors planned for the International Linear Collider (ILC), a next generation
linear collider. Additionally, an extension for the classic noise analysis methodology
in particle physics experiments is presented, in an attempt to provide a better under-
standing on noise - power - collision rate tradeoffs and allow simpler analysis when
switched-capacitor circuits are involved.
In this chapter, the various blocks in a typical front-end electronics IC for high
energy physics experiments are briefly described. After that, current trends in noise
minimization in front-end electronics for particle physics experiments are reviewed.
Finally, the contents of this thesis are summarized.
1.2 Electronics for particle physics experiments
In this section, a brief review on electronics for particle physics experiments is pre-
sented. The topics covered are typical architectures, detector technologies, charge
amplifiers, pulse shapers and memory arrays. The scope is merely introductory, in-
tended for readers with no background in particle physics.
1.2.1 Instrumentation for particle physics experiments
A typical particle physics experiment detector system contains different layers of
detectors, each of which is usually highly segmented into a multichannel array. A
single channel of a certain layer includes a detector, an amplifier, a filter, a buffer,
an analog-to-digital converter (ADC), and a readout circuit [8]. Figure 1.4 shows a
highly simplified block diagram for a generic detector channel. In some cases, the
analog-to-digital converters (ADCs) are shared among a number of channels in the
same detector or layer. There are also calibration circuits, which inject a known signal
– usually the output from a digital-to-analog converter (DAC) – into each channel
6 CHAPTER 1. INTRODUCTION
DetectorParticle Amplifier Filter ADCBuffer Readout
Figure 1.4: Block diagram for a single channel, generic instrumentation circuit forparticle physics experiments.
input in order to map nonlinearities and imperfections in the circuit transfer function.
Having a known transfer function for every single channel allows digital correction of
the raw data read out from each channel.
1.2.2 Detector technologies
Many technologies are, or have been, used in radiation detection: photographic film,
ionization chambers, scintillation counters, semiconductor detectors, etc. The in-
tention of this subsection is to provide a brief introduction to some of the detector
technologies used in particle physics experiments; more detailed information is pre-
sented in [9], [10].
• Ionization chambers: A chamber is filled with a gas, and a high voltage
potential is applied through two electrodes. When a particle crosses through
the chamber, it ionizes the gas. Ionized gas molecules drift to the electrodes,
producing a measurable current pulse. Some ionization chambers amplify the
small signals using avalanche processes. A common example of a single-channel
ionization chamber detector system is a home smoke detector.
• Scintillation counters: Certain materials scintillate, or temporarily glow,
when a particle or electromagnetic wave passes through them. The detection of
this light pulse allows determining when a particle crosses through the material.
Zinc sulfide (ZnS) was used by Ernest Rutherford in his famous experiments
[11].
• Semiconductor detectors: An incident photon or particle provides energy
to lightly bound electrons in the crystal lattice, producing electron-hole pairs.
1.2. ELECTRONICS FOR PARTICLE PHYSICS EXPERIMENTS 7
These charge carriers drift due to an external electric field, producing a short
current pulse, with the measured signal coded as total pulse charge. Semicon-
ductor detectors are simply reverse-biased diodes, and can be tailored according
to specific needs, for example, to produce avalanche amplification, or to reduce
leakage and increase the effective detector volume by using an insulator (un-
doped) silicon layer between the P and N regions (PIN diode).
• Cerenkov Detectors: Measure particle velocity through the detection of
Cerenkov radiation.
Detectors can also be classified according to their purpose. For example, calorime-
ters measure the kinetic energy of particles. This is done by stopping the particle
within the calorimeter structure, and detecting the signal generated in the process.
As the particle’s total kinetic energy is lost in the calorimeter, the signal produced
is proportional to the particle energy before entering the calorimeter. Trackers and
vertex detectors, on the other hand, are designed to detect particle trajectories; in
this case, a dense segmentation is preferred, as it provides high spatial resolution.
1.2.3 Amplifier
The initial amplifier in a front-end IC for particle physics experiments, also called
preamplifier, transforms the detector charge signal into a voltage; therefore, the am-
plifier transfer function is in units of V/C or F−1. Although a simple resistor could
do the job by discharging the diode capacitance and producing a transient voltage,
there is a fundamental limitation for this circuit’s performance: if the resistor is small,
the voltage will also be small and comparable to the noise floor; on the other hand,
if the resistor is large, the time constant associated with the components will limit
the amplifier’s bandwidth. Moreover, the noise associated with the resistive element
would be intolerable.
A preamplifier transfers the charge from the nonlinear capacitance of the detector
to a linear, known capacitor. In this case, the measured voltage will be simply
V = Q/C, with C easily and precisely tailorable. This improves the circuit precision
8 CHAPTER 1. INTRODUCTION
Vout
C
D
Figure 1.5: Charge-sensitive amplifier using common-gate stage. Biasing has beenpurposely omitted. This circuit transfers the charge generated in the photodiode tothe capacitor.
Vout
C
D
Figure 1.6: CSA using a voltage amplifier. This circuit transfers the charge generatedin the photodiode to the feedback capacitor.
and speed, but requires active components to transfer the detected charge to the
linear capacitor. One way of doing this is by using a transistor in common-gate
configuration, as shown in Figure 1.5, where biasing has been omitted. This would
meet the objective, but the settling time would be slow as VGS is reduced when the
detector capacitance is discharged. A better, more common preamplifier consists of
a voltage amplifier with a capacitor in negative feedback configuration, as shown
in Figure 1.6. The resulting feedback circuit is a charge-sensitive amplifier (CSA),
extensively studied in the literature related to topics such as imagers and particle
physics instrumentation [7], [12], [13], [14], [15], [16], [17], [18], [19]. A differential-
input operational amplifier with a proper feedback network can be employed for
this purpose, but in practice, a single-ended amplifier is often used. Single-ended
amplifiers offer a reduced input-referred noise and power dissipation, but must be
AC-coupled to the detector.
1.2. ELECTRONICS FOR PARTICLE PHYSICS EXPERIMENTS 9
1.2.4 Filter and discriminator
The amplified detector signal includes noise from the detector and the amplifier. Al-
though the noise is a random signal in the time domain, its frequency behavior is well
modeled and may be used to design a filter, also named pulse shaper, that maximizes
the signal-to-noise ratio. Usually the filter is an analog block, either time-invariant or
time-varying, that shapes the amplified charge into a voltage pulse. The pulse shape
defines the weights of white series, white parallel and flicker series noise sources on the
front-end output noise. This is why, in particle physics instrumentation, the words
pulse shaper and filter are used to mean the same thing.
Depending on the nature of the experiment and the energies involved, only a
fraction of the channels will be subject to the effect of scattered particles or photons
for each collision or event. The non-excited pixels will detect and amplify noise, which
is not useful for post-processing and should not be read out. In order to consider only
relevant signals, a threshold-based discriminator is typically used. The discriminator
only allows those signals with amplitudes within a defined window to be read out,
discarding the rest. The window limits can be programmed using DACs.
1.2.5 Memory arrays
A memory acts as a buffer necessary to store data for a number of events before
readout. For high-frequency pulse trains, analog memory is particularly well suited.
Filtered signals can be quickly stored as charge in integrated metal-insulator-metal
(MIM) or metal-oxide-semiconductor (MOS) capacitors, to be converted into digital
signals by dedicated analog-to-digital converters during the readout phase. In this
case, capacitor size is an important design variable, as it will determine the kT/C
noise value.
Integration and feature size reduction has allowed the design of highly dense digital
memory arrays. If a digital memory is used instead, ADCs are used to digitize the
signal prior to storage, and conversion throughput per IC must be as high as the
collision rate times the number of channels. This can be done using a single, fast
ADC or several slower ADCs.
10 CHAPTER 1. INTRODUCTION
1.3 Current trends in noise minimization for par-
ticle physics instrumentation systems
As mentioned earlier, electronic noise sets the fundamental limit for the measurement
resolution [6]. Reaching the desired noise levels while maintaining a low power con-
sumption and a high operating frequency represents the main design challenge in a
front-end electronic circuit for particle physics experiments. For this reason, under-
standing and designing for low noise is one of the main concerns in this work. In this
section, a brief review of previous work on noise minimization for particle physics
experiments is presented.
Modern papers on noise analysis for particle physics instrumentation systems date
from the late 60’s, appearing mainly in two journals, the IEEE Transactions on
Nuclear Science (TNS) and Nuclear Instruments and Methods in Physics Research,
Section A (NIM).
In 1968, important concepts of pulse shaping for particle physics experiments were
described in [20]. At this time, the search of practical optimum shapers and simpler
analysis methods were the main concerns. It was well known that the cusp function
was the theoretical best impulse response for the overall system in order to obtain
maximum signal-to-noise ratio (SNR). The concept of a weighting function (equivalent
to impulse response, but valid for time-varying systems as well) was introduced.
In 1972, an interesting time-domain analysis technique was published [21], for
comparing the filtering effects of different pulse shapers. Starting from simple ob-
servations and assuming only white noise, it was shown that all the noise sources
can be reduced to two components: step noise and delta noise. Integration of each
component in frequency allows characterization of the noise-filtering capabilities of a
pulse shaper (filter) simply by two noise coefficients, independent of the time scale.
Although this technique did not consider low-frequency noise, it allowed for a simple
characterization of noise. These ideas are still in use today, and the paper where they
were published is one of the most influential and cited papers about noise for particle
physics experiments.
In 1984, a good review and some examples of readout electronics techniques for
1.3. NOISE MINIMIZATION IN CIRCUITS FOR PARTICLE PHYSICS 11
semiconductor detectors in particle physics instrumentation systems was published
[22]. The author emphasized the importance of the input stage of the front-end
electronics in the overall noise performance. By that time, there was already some
interest in MOS technology (with lower performance than JFETs or MESFETs) due
to the potential of integrating the semiconductor detector and its electronics.
In the same year, a good summary of semiconductor position-sensitive detectors
was also published [23]. In that paper, it was shown that the minimum noise is
achieved when the detector and amplifier input capacitances are matched.
In 1988, one of the most influential papers on low-noise techniques for particle
physics instrumentation was published in Annual Review of Nuclear and Particle
Science [24]. In this survey paper, the results from previous work on noise were sum-
marized. The conclusions are consistently the same: for minimum noise, maximum
available power and capacitance matching must be used. This became the rule of
thumb for low-noise circuit design in particle physics experiments, in both JFET and
MOSFET technologies.
Flicker noise research in particle physics electronics was described in 1989 [25].
Before this paper, low-frequency noise was rarely mentioned and seldom considered
in the analysis of particle physics electronics.
In 1990, the issue of optimum shapers for particle physics electronics, including
low-frequency noise in the analysis, was addressed [26]. The same year, an excellent
derivation of noise for particle physics front-end electronics, including thermal, flicker
and shot noise sources was presented [27]. In that publication, a section on optimal
(noise-wise) design of charge amplifiers is shown; numeric techniques are necessary to
achieve a solution.
In 1998 [28], for the first time the contribution of the low-frequency noise was
computed in the time domain, using fractional derivatives. It is an extension of
earlier noise computation methods [21].
In 2001, a nice overview of front-end electronics for imaging detectors, oriented
to particle physics applications was published [6]. In that work, neat and simple
equations to compute the equivalent noise charge from white, flicker and shot sources
were presented. The same equations are employed in a later publication [13], where
12 CHAPTER 1. INTRODUCTION
it is shown that, using more accurate transistor and noise models, minimum noise is
not necessarily achieved when maximum available power and capacitance matching
conditions are fulfilled. It is also shown that the low-frequency noise contribution
may depend on the shaper time constant, a result not found before using simpler
equations.
Finally, excellent books on particle physics instrumentation systems have been
published [8], compiling and explaining the results from many papers in the field.
1.4 Thesis content
Chapter 2 includes a system-level overview of the detector system studied in this the-
sis, and presents the required specifications for the instrumentation ASIC. Chapter 3
presents the basics of noise theory, with emphasis on the definitions and mathemat-
ics required by this work. In Chapter 4, the ASIC system-level design is presented,
including the noise analysis that led to the final version. Chapter 5 shows the circuits
and the design process behind them. In Chapter 6, practical aspects of the circuit
layout and implementation are presented. In Chapter 7 the results obtained from
experimental testing are presented, analyzed and compared against the expected re-
sults. Chapter 8 summarizes the conclusions derived from this work, and presents
ideas that could be investigated in this research area.
Chapter 2
Problem Definition
2.1 The International Linear Collider
The custom integrated circuit described in this work is the front-end for one of the
detector systems of the International Linear Collider (ILC) [29]. Planned to be oper-
ating in the late 2010’s, the ILC will be the largest linear collider ever built, with a
length between 30 km and 50 km. The intended beam energy is 500GeV for the first
stage, and twice as much after a planned upgrade.
As a colossal international project, planning the ILC is a tremendously difficult
task, currently in hands of the Global Design Effort (GDE) for the ILC [30]. Although
the main specifications are roughly defined, some details – including the location of
the ILC – still remain unclear. For this reason, the requirements for the detection
circuit that is the subject of this research are still preliminary.
The ILC will collide electron and positron clusters or bunches on a beamline ac-
cording to the scheme shown in Figure 2.1. Electrons and positron bunches, spaced by
308 ns, travel at nearly the speed of light to collide against each other. Each collision
produces decaying particles and energy bursts according to the time diagram shown
in the same figure. During 0.87ms, 2820 evenly-spaced collisions occur, followed by
a 199-ms silent (collision-free) period. This pattern repeats indefinitely.
13
14 CHAPTER 2. PROBLEM DEFINITION
t (ms)0 1 200 201
0.87 ms, 2820 bunches>199 ms,collision-free
308 ns
Bea
mlin
e
CollisionPoint
ElectronBunches
PositronBunches
0.87 ms, 2820 bunches
50
>199 ms, collision-free
50ms1Mbitreadout
50ms1Mbitreadout
Figure 2.1: Pulse train structure. Each collision produces decaying particles andphotons that excite the detectors; the time diagram shows the collision timing.
2.2 The ILC forward calorimeter
The ILC detector system is roughly a cylinder-shaped detector with a radius of 6.45m,
and it consists of several sub-systems. Located at the cylinder bases or end caps, the
ILC Forward Calorimeter [31] will improve the detector hermeticity, necessary in the
search of new particles [32]. The forward calorimeter has four detectors in each cap:
the BeamCal, the LumiCal, the GamCal and the Pair Monitor. Figure 2.2 shows
a cross section of the International Linear Detector (ILD) concept, one of the two
validated detector designs for the ILC.
The BeamCal detector is an electromagnetic calorimeter made of 30 layers of
detectors interleaved with tungsten disks. Its three main purposes are: to extend
the ILC forward calorimetry to small polar angles, to reduce the backscattering from
pairs into the detector center, and to provide a low-latency luminosity signal for beam
diagnostics [33]. Figure 2.3 shows the BeamCal detector structure.
2.2. THE ILC FORWARD CALORIMETER 15
Figure 2.2: ILC detector’s cross section. The BeamCal is marked as BCal. Reprintedfrom the FCAL Collaboration website, 2008.
Figure 2.3: BeamCal structure. Adapted from the FCAL Collaboration website,2011.
16 CHAPTER 2. PROBLEM DEFINITION
2.3 BeamCal instrumentation ASIC specifications
Because of its location near the beamline, the BeamCal detector will be subject to
an enormous amount of energy in each collision. That energy provides important
information on the collision outcome, and therefore must be recorded for all collisions
(100% expected occupancy1). For the pixel sizes and quantum efficiencies considered,
the maximum input charge deposited on each pixel will be nearly 40 pC, and the
required instrumentation resolution is 10 bits. The ADC resolution was established
from science considerations, targeting 10MIP2 per LSB.
Besides the standard data taking (SDT) operation, an additional mode of oper-
ation is required for detector calibration (DCal) purposes. The detector calibration
mode makes it possible to determine the detector quantum efficiency by measuring
the instrumentation ASIC output for input pulses of known energy. Calibration can
be done periodically, in order to digitally compensate for the detector degradation in
a high-radiation environment. Because of the reduced input pulse energy, the cali-
bration mode must have a gain 50 times higher than that for standard data taking.
For the magnitude of the input signals in this calibration mode, low-noise design is
an important aspect.
The BeamCal detector will have 1,512 unit detectors in each layer, totaling 45,360
detectors in each end cap. Each instrumentation ASIC will be able to handle 32 chan-
nels. Therefore, 2,836 ASICs are necessary to cover the full detector instrumentation
needs. Each pixel will have a capacitance of about 20 pF.
The short time between bunch crossings, the high segmentation, and the expected
occupancy make it unfeasible to read out the data between bunch crossings. The only
time available for readout purposes is the 199-ms silent time between pulse trains,
and therefore, on-chip memory must be considered to store the acquired data before
readout.
1Occupancy is the fraction of channels that register a relevant stimulus on each collision.2The ionization density caused by the passage of a charged particle through matter is a function
of the particle’s momentum. This function exhibits a characteristic minimum around momentaof 1GeV/c, where c is the speed of light in vacuum. Particles exhibiting such a momentum areinformally referred to as Minimum Ionizing Particles (MIPs). A MIP represents the smallest signalthat a detector can detect.
2.3. BEAMCAL INSTRUMENTATION ASIC SPECIFICATIONS 17
Input rate 3.25MHz during 0.87ms, repeated every 200msChannels per ASIC 32Occupancy 100%Resolution 10 bits for individual channels, 8 bits for fast feedbackModes of operation Standard data taking (SDT), Detector Calibration (DCal)Input signals 37 pC in SDT, 0.74 pC in DCalInput capacitance 40 pF (20-pF detectors and 20-pF wires)Additional feature Low-latency (1µs) outputAdditional feature Internal pulser for electronics calibrationRadiation tolerance 1Mrad (SiO2) total ionizing dosePower consumption 2.19mW per channelTotal ASIC count 2,836
Table 2.1: BeamCal instrumentation ASIC specifications summary.
One of the main purposes of the BeamCal detector is to provide a fast feedback
(low latency) luminosity signal for beam diagnostics and tuning. The fast-feedback
output from each instrumentation ASIC corresponds to the total energy processed by
the ASIC. Therefore, the instrumentation ASIC must provide a low-latency (< 1µs),
8-bit output consisting of the sum of the outputs of all 32 channels after each bunch
crossing.
The instrumentation ASIC must also feature an electronic calibration system, ca-
pable of injecting known signals into each channel, in order to determine the channel’s
transfer function and allow post-processing calibration.
The BeamCal detector will be subject to harsh radiation conditions of 10MGy
per year because of depositions of beamstrahlung remnants [31]. Protected behind
shields, the BeamCal instrumentation ASICs must tolerate a radiation of 1Mrad
(SiO2) for a 10-year lifetime. A radiation-tolerant design may be necessary to achieve
this objective. The wires between the detectors and the ASICs behind the shielding
will increase each channel input capacitance by 20 pF.
Table 2.1 summarizes the BeamCal instrumentation ASIC specifications.
Chapter 3
Noise Analysis in Pulse Detectors
for Particle Physics Experiments
In this chapter, the fundamentals of noise analysis for particle physics instrumentation
systems are introduced. The analysis methods provide the required insight for a
design-oriented perspective. The first sections compile what has been established as
the classic noise analysis methodology for particle physics instrumentation systems,
and is intended as a link to particle physics experiments electronics for readers with
a solid background in electronic design. Section 3.2 combines the analysis with the
gm/ID methodology for MOSFET-based charge-sensitive amplifiers (CSAs). Section
3.3 shows the noise minimization techniques for particle physics instrumentation, and
Section 3.4 presents the application of the methodology in the noise analysis where a
switched-capacitor filter is involved.
3.1 Classical noise analysis in pulse processors
Any noisy circuit can be represented by a noise-free circuit with external noise gen-
erators [34]. In a linear circuit, the noise generators from all noisy elements can be
referred to a single port of the circuit (e.g., the circuit’s input port), and represented
by a combination of a series voltage noise generator and a parallel current noise gener-
ator, as shown in Figure 3.1. These noise generators are characterized by their power
18
3.1. CLASSICAL NOISE ANALYSIS IN PULSE PROCESSORS 19
Linearcircuit
Vn2
In2
Figure 3.1: Equivalent representation of a linear circuit’s internal noise sources, re-ferred to a single port.
spectral densities V 2n (f) and I2n(f). The integral over the circuit bandwidth yields
the circuit’s noise power, and the square root of this result is the noise RMS value.
Referring a noise source to one of a circuit’s ports is done through the correspond-
ing circuit’s transfer function’s squared magnitude |Hi(jω)|2. The superposition of
noise contributions is applied in quadrature. However, if there is correlation between
noise sources, a correlation factor must be considered.
3.1.1 Noise models
There are three sources of electronic noise in MOSFET devices: shot noise, due
to gate leakage current, channel noise, which is a combination of thermal and shot
noise components, weighted according to the channel inversion level, and flicker or
1/f noise, due to the action of charge carrier trap-release process in the gate-oxide
interface [35] [8] [36] [37] [24].
When in strong inversion, MOSFET transistors present a single-sided thermal
noise power spectral density of
I2D,T = 4 · k ·T · γ · gm, (3.1)
where I2D,T is the drain current thermal noise power spectral density, k is the Boltz-
mann constant, T is absolute temperature, γ is a coefficient with a value of 2/3 for
long-channel devices and approximately 1 for short-channel devices [38], and gm is
the transistor transconductance. Referred to the transistor’s gate-to-source voltage,
the device noise can be expressed as
20 CHAPTER 3. NOISE ANALYSIS IN PULSE DETECTORS
V 2GS,T =
4 · k ·T · γ
gm. (3.2)
In subthreshold operation, the MOSFET transistor operation resembles that of a
bipolar transistor, and the noise equation changes accordingly. Equation 3.3 expresses
the MOSFET channel shot noise single-sided power spectral density in subthreshold
operation.
I2D,S = 2 · q · ID (3.3)
The above channel noise models are adequate for hand analysis. Computer simu-
lation programs consider more accurate equations, such as those in the BSIM3 models
[39]. The BSIM3 model covers a wider range of device operation [40].
I2D,S =4 · k ·T
RDS + L2eff / (µeff |Qinv |)
(3.4)
In this equation, Qinv is the inversion charge in the channel.
Flicker noise (low-frequency noise, pink noise) is not very well understood. It is
known that flicker noise appears in a variety of systems of different nature, such as
a resistor, the flow of the river Nile and the luminosity of stars [41]. In MOSFET
devices, it is due to the traps in the gate’s SiO2 − Si interface, which capture and
release carriers in a random fashion. The larger the transistor size, the more averaged
the charge trapping-release process, and the smaller the flicker noise. Two alternative
equations are used to model flicker noise in SPICE, which can be selected in HSPICE
using the NLEV parameter. If NLEV = 0, the drain current referred MOSFET flicker
noise power is given by Equation 3.5. If NLEV = 2 or 3, the drain current MOSFET
flicker noise power is represented by Equation 3.6 [42].
I2D,F =KF · IAF
D
Cox ·L2eff · f
(3.5)
I2D,F =KF · g2m
Cox ·Weff ·Leff · fAF
(3.6)
3.1. CLASSICAL NOISE ANALYSIS IN PULSE PROCESSORS 21
In these two equations, KF is the flicker noise coefficient, with different dimensions in
each equation, and values in the range 1× 10−19V2F to 1× 10−25V2F for Equation
3.6. AF is the flicker noise exponent, typically close to 1. Cox is the oxide capaci-
tance per unit area, and Weff and Leff are the transistor’s effective width and length.
There is a widely-used variant of Equation 3.6 in which Cox appears squared in the
denominator. In this case, KF must be modified accordingly.
The BSIM3 flicker noise model, used in SPICE simulations when the parameter
NOIMOD is set to 2, 3 or 6, has two different equations, one for strong inversion and
the other for subthreshold operation. Each of these equations is quite complex and
involves several terms. For simplicity, in the equations shown below, for strong inver-
sion, the constant terms have been lumped into the parameters WA and WB.
I2D,F =q2kTµeff IDS
CoxL2eff f
EF108·WA +
(kT/q)I2DS∆Lclm
WeffL2eff f
EF108·WB (3.7)
The equation for subthreshold operation is the “electric parallel” between Equa-
tion 3.7 and the equation for weak inversion, namely:
I2D,F =NOIA · (kT/q) · I2DS
WeffLeff fEF4 · 1036(3.8)
In present MOSFET technologies, PMOS devices have lower flicker noise power
than NMOS devices [43], thus PMOS devices are usually preferred as input transistors
in charge amplifiers [13].
3.1.2 Equivalent noise charge
A fair comparison of noise behavior among different front-ends is possible if the total
system noise is referred to the input. In the case of particle physics electronics, the
input’s fundamental nature is charge, so it is natural to express the system noise as
equivalent noise charge (ENC), measured in number of electrons. The ENC is defined
as the number of electrons of input charge that produces an output signal-to-noise
ratio of 1. Typical numbers for ENC are between 10 and 1000 electrons, depending
on the system.
22 CHAPTER 3. NOISE ANALYSIS IN PULSE DETECTORS
A(jω) H(jω)CgsCD
CF
Vo(t)
+−
ID2
IAmp2
VAmp2
RR
−
+
Figure 3.2: Schematic for noise analysis. Two noise sources are considered: detectorshot noise and amplifier noise, represented as voltage and current noise. This includesboth, white and flicker noise.
The typical front-end in particle physics experiments consists of a detector, a
small-signal model for which is a capacitance CD in parallel with a current source; a
charge-sensitive amplifier, modeled as a voltage amplifier of gain A(jω) with input
capacitance Cgs and a feedback capacitor CF ; and a filter (noise shaper or pulse
shaper) with transfer function H(jω). Shot noise from the detector, and voltage and
current noise sources from the amplifier are considered. A simplified schematic for
noise analysis in a typical particle physics instrumentation system is shown in Figure
3.2. Note it is assumed that the input impedance of the amplifier is dominated by
the gate-to-source capacitance (Cgs) of the input transistor.
Resistor RR across the feedback capacitor CF represents the CSA reset element,
which can be gated or continuous. The effect of the reset element during the relatively
short time that it takes the CSA to produce an output voltage is negligible. Thus, in
the following analysis, RR can be assumed to be infinite.
Current pulses sensed at the CSA input node are integrated in the feedback ca-
pacitor. Once settled, this produces an output voltage step proportional to the input
charge, according to the approximate expression
Vstep =Qin
CF
(3.9)
The ENC for the circuit in Figure 3.2 can be computed as the square root of the
ratio between the total output noise power and the output power produced by a single
electron of charge, without including the circuit’s noise sources.
3.1. CLASSICAL NOISE ANALYSIS IN PULSE PROCESSORS 23
ENC ≡
√
√
√
√
V 2Nout
V 2electron
(3.10)
In order to simplify the ENC analysis, it is assumed that the amplifier gain and
bandwidth are very large. In fact, the gain must be large in order to reduce the
feedback error, and although the bandwidth is finite, the amplifier output is usually
fed to a lower bandwidth filter. Thus, the assumption of high gain and bandwidth is
valid. Also, it is assumed that the noise of the amplifier is dominated by the input
device and that the amplifier’s input impedance is dominated by the gate-to-source
capacitance (Cgs) of the input transistor. Under these assumptions, it can be shown
that [27] the CSA output noise power due to the amplifier’s input-referred noise power
is simply
V 2nCSA(jω) =
(Cgs + CF + CD)2
C2F
·V 2Amp(jω). (3.11)
The amplifier output is processed by the filter, with transfer function H(jω),
producing the front-end output voltage. The filtered amplifier noise is then
V 2o,Amp(jω) =
(
Cgs + CF + CD
CF
)2
· |H(jω)|2 ·V 2Amp(jω). (3.12)
The front-end output noise power due to detector shot noise can be computed as
V 2o,Det(jω) =
I2Det
|ωCF |2· |H(jω)|2 . (3.13)
Since shot noise is white, I2Det does not depend on frequency.
Because, during normal operation, the front-end input is a step of charge, it is
more convenient to express the ENC equations in terms of the filter step response.
Let G(jω) = H(jω)/jω, the Fourier transform of the filter step response. Then,
Equations 3.12 and 3.13 can be rewritten as:
V 2o,Amp(jω) =
(
Cgs + CF + CD
CF
)2
· |ω ·G(jω)|2 ·V 2Amp(jω) (3.14)
24 CHAPTER 3. NOISE ANALYSIS IN PULSE DETECTORS
V 2o,Det(jω) =
I2Det
C2F
· |G(jω)|2 (3.15)
Adding Equations 3.14 and 3.15 and integrating the result over frequency, the
front-end integrated output noise power due to amplifier and detector noise is com-
puted as
V 2o,noise =
1
2πC2F
∫ ∞
0
(
|G(jω)|2 I2Det + (Cgs + CF + CD)2 |ωG(jω)|2 V 2
Amp(jω))
dω.
(3.16)
In order to compute ENC, it is necessary to find the front-end output voltage
due to a unit of input charge. From Figure 3.2, the front-end time-domain response
to a single-electron input charge q is Vo(t) = (q/CF ) · (h(t) ∗ u(t)), where u(t) is the
Heaviside function and ∗ is the convolution operator. This is equivalent to Vo(t) =
q · g(t)/CF , where g(t) is the inverse Laplace transform of G(s). The output voltage
is a continuous variable, and in order to maximize the signal-to-noise ratio, it is
measured at the peaking time, or the time where g(t) is maximum. Thus the ENC 2
can be computed as Equation 3.16 divided by q2 ·max(g(t))2/C2F , producing
ENC 2 =1
2π
∫∞0
(
|G(jω)|2 I2Det + (Cgs + CF + CD)2 |ωG(jω)|2 V 2
Amp(jω))
dω
q2 |max(g(t))|2. (3.17)
Equation 3.17 shows that series noise is proportional to the total capacitance at
the input node CTot = Cgs +CF +CD. It also shows that the amplifier input-referred
series noise power spectral density V 2Amp(jω) can be effectively attenuated by the
filter, which has a unit step response of g(t). The amplifier input-referred noise power
spectral density V 2Amp(jω) can be computed or measured, and may include white and
low-frequency components. The filter step response g(t) is usually characterized by a
peaking time τp, defined as the time between the input charge and the step response
maximum value.
3.1. CLASSICAL NOISE ANALYSIS IN PULSE PROCESSORS 25
3.1.3 Noise coefficients
A closer look into Equation 3.17 reveals that the integrals can be simplified if the
terms that do not change with frequency are represented as constant factors. The
detector noise power spectral density can be directly removed from the integral, but
the amplifier series noise has a frequency-dependent power spectral density. In order
to split the analysis into smaller parts, V 2Amp(jω) can be decomposed into its white
and low-frequency components:
V 2Amp(jω) = V 2
Amp,W + V 2Amp,F (jω), (3.18)
where V 2Amp,W is the amplifier input-referred white noise component, and V 2
Amp,F (jω)
is the low-frequency noise component. The latter can be expressed as
V 2Amp,F (jω) =
∣
∣
∣
∣
∣
KF
(jω)AF
∣
∣
∣
∣
∣
, (3.19)
where KF is the flicker noise coefficient, and AF is the flicker noise exponent. Thus,
Equation 3.17 becomes
ENC 2 =V 2oDet + V 2
oAmp,W + V 2oAmp,W
2πq2 |max(g(t))|2, (3.20)
where
V 2oDet = I2Det
∫ ∞
0|G(jω)|2 dω, (3.21)
V 2oAmp,W = C2
TotV2Amp,W
∫ ∞
0|ωG(jω)|2 dω, (3.22)
V 2oAmp,W = C2
TotKF
∫ ∞
0
|ωG(jω)|2|jω|AF
dω. (3.23)
Now it is possible to define the three front-end noise coefficients for parallel (NP ),
white series (NW ), and flicker series (NF ) noise sources, which depend only on the
filter response and the flicker noise exponent. Equation 3.17 can then be rewritten as
26 CHAPTER 3. NOISE ANALYSIS IN PULSE DETECTORS
ENC 2 = C2Tot
(
NWV 2Amp,W +NFKF
)
+NP I2Det , (3.24)
where the noise coefficients are
NW =
∫∞0 |ωG(jω)|2 dω
2πq2 |max(g(t))|2, (3.25)
NF =
∫∞0
|ωG(jω)|2
|jω|AFdω
2πq2 |max(g(t))|2, (3.26)
NP =
∫∞0 |G(jω)|2 dω
2πq2 |max(g(t))|2. (3.27)
Equation 3.24 is convenient for simple noise analysis, since it partitions the noise
equations into noise contributions and noise-filtering factors. To a first order, the
latter depend only on the filter and can be tabulated for filters with different step
responses or pulse shapes.
3.1.4 Normalized noise coefficients
Further manipulation on the ENC equation yields a more perceptive form. Normal-
izing the time variable to an arbitrary time constant (e.g., the filter step response
peaking time τp), g(t) becomes g(t/τp) and G(s) becomes τpG(sτp). Thus, Equations
3.24 through 3.27 change accordingly1:
ENC 2 = C2Tot
(
NWn
τpV 2Amp,W +NFnKF
)
+ τpNPnI2Det (3.28)
NWn =
∫∞0 |ωG(jω)|2 dω
2πq2 |max(g(t/τp))|2(3.29)
NFn =
∫∞0 ω |G(jω)|2 dω
2πq2 |max(g(t/τp))|2(3.30)
1For the moment, AF will be assumed 1 to simplify the following derivations. Proper generaliza-tion in next subsection allows to revert this assumption.
3.1. CLASSICAL NOISE ANALYSIS IN PULSE PROCESSORS 27
NPn =
∫∞0 |G(jω)|2 dω
2πq2 |max(g(t/τp))|2(3.31)
From these expressions it is evident that series white noise power is reduced when the
filter time constant increases, and that parallel white noise power increases with the
filter time constant. For the assumption of AF = 1, series low-frequency noise does
not depend on the filter time constant. When there are no system-level constraints
on τp, the peak SNR of the front-end is optimized for the value of τp for which white
series and parallel noise powers are equal.
Using Parseval’s theorem on Equations 3.28 through 3.31, the noise coefficients can
be computed from the front-end time-domain response. In this time-domain analysis,
the parallel noise coefficient NPn is proportional to the integral of the front-end step
response squared (g(t))2. Since the integral argument in white series noise coefficient
includes ω2, the white series noise coefficient NWn is proportional to the derivative of
the front-end step response squared (g′(t))2. The flicker series noise coefficient NFn is
proportional to the half derivative of the front-end step response squared(
g(1/2)(t))2
[28]. Once again, it is evident that the noise contributions depend directly on the
front-end’s output pulse shape. This is the reason why in instrumentation systems
for particle physics experiments, filters are also called pulse shapers.
Parallel noise increases with the filter time constant, since the integral of the step
response squared grows with it. White series noise decreases with the pulse shape
time constant, since that implies a decrease in the pulse shape derivative. In other
words, large time derivative in the front-end step response produces large series noise
contribution. These conclusions are consistent with those from frequency-domain
analysis.
3.1.5 Noise analysis in time-varying systems
The noise analysis presented in previous section is valid for linear, time-invariant
(LTI) systems. When a linear, time-varying (LTV) system is considered, an extension
of this approach, based upon the concept of weighting function W (t), can be used.
Through the weighting function, a mathematically equivalent LTI system is obtained
28 CHAPTER 3. NOISE ANALYSIS IN PULSE DETECTORS
from an LTV system, thus allowing frequency-domain noise analysis [44]. In short,
the weighting function of an LTV system is an LTI representation of the system’s
time-domain response, with the same ENC as the original LTV system. The weighting
function idea is similar to the impulse sensitivity function (ISF) analysis methodology,
used in RF electronics for time-varying system analysis [45]. In order to understand
the weighting function methodology, the fundamentals of the noise process beyond
the statistics must be considered.
Noise in charge amplifiers arises from three different processes:
1. The discrete nature of the CSA input current. This is equivalent to current
impulses of noise at the CSA input node. Each current impulse is a transport
of a charge packet into the CSA, and consequently produces a voltage step
at the CSA output. This is called step noise [21], and the best examples are
the detector’s dark current and the input device’s gate current. Both give rise
to shot noise. Since the spectrum of an impulse is white, the step noise power
spectral density does not depend on frequency, and its amplitude is proportional
to the rate of current impulses.
2. The discrete nature of the amplifier’s current. This is translated to input-
referred voltage impulses of noise, which produce filtered pulses at the CSA
output. A voltage impulse can be modeled as a voltage step followed by a
negative voltage step. This noise source is called delta noise [21]. The power
spectral density of the voltage impulses is white, and its amplitude depends on
the rate at which noise voltage impulses appear.
3. Charge release from traps in the gate oxide. Each trap produces a stationary
random telegraph signal (RTS) at rate λ, with 1/f 2 noise power spectral den-
sity. The superposition of the effect of different traps with different values of λ
produces a nearly 1/f noise power spectral density [46].
In summary, the CSA noise can be explained in time domain as random unit
impulses from voltage and current white noise generators (constant power spectral
3.1. CLASSICAL NOISE ANALYSIS IN PULSE PROCESSORS 29
density component), and a superposition of random telegraph signals produced by
the voltage noise generator (1/f power spectral density component).
The front-end output signal and output noise are sampled by the ADC at a sam-
pling instant τm. The noise sample has contributions from individual noise events
occurring prior to the measurement time, weighted by their corresponding effects on
the front-end output at the measurement time. In order to quantify the contributions
of individual noise events on the front-end output according to their time of occur-
rence, the weighting function concept is used [20]. The weighting function W (t) is
defined as the front-end output, measured at the measurement time τm, for a unit
input impulse of current occurring at time t. In a causal system, W (t) = 0 for t > τm.
In an LTI system, W (t) = g(τm − t), this is, the time-reversed and shifted version of
g(t).
The front-end output noise power is proportional to the integral of input noise
pulses contributions at measurement time τm. Therefore, noise coefficients can be re-
lated to W (t) through the following equations, where the link with frequency-domain
analysis through Parseval’s theorem is evident:
NWn =
∫∞0 |W ′(t)|2 dt
q2 |max(W (t/τp))|2, (3.32)
NFn =
∫∞0
∣
∣
∣W (1/2 )(t)∣
∣
∣
2dt
q2 |max(W (t/τp))|2, (3.33)
NPn =
∫∞0 |W (t)|2 dt
q2 |max(W (t/τp))|2. (3.34)
It can be concluded from Equation 3.32 that weighting functions that have a large
time derivative produce a large series noise coefficient NWn .
The effect of a steep weighting function in the noise coefficient can be explained
intuitively. A series noise input impulse can be thought of as a step doublet, a series
of two noise steps, one positive and one negative [21]. When the weighting function is
rather flat, the contributions from both steps are mutually subtracted, because they
are subject to a similar attenuation at τm, producing a low output noise. However,
30 CHAPTER 3. NOISE ANALYSIS IN PULSE DETECTORS
if the weighting function is steep, it splits the doublet [44]. Consequently, the noise
steps are weighted differently because they are subject to different values of W (t).
The subtraction of the results from the two adjacent steps produces a non-negligible
baseline2 fluctuation.
One way to get a step in the weighting function is by means of a reset mechanism
at the front-end. The reset itself will eliminate any noise contribution at the front-
end output, thus the weighting function evaluated at the reset time is zero. At the
time when the reset is released, a sudden increase in the weighting function occurs.
The sudden increase of the weighting function from the reset time to amplification
time splits noise doublets that occur during the reset-release time, shifting the CSA
baseline to a random value. The baseline voltage shift is a DC value, easily corrected
by correlated double sampling (CDS) or autozeroing (AZ) techniques.
3.2 gm/ID extension of noise analysis
The complexity of transistor behavior in submicron CMOS technologies has rendered
square-law models useless for precise large-signal circuit analysis. Modern circuit sim-
ulators such as SPICE rely on more precise models based on both physical principles
and empirical parameters. Although excellent for numerical analysis, these models do
not offer the insight into device behavior of simpler models. A few attempts have been
made to create models complex enough for analysis and simple enough for intuitive
design [47], but these still rely on equations that may require continuous updates as
the models become more complicated.
The gm/ID methodology [48] [49] [50] is an attempt to overcome the model lim-
itations by using SPICE to compute the transistor’s small signal parameters under
controlled conditions. The SPICE simulation results are compiled in tables that re-
late the transistors’ per-width variables such as capacitance, transconductance and
current. The results can be interpolated and scaled to estimate the small-signal pa-
rameters of a wide range of transistor sizes operating at different currents.
2The baseline is defined as the CSA DC output voltage after reset, when no input has beenapplied.
3.2. GM/ID EXTENSION OF NOISE ANALYSIS 31
As suggested in early works on the topic [48], the gm/ID methodology can be ex-
tended for noise analysis. However, since the noise models in Equations 3.1 through
3.8 are not expressed as functions of gm/ID or transistor current density, a normaliza-
tion is required. The normalization consists of multiplying the gate-referred transis-
tor voltage noise power spectral density by the drain current, producing a normalized
noise Sn that only depends on per-width values3, such as gm/ID. The results for
thermal, flicker and shot noise (for weak inversion operation) are shown in Equations
3.35, 3.36, 3.37 and 3.38. The normalized noise power spectral density dimensions
are Volt-Joules, with no evident meaning.
SGS ,TN = 4 · k ·T · γ ·
(
IDgm
)
(3.35)
SGS ,SN = 2 · q ·
(
IDgm
)2
(3.36)
SGS ,FN =KF
Cox ·L2eff · f
·
(
IAF+1D
g2m
)
(3.37)
SGS ,FN =KF
Cox ·Leff · fAF
·
(
IDWeff
)
(3.38)
The normalized noise dependence on per-width values holds for more complicated
models, such as the BSIM3. As an example, normalized versions of some BSIM3 equa-
tions are shown below. Figure 3.3 shows normalized gate-referred noise power spectral
densities for different values of gm/ID in a 0.54µm-long PMOS transistor.
SGS,TN =
(
IDgm
)
4 · k ·T
gm ·RDS + L2eff · gm/ (µeff |Qinv |)
(3.39)
SGS,FN,inv =
(
I2DS
g2m
)
·
q2kTµeff
CoxL2eff f
EF108·WA +
(
I2DS
g2m
)
·
(
IDS
Weff
)
·
(kT/q)∆Lclm
L2eff f
EF108·WB
(3.40)
3Slight modifications are necessary if the flicker noise frequency exponent AF is not exactly 1.As an example, Equation 3.5 should be multiplied by I2−AF
Dfor proper normalization.
32 CHAPTER 3. NOISE ANALYSIS IN PULSE DETECTORS
Figure 3.3: Example of normalized noise curves.
SGS,FN,sub =
(
I2DS
g2m
)
·
(
IDS
Weff
)
·
NOIA · (kT/q)
Leff fEF4 · 1036(3.41)
The normalized noise curves for different values of gm/ID can be obtained through
simple SPICE simulations. For circuit design purposes, the normalized noise can be
converted back to noise power by simply dividing the normalized noise by the device
current. Normalized noise power spectral density decreases with increasing gm/ID,
and is minimum for weak inversion operation.
3.3 Noise minimization in particle physics experi-
ments
Noise minimization in particle physics experiments involves two parts: system-level
optimization and circuit-level optimization. On the system level, it involves the def-
inition of the filter transfer function, which sets the noise coefficients in Equation
3.3. NOISE MINIMIZATION IN PARTICLE PHYSICS EXPERIMENTS 33
3.28. On the circuit level, it involves the CSA design, which sets the other terms in
the equation. Usually the noise minimization in both levels is done in parallel, since
decisions in one level affect the other.
If the filter parameters are already set (e.g., by defining a filter that matches the
series and parallel noise contributions, or that minimizes series noise over the allocated
filtering period), the CSA noise contribution can be minimized independently. If the
CSA is well designed, it can be assumed that its noise is dominated by the input
transistor’s [8] [13]. Well designed means that the contribution of other transistors
in the amplifier noise equation is small, and this can be achieved by means of a
high transconductance in the input transistor, and a low transconductance in the
load transistors. This assumption is fairly good, since the input transistor usually
accounts for 70% – 90% of the total CSA noise. This assumption simplifies the
amplifier optimization procedure, since its input-referred noise is reduced to the input
transistor’s.
Optimizing for the CSA input transistor means minimizing the input transistor
contributions in Equation 3.28. One possibility is to fix gm/ID due to system-level
performance constraints (e.g., CSA bandwidth or output swing), and fine-tune the
remaining variables. It can be shown that, for constant gm/ID in the input device,
the CSA noise minimization problem can be reduced to the objective function given
by
Fobj = Cgs(ID)
(
1 +CK
Cgs(ID)
)2
, (3.42)
where CK = CD + CF is the constant component of the input node capacitance.
The minimum noise for constant gm/ID occurs at a device current for which the
input device’s capacitance matches the constant component of the input node capac-
itance, that is, Cgs(ID) = CK [23]. This is an important conclusion from classic noise
minimization techniques for particle physics experiments, but has some caveats: a
different gm/ID, of course, implies a different current for minimum noise. Also, for
constant current, noise minimization can be achieved by moving to a different gm/ID
with lower overall noise, even though capacitance matching no longer holds.
34 CHAPTER 3. NOISE ANALYSIS IN PULSE DETECTORS
The objective function in Equation 3.42 implicitly depends on the transistor chan-
nel length. Although the minimum achievable noise typically does not change much
with channel length4, the current necessary to reach the minimum is reduced as the
transistor channel length is increased. This is because the transistor capacitance per
unit width increases with the channel length. Thus, a narrower transistor is necessary
to match the constant capacitance, and at constant gm/ID this means lower current.
Increasing the channel length too much while maintaining a constant capacitance,
however, compromises the circuit bandwidth. This is because, at constant capaci-
tance, a longer channel requires a channel width reduction. Both changes reduce the
transistor transconductance, so the transistor’s transit frequency is degraded. The
transistor is operating at a higher gm/ID, which has a lower normalized noise coef-
ficient, but also a lower fT . At some point, the transistor becomes too slow for the
required CSA bandwidth.
Current for capacitance-matching point increases with the input device’s cur-
rent density, because for the same current density or gm/ID, more capacitance im-
plies more current. Figure 3.4 shows that, if only series white noise is considered,
ENC for capacitance-matching point decreases with input device’s current density, at
the cost of additional power dissipation. This is because lower gm/ID implies lower
gm/Cgs , thus for capacitance-matching point, implies a higher gm. Since gate-referred
white noise power is inversely proportional to gm, lower gm/ID implies lower noise for
capacitance-matching point.
Flicker noise dependence on gm/ID is more complicated than that of white noise
and is very sensitive to the noise model. In order to study it, the concept of normalized
noise power will be used. As an example of flicker noise analysis as a function of gm/ID,
Equation 3.5 will be used, also assuming AF = 1. With these ideas, the objective
function related to the ENC can be simplified to
4Unless the minimum achievable noise is dominated by flicker noise, in which case noise is lowerfor longer transistors.
3.3. NOISE MINIMIZATION IN PARTICLE PHYSICS EXPERIMENTS 35
Figure 3.4: Example of ENC due to series white noise for a PMOS input device anda 41-fF constant capacitance at the input node.
Fobj2 =(Cgs + CK)
2
ID·
∫ ∞
0|H(jω)|2
(
4KTγ(
gmID
)−1
+KF
CoxLeff f
(
gmID
)−2)
dω.
(3.43)
For constant gm/ID, the minimum Fobj2 is achieved with matched capacitances,
that is, Cgs = CK . Also, knowing that the transistor’s transit frequency is ωT =
gm/Cgs , Equation 3.43 can be further manipulated to obtain:
Fobj2 =4CK
ωT
[
∫ ∞
0K1 |H(jω)|2 dω +
(
gmID
)−1 ∫ ∞
0
K2
f|H(jω)|2 dω
]
, (3.44)
where K1 and K2 are lumped constant terms.
From Equation 3.44 it is evident that, at capacitance matching point, white noise
(proportional to the first term inside the brackets) is reduced by using a transistor
biased at higher ωT , which for low-field transistor model is proportional to (gm/ID)−1.
The second term in brackets shows that the flicker noise component does not depend
36 CHAPTER 3. NOISE ANALYSIS IN PULSE DETECTORS
Figure 3.5: Example of ENC due to series white noise for a PMOS input device anda 41-fF constant capacitance at the input node.
on gm/ID, since the dependence of the term inside the integral is canceled with that
of ωT . Since the independence of flicker noise minima on gm/ID is sensitive to a
cancellation of key factors, it can be expected that when using more precise models,
valid for a wider inversion envelope, this result does not hold.
Figure 3.5 shows that, if only flicker noise is considered, ENC for capacitance-
matching point presents a minimum at a certain gm/ID. Thus, increasing the current
density does not necessarily mean better SNR. This confirms the suspicion from the
previous paragraph, about the sensitivity of flicker noise to changes on gm/ID.
As explained earlier, a lower gm/ID requires more current and therefore higher
gm for capacitance matching, which usually implies lower noise. However, the flicker
noise corner grows faster as gm/ID is reduced (Figure 3.3), and depending on the
operating point, the net effect may result on an increase of the ENC.
The combined effect of series white and flicker noise also produces a minimum ENC
for a certain current density, much higher than that for flicker noise alone (Figure
3.6). The results shown in these plots confirm that flicker noise is responsible for the
3.3. NOISE MINIMIZATION IN PARTICLE PHYSICS EXPERIMENTS 37
Figure 3.6: Example of ENC due to series white and flicker noise, PMOS input deviceand 41 fF constant capacitance at input node.
ENC fundamental lower limit [13]. It is inferred from Equation 3.44 that an analysis
on the optimal gm/ID for capacitance-matching point is equivalent to an analysis
on the relative weights of gm/ID and (gm/ID)2 in the noise equation, and how the
exponents change with ID for capacitive-matching point.
An alternative perspective is gained from the calculation of the device noise corner
frequency fc as a function of gm/ID. If fc were proportional to (gm/ID)−1, the increase
in flicker noise due to higher gm/ID would be compensated by the increase in ωT .
Thus, flicker noise would not depend on gm/ID and white noise could always be
reduced by increasing the current. If fc grows faster than ID/gm, flicker noise would
increase as gm/ID decreases, and if flicker noise is dominant, the total noise would
present a minimum for a finite current.
Previous analysis shows the involved dependence of ENC on the models and tran-
sistor’s inversion level. The analysis also illustrates the insight gained by expressing
the models as functions of gm/ID, and the convenience of using the gm/ID method-
ology to obtain a numerical solution to the ENC optimization problem.
38 CHAPTER 3. NOISE ANALYSIS IN PULSE DETECTORS
Not being relevant in noise optimization, the parallel noise contribution was not
considered in the above analysis. ENC due to detector and input transistor leakage
current depends on the filter, and adds a constant component to the ENC power.
3.4 Noise analysis of front-ends that incorporate
switched-capacitor filters
The same time-domain technique presented earlier can be used for the noise analysis
of front-ends for particle physics experiments that include switched-capacitor (SC)
filters. In such cases, the weighting function, from which the noise coefficients are
computed, will be rippled due to the switched nature of the filter. This implies a rip-
pled time derivative, with a higher integral because the peaks squared imply a higher
series noise coefficient than that of a continuous-time filter. At higher sampling fre-
quencies, the switched-capacitor filter response becomes closer to the continuous-time
filter response. In the limit, with infinite sampling frequency, the switched-capacitor
filter responds exactly like a continuous-time filter. Although switched-capacitor fil-
ters for particle physics experiments represent a subset of suboptimal solutions, they
can be attractive if high precision in both the time and signal amplitude domains
is required. Moreover, a switched-capacitor filter has precisely defined sampling and
hold times, and its output can be held for precise A/D conversion, even during the
reset of the CSA (pipelined operation), without lengthening the flat-top portion of
the weighting function.
Figure 3.7 shows the contrast between two weighting functions with a 2× ratio in
the switched-capacitor sampling frequency, and illustrates the advantage of switching
at higher frequency. Of course, there is a tradeoff between noise added due to the finite
sampling frequency and power consumption needed to push the sampling frequency
envelope.
Another point of view on the effect of switching on noise filtering capabilities is
the aliasing due to the sampling nature of the switched-capacitor filter. At a lower
sampling frequency, the required anti-alias filter specifications become more stringent,
3.4. NOISE ANALYSIS AND SWITCHED CAPACITORS CIRCUITS 39
0 50 100 150 200 250 3000.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Time (ns)
Nor
mal
ized
wei
ghtin
g fu
nctio
n
Figure 3.7: Comparison between two weighting functions. The switched-capacitorportion has a 2 : 1 ratio in switching frequency.
and a suboptimal anti-alias filter fails to cancel out the noise components folded into
the signal bandwidth.
A third point of view is the noise-averaging of the switched-capacitor integrator.
The integrator input is a noisy voltage step, and its noise can be computed using the
equations presented in this chapter. The samples of the output step due to the input
signal are fully correlated and added as voltages. The delta noise voltage holds no
correlation between samples and therefore is added as power. As integration proceeds,
the signal integral grows faster than the noise integral, producing an increasing SNR
for delta noise as integration time increases. The reset-induced baseline fluctuation
due to split doublets can be added to the integrator output noise result, completing
the series noise analysis.
Chapter 4
System-Level Design
This chapter presents the system-level design of the Bean in the context of a top-down
design approach. First, signal, noise and collision rate specifications are considered
for a general idea on a possible system architecture. Then, the signal path is specified,
and power and noise budgets are then assigned. This chapter ends with a summary
on the Bean’s system-level design.
4.1 Signal, noise and rate considerations
The maximum input signals to the Bean will depend on the BeamCal detector tech-
nology, which is still being designed, and on the mode of operation. For a silicon
detector, the maximum input charge per pixel per bunch crossing will be 36.9 pC
in standard data taking (SDT) mode, and about 50× smaller in detector calibration
(DCal) mode. The SDT maximum input signal corresponds to 230.6 million electrons
of charge. At 10 bits, 1 LSB corresponds to 225 k electrons of input charge, a rather
large number for particle physics experiments. In DCal, 1 LSB corresponds to 4.5 k
electrons of input charge. Although in particle physics experiments noise is specified
in ENC, since this particular instrumentation ASIC will include ADCs, RMS noise
will be specified in terms of LSB.
As shown in Chapter 3, the front-end (CSA and filter) noise depends on the total
capacitance at the input node, the detector leakage current, the CSA input-referred
40
4.1. SIGNAL, NOISE AND RATE CONSIDERATIONS 41
noise (which is a function of its bias current) and the noise coefficients derived from
the front-end weighting function W (t). With only 308 ns for signal processing, the
series noise component will be dominant in the noise equation. This is because the
series noise coefficient NS =∫
(W ′(t))2dt is proportional to the slope of W (t), which
needs to be large in order to define the weighting function shape in such a short time.
The timing constraint also makes it necessary to use an active baseline restoration
method (e.g., gated reset), implying a time-varying front-end design.
In SDT, for a typical weighting function shape defined only by the CSA-limited
bandwidth, even without using a filter noise is not a concern due to the relatively
large input signals. Since this is not necessarily the case for DCal, the weighting
function in this mode of operation must be carefully tailored in order to meet the
noise specifications.
The theoretical minimumNS corresponds to an isosceles-shaped triangular weight-
ing function, which effectively minimizes its slopes. Figure 4.1 shows the theoretical
minimum front-end series noise due to the CSA input device, as a function of the in-
put device’s bias current and for different values of gm/ID. The calculation considers
the circuit capacitances for DCal, and a front-end output swing of 1V.
Figure 4.1 shows that a theoretical minimum current of 82µA is required in
the CSA’s input device in order to have an input-referred RMS noise charge below
0.5LSB, or 2,250 electrons. Any departure from the isosceles triangle shape will imply
additional noise, and more current will be needed in the CSA. The plot also confirms
that a low-noise design benefits from larger values of gm/ID. However, bandwidth
and settling considerations limit the gm/ID value to about 16mS/mA. Moreover, the
result shown in the plot is optimistic, because isosceles-shaped weighting functions
are difficult to achieve, the 1-V output swing implies unacceptable nonlinearity due
to finite amplifier gain, and the noise contributions from other amplifier devices are
not considered. Additionally, the power overhead due to the front-end filter is not
included in the analysis, and could easily add 0.5mA to the current consumption.
A second case for consideration would be to rely only on filtering by the CSA itself,
tailoring a slow-gated reset in order to limit the weighting function’s positive slope.
The analysis in this case shows that, for a CSA modeled by a single pole system with
42 CHAPTER 4. SYSTEM-LEVEL DESIGN
−210
−110
010
210
310
410
Current (mA)
EN
C (
elec
tron
s)
gm/Id = 10 mS/mAgm/Id = 12 mS/mAgm/Id = 14 mS/mAgm/Id = 16 mS/mAgm/Id = 18 mS/mAgm/Id = 20 mS/mAgm/Id = 22 mS/mA
Figure 4.1: ENC series noise contribution as a function of input device’s ID, fordifferent values of gm/ID.
1-LSB settling error, the current needed to achieve RMS noise below 0.5LSB is close
to 0.5mA.
From the analysis results, the simplest noise-reduction strategy would be to rely
only on the CSA for filtering, and increase the amplifier current in order to meet
the noise specifications. Fixing gm/ID and with CSA’s thermal noise dominating the
equation, an increase of CSA current by 100× is required to achieve an RMS noise
reduction of 10×, so this strategy reaches a fundamental diminishing returns regime.
If the additional amplifier current exceeds a tipping point of about 0.75mA, it is more
efficient to move to a different strategy, using a dedicated filter in order to reduce the
weighting function slopes. Therefore, a dedicated pulse-shaping filter is used in the
Bean design.
4.2 Signal path
Figure 4.2 shows the signal path of a single channel. A folded cascode topology is used
for the CSA, as it provides excellent gain and bandwidth and is compatible with a
4.2. SIGNAL PATH 43
CSAReset
Filter ADCDetector
todigitalmemory
Precharge
Figure 4.2: Signal path block diagram.
1.8-Volt power supply. The CSA has two selectable feedback capacitors to implement
the appropriate gains for the different modes of operation, aiming to have an output
swing of 0.9V for each. For an NMOS input device, the baseline will settle at about
VT , or 0.5V. However, the high-gain region of operation will be roughly 0.4V from
the rails, still allowing sufficient VDS headroom in the cascoded active load for a high
output resistance. In order to take advantage of the CSA’s full output swing, it will
be connected to an internal precharger circuit that will inject a known amount of
charge prior to each cycle, in order to move the baseline closer to 0.4V.
Based on the conclusion of Section 4.1, the front-end employs a filter following
the CSA, which can be bypassed depending on the mode of operation. The filter’s
transfer function is a lossless integrator in order to produce the negative slope of the
triangular weighting function. Considering 308 ns cycles, timing must be precisely
defined. Therefore, a switched-capacitor (SC) integrator is used for the filter, pro-
viding a precisely-defined time constant and taking advantage of the technology’s
MIM capacitor linearity and matching. The sampling nature of the SC filter aliases
high-frequency components, including noise, into the baseband. In principle, the
bandwidth-limited CSA will act as the required anti-alias filter for the SC integrator.
Early calculations and validating simulations of the SC filter showed that a sam-
pling rate of 51.95MHz, equivalent to 16 sampling periods per collision, is a good
tradeoff between circuit complexity and performance. A higher sampling rate makes
44 CHAPTER 4. SYSTEM-LEVEL DESIGN
the design of the SC filter more challenging, whereas a lower rate has a reduced fil-
tering capability as the aliasing increases the integrated noise. Therefore, the Bean
is designed to process the input pulses at the 3.247-MHz ILC collision rate, with an
internal clock 16× faster. The 308 ns period between pulses constitutes one cycle,
and the 16 clock periods within each cycle define subcycles and sampling periods of
switched-capacitor circuits.
As mentioned earlier, the weighting function must be carefully tailored in order
to maximize the SNR. When the filter is bypassed, the weighting function’s negative
slope is directly related to the CSA time-domain response. When the filter is included
in the signal path, the weighting function’s negative slope is shaped by the SC filter.
Both cases have adequate noise filtering properties, being the latter better, but more
power consuming. As for the weighting function’s positive slope, there are basically
two options: to perform a slow reset release, which slowly opens the reset transistor,
gradually reducing the CSA bandwidth and limiting noise, or using correlated double
sampling (CDS), which basically copies a mirrored version of the weighting function’s
negative slope.
Implementing CDS involves three steps: reset, baseline sampling and signal sam-
pling. In this case, the reset does not need to be complete, as the CDS will eliminate
any reset-related offset. As for the baseline and signal, both need to be filtered prior
to sampling, and therefore the remaining part of the cycle must be split into two
equal periods for filtering purposes. Since the reset period does not contribute to the
weighting function but uses some of its time span, the more the time spent in reset,
the higher the weighting function slopes.
The slow reset release option also involves three steps: full reset, slow reset release
and signal sampling. One option would be to use half of the cycle period for filtering
purposes prior to signal sampling, and the other half to be split between full and slow
reset, with tunable individual contributions.
In the Bean circuit a slow reset release technique is implemented in order to test
the idea. CDS will still be possible, done in the digital domain and using two 308-ns
cycles per reading: one for baseline sampling, and another for signal sampling. If
CDS is implemented in this fashion, the pulse train input rate will be halved.
4.2. SIGNAL PATH 45
The next step in the signal path is digitization and storage. One choice would
be to sample the front-end output in an analog memory block, and then digitize
and read out during the silent period. Another option is to digitize in real time,
and read out during the silent period. The analog memory option has some draw-
backs: the relatively large area required to hold the data before digitization; timing
variability among frames, implying a frame-dependent gain; memory leakage, which
increases with irradiation; and the lack of algorithms to overcome the consequences
of single-event upsets (SEU) when the storage unit is upset by a particle [51]. These
considerations support the use of real-time, or near real-time, digitization and the
implementation of static RAM cells as the digital memory units in this system.
Digitization in the channel signal path is accomplished with 10-bit ADCs. Dif-
ferent options are possible, such as sharing an ADC among a number of channels,
which requires analog memory for buffering and implies near real-time digitization,
or implementing a single ADC per channel, digitizing during the 308 ns period. The
latter option has been chosen to improve the channel-to-channel uniformity by reduc-
ing the effects of different analog signal paths and timing. Each ADC must have a
conversion rate of almost 3.25MS/s. To achieve the required resolution, a successive
approximation register (SAR) ADC architecture is a good candidate due to circuit
simplicity, small footprint and low power consumption.
As mentioned in Chapter 2, the Bean must be able to tolerate a total radiation
dose of 1Mrad (SiO2). The 180-nm TSMC mixed-signal process is naturally tolerant
to total ionizing dose (TID) radiation effects [52] since quantum tunneling through
the thin oxide removes its traps and reduces leakage. However, special techniques to
mitigate irradiation effects in shallow trench isolation (STI) oxide and device-to-device
leakage will be necessary. Enclosed-layout transistors (ELTs) and guard rings are
effective irradiation mitigation methods [53] [54] [55] [56] [57] that should extend the
ASIC radiation tolerance well beyond the specifications [58]. These methods represent
a radiation hardening by design (RHBD) approach, where a standard technology is
radiation-hardened with special layout. The drawbacks of RHBD are penalties in
area and power, and limited transistor sizes [59] [60] [61] [62] [53] [63]. Moreover, the
lack of models and adequate extraction tools for RHBD circuits make the design and
46 CHAPTER 4. SYSTEM-LEVEL DESIGN
Noise source Noise power budget
CSA 1×Q2n
Filter kT/C 0.25×Q2n
Filter amplifier 0.25×Q2n
Buffers 0.25×Q2n
ADC 1×Q2n
Total 2.75×Q2n
Table 4.1: Channel noise budget.
verification process even more challenging [57] [64].
4.3 Power and noise budget
The power dissipation goal of 2.19mW per channel is difficult to achieve since the
CSA alone will use almost half of it. Small changes in the system specifications will
imply new struggles to accommodate any required additional power. A solution is to
implement a power cycling mechanism, which reduces the front-end quiescent current
to a very small value during readout. Since the beamline is silent 99.5% of the time,
the power dissipation specification is not really a problem, and the only reason to
require low power electronics is to mitigate peak power effects. This idea will be
included in future revisions of the Bean.
Regarding input-referred noise power, let Qn be the input-referred quantization
noise voltage, equivalent to 65 k electrons in SDT and 1.3 k electrons in DCal. Input-
referred noise from different circuits in the signal path will be specified in terms of
Q2n. Table 4.1 shows the noise budget for the front-end independent noise sources.
4.4 Block and timing diagrams
Figure 4.3 shows a block diagram of the Bean. The circuit will have 32 identical
channels, each providing the signal path for different detector pixels. The Bean
signal path begin with the CSA, connected to the detector trough an external coupling
capacitor. An internal pulser will also be connected to the input pin in order to provide
4.4. BLOCK AND TIMING DIAGRAMS 47
Filter
CSA
Memory
q1 q2 qi-1 qi
Detector
Σ
Adder
Dia
gnos
tics
Sta
ndar
d R
eado
ut
ADC
ADC
qNqi+1
Cal
Reset
CH01
CH32
THE BEAN
Figure 4.3: The Bean block diagram.
a known input signal for calibration purposes. The pulser doubles as a precharging
circuit, moving the Bean baseline in order to take full advantage of the CSA linear
region. The CSA is followed by a SC integrator, capable of producing the triangular-
like negative slope in the weighting function. One ADC per channel will be included,
taking the input from either the CSA or the filter output. The ADC outputs will be
stored in digital memory cells, which will be read out during the silent period. In
addition to the identical 32 channels, an analog adder followed by a dedicated ADC
will also be included, in order to generate the low-latency output.
For proof-of-concept purposes, a smaller prototype has been designed, integrated,
and tested. A block diagram of the prototype is shown in Figure 4.4. The Bean
prototype is similar to the Bean, but includes only three channels and lacks digital
memory.
Figure 4.5 shows a possible timing diagram for SDT mode during the pulse train,
spanning two identical cycles. The CSA is reset during the first 8 subcycles within
each cycle. At the end of reset, a bunch crossing occurs, and an impulse of charge is
produced by the detector. At the same time, the precharging circuit injects the charge
needed to shift the baseline to the voltage for which the output swing is maximum,
48 CHAPTER 4. SYSTEM-LEVEL DESIGN
Detector
Σ
DiagnosticsReadout
ScienceReadout
CHANNEL 1
CHANNEL 3CHANNEL 2
Stimuli
THE BEAN V1.0
CSAReset
Filter ADC
Cal
Adder ADC
FPGA
Figure 4.4: The Bean prototype block diagram.
Subcycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1615
Pulse in
Precharge
CSA
Buffer
ADC
Adder
Adder ADC
Rst En
Full Rst Slow Rst Rel Amplify
Rst En
Sample D1D2 D3 D4 D5 D6 D7 D8 D9 D10
Sample AddD1D2 D3 D4 D5 D6 D7 D8 D9 D10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1615
Rst En
Full Rst Slow Rst Rel Amplify
Rst En
Sample D1D2 D3 D4 D5 D6 D7 D8 D9 D10
Sample AddD1D2 D3 D4 D5 D6 D7 D8 D9 D10Sample Sample
Figure 4.5: Timing diagram in SDT mode.
and the CSA is enabled. By the end of the first cycle, the CSA output is already
settled and ADC sampling occurs. In this pipelined operation, the A/D conversion
occurs while the front-end processes the next pulse. The adder, implemented as a
switched-capacitor analog summer, samples all the Bean’s CSA outputs by the end of
the amplifying period. It takes it one subcycle to produce the addition. Shortly after
that, the ADC dedicated to digitizing the analog summation of 32 channel outputs
starts the conversion. The fast feedback adder latency, defined as the time between a
collision and the 8-bit digital output corresponding to the summation of the signals
measured by all the ASIC’s channels, is about 308 ns.
Figure 4.6 shows a possible timing diagram for DCal mode, spanning two identical
4.4. BLOCK AND TIMING DIAGRAMS 49
Subcycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1615
Pulse in
Precharge
CSA
Buffer
Filter
ADC
Adder
Adder ADC
Rst En
Full Rst Slow Rst Rel Amplify
Rst En
Hold Rst FilterD1 D2 D3 D4 D5 D6 D7 D8 D9 D10
Sample AddD1 D2 D3D4 D5 D6 D7 D8 D9 D10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1615
Rst En
Full Rst Slow Rst Rel Amplify
Rst En
Hold Rst FilterD1 D2 D3 D4 D5 D6 D7 D8 D9 D10
Sample AddD1 D2 D3D4 D5 D6 D7 D8 D9 D10Sample Sample
Sample Sample
Figure 4.6: Timing diagram in DCal mode.
cycles. The CSA operates with the same timing as in SDT mode. Since the CSA
does not slew in this mode, the filter can be enabled along with the CSA without
compromising the linearity. At the end of the amplification period, the filter holds
the output for the ADC. The filter reset is fast enough and does not contribute to
split doublet noise effects [44]. Thus, it can hold the output until right before a new
pulse arrives.
The corresponding weighting function for DCal mode, for the timing diagram
shown in Figure 4.6, is presented in Figure 4.7. It was obtained via behavioral sim-
ulations, assuming a 3-subcycle full reset followed by a 5-subcycle slow reset release
and an 8-subcycle filtering time. The ripple in the negative slope section is due to
the sampled-data nature of the filter.
50 CHAPTER 4. SYSTEM-LEVEL DESIGN
0 50 100 150 200 250 3000.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Time (ns)
Nor
mal
ized
wei
ghtin
g fu
nctio
n
Figure 4.7: Simulated weighting function in DCal mode, for a switched-capacitorintegrator and slow reset-release technique.
Chapter 5
The Bean Prototype: Circuit
Design
The Bean circuit is designed to implement the signal path of the block diagram shown
in Figure 4.4. Figure 5.1 shows a block diagram that implements the same signal path,
now including additional details on the fully-differential blocks and the interconnect
buffers. This chapter deals with the Bean circuit-level design, according to the block
diagram shown in Figure 5.1, including the charge amplifier, filter, ADC, adder and
buffers.
5.1 Charge-sensitive amplifier design
The charge-sensitive amplifier (CSA) converts charge generated in the detector into
voltage. The global specifications of the CSA are presented in Table 5.1.
The CSA has been designed around a folded-cascode topology due to its simplicity,
linearity, low noise, excellent gain and bandwidth, and compatibility with a 1.8-volt
CMOS process technology. The low noise results from the independence between
input and load branch currents, which makes it possible to choose transconductances
that ensure the noise from the input device is dominant.
Equation 5.1 gives the change in the output voltage of the CSA as a function of an
input charge of Qin , the feedback capacitance CF , an open-loop small-signal gain of
51
52 CHAPTER 5. THE BEAN PROTOTYPE: CIRCUIT DESIGN
Σ
CSA
Feedbacknetwork
Filter ADC
Cal Adder ADC
fromdetector
fromotherchannels
∫frombias gen
Signalbuffers
Rail-to-railbuffers
Rail-to-railbuffers
Adderoutput
Channeloutput
Figure 5.1: The Bean block diagram, including one channel and the fast feedbackadder.
Specification Value
Modes of operation SDT and DcalExt. input capacitance 40 pF due to detector and wireInput charge 36.9 pC (SDT), 738 fC (DCal)Output swing 1V or closeNonlinearity < 1%, measured as max. deviation from linearSettling time < 154 ns for quant. noise-like levels (28.9% of 1 LSB)Power consumption Minimize
Table 5.1: Charge amplifier specifications.
5.1. CHARGE-SENSITIVE AMPLIFIER DESIGN 53
AOL, and a parasitic capacitance at the input node of CD+W , which is due to detector
and wire capacitances. This result is topology-independent:
vo =Qin
CF
·
(
AOL · β
1 + AOL · β
)
=Qin
CF
· γOL, (5.1)
where β is the feedback factor given by Equation 5.2:
β =CF
CF + CD+W
. (5.2)
The ideal transfer characteristic is vo = Qin/CF , valid for AOL = ∞. The factor
γOL represents the effects of the finite open-loop gain of the CSA on the ideal transfer
characteristic. Although the static error can be significant, especially in the DCal
mode if AOL < 100 dB, it can be corrected through post-processing. Since AOL
changes over the CSA output range, γOL introduces nonlinearity into the equation
that is more pronounced for small CF (DCal). This can be mitigated by reducing the
CSA output swing to a range where the variation in AOL is sufficiently small. It was
found through simulations that feedback capacitances of 45 pF for SDT and 0.9 pF
for DCal, implying a full-scale output swing of 0.82V, are large enough to meet the
linearity requirement.
In the folded-cascode topology, the CSA baseline is approximately set by the input
device’s threshold voltage, near VDD − |VTH | for a PMOS input device, or VTH for
an NMOS input device. The former is preferred for a common-cathode detector,
which injects current into the feedback capacitor, whereas the latter is preferred for
a common-anode detector, which pulls current from the feedback capacitor. As the
detector technology is still to be chosen, an NMOS input device will be used in the
prototype design. This can be changed in future revisions if necessary. As mentioned
in Chapter 4, a precharge circuit will be used to shift the baseline in order to take
advantage of the CSA linear output range.
Figure 5.2 shows a single-ended, NMOS-input folded-cascode amplifier schematic.
It consists of 5 devices: input transistor MI , folding transistor MF , the folded cascode
transistor MCF , load transistor ML and the cascode for load transistor MCL. Noise
considerations from Chapter 4 set the input device’s gm/ID value around 16mS/mA
54 CHAPTER 5. THE BEAN PROTOTYPE: CIRCUIT DESIGN
VDD
VIN
VOUT
VL
VCL
VF
VCF
MI
MF
MCF
MCL
ML
II
IF
IL
Figure 5.2: Schematic of a single-ended, NMOS-input folded-cascode amplifier.
for DCal mode. MF sets the amplifier current, IF , at 500µA. ML sets the load
branch current, IL, at 50µA. MI ’s bias current is the difference between IF and IL,
or 450µA. These currents were established based on noise considerations.
The amplifier architecture implies asymmetric slewing, since the current it can sink
from the load is limited to the load transistor’s current IL, whereas the current it can
push into the load is set by the cascode for folding device’s current ICF . Although in
steady state ICF should match IL, when slewing it will take some of the input device’s
current II . Calculations and simulations show that the slew rate in the SDT mode
(with CF = 45 pF) is sufficient to settle the output voltage within half a cycle.
A simplified small-signal static model of the amplifier in Figure 5.2 is shown
in Figure 5.3. The effective transconductance, gmeff , defined as the output current
derivative ∂Io/∂Vin when Vout is shorted to ground, is given in Equation 5.3. The
output resistance ro, defined as the resistance seen at the amplifier output node when
no input is applied, is given in Equation 5.4:
5.1. CHARGE-SENSITIVE AMPLIFIER DESIGN 55
gmivi
roi rof
vyvx
vorol
roclrocf
gmcfvx gmclvy
Figure 5.3: CSA simplified small signal static model.
gmeff = gmI ·
(roF ||roI ) · (1 + gmCF · roCF )
(roF ||roI ) · (1 + gmCF · roCF ) + roCF
(5.3)
ro = (roL + roCL + gmCL · roCL · roL) || ((roI ||roF ) + roCF + gmCF · roCF · (roI ||roF ))(5.4)
For similar output resistance contributions from upper and lower output branches,
and for relatively large intrinsic gain in all the devices, gmeff and ro can be approxi-
mated as:
gmeff ≈ gmI (5.5)
ro ≈ (gmCL · roCL · roL) || (gmCF · roCF · (roI ||roF )) . (5.6)
The low-frequency open-loop gain can then be approximated as
|AV | = gmeff · ro ≈ gmI · (gmCL · roCL · roL) || (gmCF · roCF · (roI ||roF )) . (5.7)
The dynamic behavior of the open-loop CSA will be dominated by the output
node resistance and capacitance, so other time constants can be ignored. Figure 5.4
is a small-signal model of the closed-loop CSA, where CL is the load capacitance.
From the schematic, the dominant pole can be computed as
p = − gmeff · ro ·CF + CF + CD+W
ro (CL ·CF + CL ·CD+W + CF ·CD+W )≈ − β · gmeff
CL + (1− β)CF
, (5.8)
where the feedback factor β is given by Equation 5.2.
56 CHAPTER 5. THE BEAN PROTOTYPE: CIRCUIT DESIGN
CF
CD+W
CLro
vi vo
gmeffvi
Figure 5.4: CSA dynamic model.
The amplifier’s input-referred noise power for relatively low frequency can be
expressed as the weighted sum of the noise power contributions of all transistors,
which is
V 2N = V 2
NI ·N2I + V 2
NF ·N2F + V 2
NCF ·N2CF + V 2
NCL ·N2CL + V 2
NL ·N2L, (5.9)
where V 2NI is the gate-referred noise power of MI , V 2
NF is the gate-referred noise power
of MF , V 2NCF is the gate-referred noise power of MCF , V 2
NCL is the gate-referred noise
power of MCL, and V 2NL is the gate-referred noise power of ML. From Figure 5.2, the
static gains that refer the gate voltage of each transistor to the CSA input can be
computed as
NI = 1 (5.10)
NF ≈ gmF
gmI
(5.11)
NCF ≈ 1
gmI · (roI ||roF )(5.12)
NCL ≈ 1
gmI · roL(5.13)
NL ≈ gmL
gmI
(5.14)
Since gmI is large compared to gmL, 1/roL and 1/ (roI ||roF ), the noise contributions
from MCF , MCL and ML can be neglected. Thus, the dominant noise contributors
are MI and MF .
Using equations 5.1 and 5.5 through 5.14, and following the gm/ID methodol-
ogy while targeting the specifications stated in Table 5.1, the CSA design space was
5.1. CHARGE-SENSITIVE AMPLIFIER DESIGN 57
Transistor Bias current gm/ID W LMI 450µA 16mS/mA 283.7µm 0.9µmMF 500µA 8.5mS/mA 253.3µm 0.72µmMCF 50µA 20mS/mA 298.6µm 0.54µmMCL 50µA 15mS/mA 30.8µm 1.08µmML 50µA 15mS/mA 30.8µm 1.08µm
Table 5.2: CSA design values.
explored. Device channel lengths were tailored to balance the contributions from dif-
ferent devices to internal capacitances and resistances, aiming for an optimal design.
The resulting design values are shown in Table 5.2.
SPICE simulations show an open-loop gain of 76.5 dB, a unity-gain bandwidth
of 800MHz, and a closed-loop bandwidth of 19.1MHz for DCal. Phase margins are
84.2 ◦for DCal, and 81.7 ◦ for SDT.
The CSA feedback network, shown in Figure 5.5, includes the two feedback ca-
pacitors, COp and CCal , two reset switches, MROp and MRCal , and the mode-select
switch, MOM , driven by clock OM . During CSA amplification operation, the reset
switches remain open. When a full reset is engaged, the reset switches are driven
by clock RstF . After four subcycles of full reset, the charge stored in the feedback
capacitor is negligible and the reset clock RstF is disabled. At this moment, there
is a charge stored in capacitors C4 and C1. Through the action of switch MLVgs , ca-
pacitor C1 is now sharing its charge with C2. Capacitances C1 +C2 and C4 keep the
reset transistors MRCal and MROp operating in the triode mode, preventing a sharp
reset-release action. On each subsequent subcycle, switched-capacitors C3 and C5 re-
duce the gate-to-source voltage of the reset transistors by taking a percentage of the
charge stored in capacitances C1 + C2 and C4, and dissipating it in switches MDisCal
and MDisOp . The consequential reduction in the reset transistors’ VGS produces the
slow reset-release action designed to reduce the weighting function’s positive slope.
Capacitors C1-C5 were sized to produce a wide range of VGS voltages that crosses
the reset transistor’s threshold voltage. After the slow reset-release action ends, the
switches in the reset-release network short-circuit the gate and source terminals of
each reset transistor, forcing them open and enabling the CSA amplification.
58 CHAPTER 5. THE BEAN PROTOTYPE: CIRCUIT DESIGN
CCal
RstF
RstF
OM
COp
φ2
RstF
VIN VOUT
φ2
φ1
φ1
MRCal
MROp
C1
C2
C3
C4
C5
MOMMShCal
MShOp
MDisOp
MDisCal
MLVgs
Figure 5.5: CSA feedback network.
5.2. CSA PRECHARGER 59
In the frequency domain, the reset-release action can be seen as a progressive
reduction in the CSA bandwidth, from the CSA unity-gain bandwidth (full reset,
when the reset transistors behave as short circuits) to the CSA operating bandwidth
(CSA enabled, when the reset transistors are open). The weighting function positive
slope is shaped according to the CSA dominant time constant, which is modulated by
the slow reset-release action. The effect is a soft reset-release action, and consequently,
a reduced positive slope in the weighting function.
5.2 CSA precharger
A precharger circuit was designed to inject a known charge into the CSA for baseline
adjustment and electronic calibration purposes. During testing, the precharger was
used to reduce the CSA baseline level on the DCal mode in order to maximize the
CSA output swing, taking full advantage of its linear region.
Figure 5.6 shows a simplified schematic for the precharger circuit. It consists of
two MOS switches and a 0.5-pF MIM capacitor CPC connected to the CSA input
node. A 50× larger, off-chip capacitor was used as the precharger capacitor for the
SDT mode of operation.
The precharger works on a two-phase, non-overlapping clock. During φ1, the ca-
pacitor left plate is tied to an external, adjustable reference VDD Ref . During φ2 the
capacitor left plate is tied to ground. On every φ2 to φ1 transition, the capacitor
pushes a charge of QPC = CPC ·VDD Ref into the CSA input. This produces a CSA
output voltage variation of −CPC ·VDD Ref /CF , where CF is the CSA feedback capac-
itor, either CCal for the DCAL mode, or CCal + COp for the SDT mode. The charge
injection is done right after the CSA is enabled, reducing the output baseline voltage.
On the opposite clock transition, from φ1 to φ2, the precharger is reset and pulls the
same amount of charge from the CSA. Since the precharger reset occurs during the
CSA reset, the baseline is not affected by this clock transition.
60 CHAPTER 5. THE BEAN PROTOTYPE: CIRCUIT DESIGN
CSAinputnode
CPC
φ1
φ2
VDD_Ref
Figure 5.6: Schematic of CSA precharger circuit.
VICM
CSA
CSB
CFA
CFB
VIFA
VIFB
VOFA
VOFB
Switch Control
−+
+−
φ1
φ1
φ1
φ1
φ2
φ2
φ2
Mux
Mux
Figure 5.7: Filter simplified schematic.
5.3 Filter design
A non-inverting, fully-differential switched-capacitor (SC) integrator serves as the
front-end filter. The input corresponds to the buffered and level-shifted difference
between the CSA output and the baseline. A simplified schematic of the filter is
shown in Figure 5.7. Some reset control logic and switches have been purposely
omitted.
Capacitors CSA and CSB are the series switched capacitors emulating the integra-
tor resistors, whereas CFA and CFB are the feedback capacitors. The OTA output
common-mode level is set by the OTA’s internal common-mode feedback (CMFB)
5.3. FILTER DESIGN 61
Vtbias
VCMFB1
Vbias
Vip Vim
VDD
VomVop
CMFB2
M1A
M2A
M3A
M4A M5A
M6A
M1B
M2B
M3B
M4BM5B
M6B
Mtail MCMFB
RZARZBCCACCB
Vo1p Vo1m
Figure 5.8: Class A/AB filter’s OTA schematic.
circuit, whereas the input common-mode level is set by the external reference VICM .
The sampling frequency is 51.95MHz. Thus, each integration subcycle is 19.25 ns
long. Since each subcycle involves two phases, sampling and holding, each phase
has only 9.625 ns for settling. On the other hand, kT/C noise considerations set the
minimum sizes for the integrator’s capacitances, and the OTA output must be able
to drive these capacitances. To conserve power, a class-AB amplifier is used, which
is capable of providing enough output current during the transients, without large
quiescent current consumption.
A schematic of the OTA is shown in Figure 5.8 [65]. The OTA is fully differential
and consists of a class-A first stage followed by a class-AB second stage, with Miller
compensation. Two independent CMFB circuits, shown in Figure 5.9, are used, one
per stage. The first-stage quiescent current is set by the differential pair’s tail current
source. The second-stage quiescent current is set by the first stage’s common-mode
output, a reference for which is established by a diode-connected device biased by
a reference current source. The second-stage input devices are NMOS transistors,
rather than PMOS, in order to minimize the amplifier quiescent power dissipation.
A small-signal differential equivalent half circuit for the OTA can be reduced to
a cascade of two common-source stages as shown in Figure 5.10, where gmx = gm1 ,
gmy = gm6 + gm5 · gm3/gm4 , rox = ro1 ||ro2 and roy = ro5 ||ro6 . This model assumes
that the current mirror M4 −M5 has a higher bandwidth than the rest of the circuit,
62 CHAPTER 5. THE BEAN PROTOTYPE: CIRCUIT DESIGN
VOCMφ1
φ1φ2
φ2VOCM φ1
φ1 φ2
φ2
VomVop
Vb Vb
Vbout
Vdd
Vbout
VddVbp
φ1
φ1 φ2
φ2φ1
φ1φ2
φ2
Vo1mVo1p
Vb Vb
VCMFB1VtbiasVtbias
Vop Vom
Figure 5.9: Class A/AB filter OTA common-mode feedback circuit schematic.
gmxvin gmyvx
vx
rox roy
voCC RZ
Figure 5.10: OTA small-signal half circuit model.
and neglects the common-mode feedback output conductances. The compensation
network, CC and RZ , was designed to ensure stability in the worst-case feedback
factor scenario, which occurs during reset.
From the small-signal model in Figure 5.10, the open-loop gain of the OTA is seen
to be gmx · rox · gmy · roy , designed with a target gain over 60 dB for low closed-loop
steady-state error. A dominant-pole approximation analysis [66] shows that the open-
loop dominant time constant is gmy · rox · roy ·CC , whereas the closed-loop bandwidth
is β · gmx/CC , where the feedback factor is
β =CF
CF + CS + Cggx
. (5.15)
The output RMS noise of the filter must be computed for the entire integration
period, starting from reset and spanning N = 8 subcycles. There are two main
5.3. FILTER DESIGN 63
Transistor Bias current gm/ID W LM1 30µA 11.3mS/mA 17.37µm 0.45µmM2 30µA 11.3mS/mA 3.15µm 0.45µmM3 85µA 11.3mS/mA 9µm 0.45µmM4 85µA 2.7mS/mA 1.8µm 0.27µmM5 85µA 2.7mS/mA 1.8µm 0.27µmM6 85µA 11.3mS/mA 9µm 0.45µm
Table 5.3: Filter amplifier design values.
contributions to the integrated filter noise: V 2kT/C noise due to switch resistances and
V 2filteramp due to amplifier noise.
After N integration subcycles, the contribution from kT/C noise can be computed
as
V 2kT/C = 2
kT
αCS
(
1 +N
α
)
, (5.16)
where α = CF/CS. The factor 2 is due to the fully-differential topology. The ampli-
fier’s integrated output noise can be computed as [67]
V 2filteramp ≈ 2N
{
γ
β·
kT
CC
(
1 +gmxx
gmx
)
+kT
CLtot
[
1 + γ
(
1 +gmyy
gmy
)]}
, (5.17)
where γ is the technology-dependent MOSFET noise parameter, CLtot is the total
capacitance at the output node, including CF , gmxx = gm2 , and gmyy = gm5 (1 +
gm5/gm4 ).
Table 5.3 shows the parameter values for the filter OTA design. Transistors M4
and M5 are small, and thus biased in strong inversion in order to reduce the current
mirror doublet effect [66] in the transient response, at the cost of a reduced output
swing. The devices channel lengths provide a good balance between open-loop gain
and power consumption. The input device’s transconductance efficiency, gm1/ID1,
was limited to the design value in order to prevent the amplifier from slewing. The
second-stage input device’s transconductance efficiency was limited to the design value
in order to reduce the output quiescent current sensitivity to small variations in the
first stage’s common-mode output voltage.
Simulations show that the amplifier’s open-loop gain is over 70 dB, with a phase
64 CHAPTER 5. THE BEAN PROTOTYPE: CIRCUIT DESIGN
−
+
VCM
Vin_P
Vin_M
Vref_P
Vref_Com
Vref_Com
Vref_M
Dout
C1
C1
CX
CXC2
C2CN-1
CN-1
CN
CN
Figure 5.11: Charge-redistribution switched-capacitor DAC network.
margin of PM = 83o and a crossover frequency of fc = 143.5MHz when connected in
the integrator configuration. This allows more than 7 time constants for settling in
each clock phase.
5.4 ADC design
As mentioned in Section 4.2, there is one 10-bit SAR ADC per ASIC channel with a
sampling rate of 3.25MS/s. If operated at the SC filter clock frequency, there are 16
subcycles per conversion. Since each converted bit requires one subcycle, there is a
6-subcycle overhead for reset, or possibly, for slower bits.
A fully-differential, charge-redistribution SAR ADC is used, taking advantage of
the pseudo- or fully-differential output from the CSA or filter and maintaining good
power supply rejection (PSR). Two DAC switched-capacitor arrays are necessary, as
shown in the simplified schematic of the ADC in Figure 5.11. The SAR logic has
been omitted from this figure.
During reset, the comparator inputs are connected to VCM to set the comparator’s
initial common-mode input voltage, and the capacitor arrays are switched to VinP
and VinM , sampling the differential input. After the reset period, the common-mode
5.4. ADC DESIGN 65
switches are opened and the capacitor arrays are connected to the negative references,
VrefCom for the positive half circuit and VrefM for the negative half circuit. At this
time, the comparator differential input becomes (VrefCom − VrefM ) − (VinP − VinM ).
Then, on each bit test, from MSB (i = N) to LSB (i = 1), the corresponding
capacitors are connected to the positive references, VrefP for the positive half circuit
and VrefCom for the negative half circuit. Since the capacitors are binary-weighted,
with Ci = 2i−1·CX , on bit test i the comparator differential input increases by
VFR/2N−i+1, where VFR = VrefP + VrefM − 2 ·VrefCom is the differential input full-scale
range. The successive approximation register sets the DAC input based upon the
comparator output, and the DAC output thus successively converges to the ADC
differential input value.
Although the capacitor array is nominally binary-weighted, different implementa-
tion techniques can be used. These techniques cover different regions in the design
space, trading capacitance spread and area, linearity, input capacitance and circuit
complexity. For example, a series capacitor in the array produces a split or segmented
array, which presents a reduced input capacitance, as well as area and spread in ca-
pacitor values, but makes the array linearity sensitive to parasitic capacitances to
ground [68]. Calibration is then usually necessary to meet linearity specifications. A
thermometer-coded array offers a reduced ADC differential nonlinearity (DNL), at
the cost of additional logic for a binary-to-thermometer decoder [69]. The spread in
capacitor values is reduced, while the area and input capacitance are unchanged. The
decoder size increases exponentially with the number of bits in the binary output.
Thus, a practical solution is to thermometer-encode only the most significant bits.
In order to reduce the ADC’s input capacitance and area, the smallest possi-
ble capacitors in the 180-nm TSMC process are used, and two different capacitor
structures were considered: metal-insulator-metal (MIM) capacitors and metal-oxide-
metal (MOM) capacitors. In the 180 nm TSMC process, MIM capacitors are made of
parallel plates on M5 and CTM (capacitor top metal), with a capacitance of 1 fF/µm2
and a minimum size of 16µm2, set by design rules. The plate shape is defined by the
photolithographic process, and the dielectric is a 38-nm PECVD oxide layer.
66 CHAPTER 5. THE BEAN PROTOTYPE: CIRCUIT DESIGN
Lateral-field MOM capacitors are made of closely-placed interconnect metal lay-
ers. Although TSMC provides precise RF models for a rotative metal-oxide-metal
capacitor structure [70], more compact MOM capacitor cells with better capacitor-
to-capacitor shielding can be achieved with a custom design. In this context, the
capacitance lower limit is set by matching constraints, as opposed to design rules,
and a lower input capacitance than with MIM capacitors can be achieved. This
makes custom MOM capacitors especially attractive for low-power applications [71]
[72] [73].
MOM capacitor matching data was found in the literature for different processes
[72] [74]. From the data and behavioral Montecarlo simulations on a generic SAR
ADC, it was found that MOM capacitor matching in the 180 nm TSMC process should
be enough to achieve zero missing codes in a 10-bit ADC using unit capacitances in
the low femtoFarad range.
MOM capacitors were designed with a target single-layer unit capacitance of 2 fF,
or a total array capacitance close to 2 pF. Another array with 2 layers and twice the
capacitance was also designed. The structure capacitance was extracted using Space
3D layout-to-circuit extractor software from Delft University [75]. The MOM capaci-
tor ADCs were placed in separate dies, but a conservative MIM capacitor version was
included in the Bean prototype. More details on the MOM capacitor structure will
be provided in Chapter 6.
All digital circuits in the ADC are based on standard CMOS logic gates. The
sequential logic for the SAR ADC was designed to operate on a locally-generated,
non-overlapping two-phase clock. The two-phase clock generator is a copy of the one
used for the switched-capacitor circuits.
The ADC comparator, shown in Figure 5.12, comprises a preamplifier that reduces
offset, noise and possible metastability problems, followed by a latched comparator.
The preamplifier is based on a differential-to-single-ended configuration with current
mirror load. Transistors M1A and M1B are the input devices, transistors M2A and
M2B form the current mirror load, and MtailP is the preamplifier bias current source.
The comparator has two phases of operation. During reset phase (En input low),
MRA and MRB pull the comparator outputs to VDD . During the compare phase (En
5.4. ADC DESIGN 67
VDD
VtailN
VtailP
VP VM
En
VOPVOM
DOut
M1A
M2A
MtailN
MtailP
M2B
M1BMRAMRB
M3A
M4A
M3B
M4BDOut
Figure 5.12: ADC comparator schematic.
input high), the reset transistors MRA and MRB are open and the positive feedback
throughM4A andM4B swings the output nodes toward different rails, according to the
differential input on M3A and M3B . Transistor MtailN sets the the latched comparator
stage quiescent current consumption.
The complementary outputs of the comparator each drive a chain of two inverters,
although only one of the complementary outputs is used. The other one has dummy
inverters to ensure a fully-symmetric circuit with matched loads. The comparator
outputs cannot swing from rail to rail due to the tail current source voltage overhead.
To overcome this problem, the threshold voltage of the first of the two inverters in the
comparator output is skewed high. Table 5.4 shows the comparator currents, device
sizes, and transconductance efficiencies.
Unlike the MOM capacitor ADC, and due to the large capacitive load it represents,
the MIM capacitor ADC included in the Bean prototype cannot be driven directly
by the filter because the filter was not designed to drive large capacitive loads. To
overcome this limitation, a rail-to-rail buffer was designed. The details on this are
presented in Section 5.7.
68 CHAPTER 5. THE BEAN PROTOTYPE: CIRCUIT DESIGN
Transistor Bias current gm/ID W LM1 40µA 17mS/mA 25.9µm 0.18µmM2 40µA 4.5mS/mA 1.35µm 0.9µmM3 17.5µA 10.5mS/mA 0.72µm 0.18µmM4 17.5µA 12mS/mA 3.24µm 0.18µmMR — — 7.2µm 0.18µmMtailN 35µA 18.5mS/mA 17.8µm 0.36µmMtailP 80µA 11mS/mA 54µm 0.54µm
Table 5.4: Comparator design values.
5.5 Adder design
A switched-capacitor adder is used to sum the outputs from the ASIC’s three channels.
The purpose of the adder is to provide a low-latency output proportional to the sum
of the signals detected by all the channels on each collision. Although not useful for
science purposes, output of the adder is helpful in tuning the beams and monitoring
the collision process in real time. The adder takes one subcycle to perform the sum,
and its output is converted to digital using a dedicated ADC.
The adder is implemented using switched capacitors and an OTA identical to that
used in the filter. A simplified schematic is shown in Figure 5.13. The adder gain for
each of the three channels is 1/3. Thus, its full-scale output range is the same as the
filter’s. The gain can be reduced in future revisions of the chip, by simply reducing
the sizes of CSiA and CSiB accordingly, in order to accommodate for the planned 32
channels.
5.6 Signal buffer
Signal buffers are used at the outputs of the CSA and the CSA baseline generator
to prevent filter kickback noise from affecting the CSA operation. The buffer also
shifts the baseline so that the filter differential input (in the DCal mode) or the ADC
differential input (in the SDT mode) span a more symmetric range. The buffer is
based on a level shifter and a common-drain amplifier, as shown in Figure 5.14.
The level shifter in the buffer operates on two phases. During φRst , capacitor CShift
5.6. SIGNAL BUFFER 69
CFA
CFB
VOFP
VOFM
Switch Control
−+
+−
VI3P
VI2P
VI1P
VI1N
VI2N
VI3N
CS3A
CS2A
CS1A
CS1B
CS2B
CS3B
VIcm
Figure 5.13: Adder schematic.
Transistor Bias current gm/ID W LM1 65µA 14.5mS/mA 22µm 0.18µmM2 65µA 20mS/mA 30µm 0.18µmM3 65µA 14.5mS/mA 127µm 0.72µmM4 65µA 6.5mS/mA 30µm 1.08µmMtailN 130µA — 3µm 0.18µm
Table 5.5: Signal buffer design values.
is charged with the external voltage VShift . During φEn the capacitor is connected in
series between Vin and the source follower input.
The source follower comprises seven devices. Transistor M1 is the input device,
biased by cascoded current source M3A-M4A. Transistor M2 improves the buffer
linearity by setting the input device’s source-to-drain voltage equal to M2’s gate-to-
source voltage, which is almost constant. Device M2 is biased by the cascoded current
source M3B -M4B . Finally, Mtail is a triode-connected device that allows the freedom
for M2 source to swing along with the output voltage. Table 5.5 lists the parameter
values for the buffer design.
70 CHAPTER 5. THE BEAN PROTOTYPE: CIRCUIT DESIGN
VDD
VDD
Vout
Vshifted
Vin
Ctrl
BiasCkt
Cshift
VShift
φEn
φRst φRst
M1
M4A
M3A M3B
M4B
Mtail
M2
Figure 5.14: Level-shifting signal buffer.
5.7 Rail-to-rail buffer
The rail-to-rail buffers in Figure 5.1 serve two purposes: they drive the MIM ADC
input nodes and buffer some of the Bean prototype nodes for scope probing. The
buffer must be able to drive 16 pF at a reasonable speed and power dissipation, with
truly rail-to-rail input and output voltages. A schematic of this is presented in Figure
5.15, showing a buffer-connected operational amplifier.
The two-stage amplifier consists of a rail-to-rail, complementary combination of
constant-gm input pairs, MINA-MINB and MIPA-MIPB , followed by folded-cascode,
current-mirroring loads, MCNA-MLNA, MCNB -MLNB , MCPA-MLPA, and MCPB -MLPB ,
and a class-AB output, MoutN -MoutP [76]. Transistors MSNi and MSPi implement a
translinear loop [77], producing the voltage shifts necessary to set the output devices
quiescent current consumption.
In the buffer design, ease of layout took priority over the design optimality. All
devices are, therefore, a parallel connection of a base unit device. Table 5.6 shows
the parameter values for the rail-to-rail buffer design.
As a two-stage, buffer-connected amplifier with a relatively large capacitive load,
stability compensation is an issue and has been addressed by means of pole-splitting
5.7. RAIL-TO-RAIL BUFFER 71
VDD
VIN
VDD VDD VDD VDD VDD
VOUT
VtailP
VtailN
VLP
VCP
VCN
VLN
VLP
RZA
RZB
CCB
CCA
MINA MINB
MIPA MIPB
MtailP
MtailN
MeqP
MeqN
MoutP
MoutN
MLPA
MCPA
MCNA
MLNA MLNB
MCNB
MCPB
MLPB
MSP1
MSP2
MSP3 MSN1
MSN2
MSN3
MSP4
MSN4
Figure 5.15: Rail-to-rail buffer schematic.
(RZi and CCi). Transistors MeqN and MeqP keep the input stage’s total transconduc-
tance constant, simplifying the compensation network design.
SPICE simulations predict an open-loop DC gain of 101.6 dB, a crossover fre-
quency of 49MHz, and a phase margin of 80.3o measured with an 8-pF load.
Transistor Bias current gm/ID W LMIN 15µA 18mS/mA 7.2µm 0.45µmMIP 15µA 17mS/mA 32.4µm 0.45µmMtailN 60µA 14mS/mA 7.2µm 0.45µmMtailP 60µA 11mS/mA 32.4µm 0.45µmMLP 45µA 12.2mS/mA 32.4µm 0.45µmMCP 30µA 14mS/mA 32.4µm 0.45µmMLN 45µA 12.3mS/mA 5.8µm 0.45µmMCN 30µA 14mS/mA 5.8µm 0.45µmMoutP 240µA 9.7mS/mA 97.2µm 0.45µmMoutN 240µA 9.6mS/mA 17.3µm 0.45µm
Table 5.6: Rail-to-rail buffer main design values.
Chapter 6
The Bean prototype:
Implementation
In the Bean prototype layout, special care has been taken to mitigate the effects
of electrical and process-related nonidealities. Shielding, common centroid layout,
extensive ground planes and separate supplies and grounds are among the measures
taken. This chapter describes some details on the Bean prototype implementation.
6.1 Floorplan
Figure 6.1 shows the Bean Prototype floorplan. The floorplan of the prototype core
has three parts, from top to bottom: bias circuits, channels, and auxiliary circuits.
The bias circuits provide the references for the current mirrors of all the circuit
blocks. These references, along with external voltage references and the main clock,
are distributed on vertical lines that cross through all the channels. Wires that
transmit the most critical voltages are shielded using grounded metal planes on top
and on the sides, with the undesired effect of increasing the capacitance to ground.
The most critical lines were routed over diffused strips of alternating N-type and
P-type material on the substrate. This reduces noise coupling through substrate.
The channels were designed to be independent. They only share the power supply,
references and the main clock. Therefore, additional channels can easily be added by
72
6.1. FLOORPLAN 73
Channel 1
Channel 2
Channel 3
Aux. Ckts
Bias Ckts
Buf
fers
Figure 6.1: Floorplan of the Bean prototype core.
stacking. Since all of the common lines run vertically, adding more channels does not
change the connectivity to these lines. Although not implemented in this prototype,
the references must be buffered locally in future versions of the ASIC. This change
will prevent the parasitic inductances in the lines from affecting the dynamic response
of the references.
The auxiliary circuits include a baseline generator, some buffers that are common
to the entire ASIC, a fast-feedback adder, and an ADC. Although these circuits were
placed at the bottom of the ASIC, in future revisions they can be placed at the center
in order to reduce the wire length spread among the channels.
A channel slice is approximately 1.6mm long without the digital memory block.
The channel pitch is 360µm, including the surrounding power bus. This pitch matches
the ADC’s pitch for a square-shaped capacitor array, including power bus, and pro-
duces a well-balanced floorplan. If the number of channels is increased to the nominal
value of 32, the ASIC will be approximately 12mm tall, still much smaller than the
MOSIS maximum reticle size of 21mm a side. If digital memory is included, the
32-channel ASIC shape will be closer to a square.
As shown in Figure 6.2, for each channel the floorplan resembles the signal path.
The charge-sensitive amplifier (CSA), shown in Figure 6.3, is located at the left end of
the channel slice, has a total area of 250µm×330µm, and was divided into 56 square
reticles, 8 tall and 7 wide. Fifty reticles are occupied by feedback metal-insulator-
metal (MIM) capacitors, four hold the amplifier, and the remaining two contain the
feedback switches and logic for reset operation. Among the 50 unit MIM capacitors,
74 CHAPTER 6. THE BEAN PROTOTYPE: IMPLEMENTATION
Figure 6.2: Channel layout.
one implements CCal (CF for the DCal mode), and the other 49 are connected in
parallel to implement COp (used in the SDT mode). This provides the 50× gain ratio
between the two modes of operation. Ground planes on M4 shield lines underneath
the MIM capacitors from cross coupling with the CSA output. Since the CSA is the
Bean circuit most sensitive to external disturbances, it has its own 1.8-volt power
supply, CSAVDD , routed through dedicated pads.
Separated by a power bus, the next circuit blocks in the channel slice are placed
in a section located to the right of the CSA. The signal buffers shown in Figure 6.4,
measuring 270µm× 52µm, are located on the top and bottom regions of this layout
section. Although small in capacitance, the MIM capacitor for baseline level shifting
occupies a large portion of the signal buffer area. The buffer outputs are connected
to the filter, which is shown in Figure 6.5. The filter, located at the center of this
layout section, measures 110µm×150µm. The filter has switches, series and feedback
capacitors, and a fully-differential amplifier implemented with cross-quadded devices
[78] to improve matching. The filter outputs are buffered using the output amplifiers
shown in Figure 6.6. Located to the right of the filter and measuring 110µm×83µm,
the buffers are implemented with cross-quadded devices. All structures are carefully
shielded. As an example, the references run at the center of grounded coaxial metal
shields where possible, to prevent capacitive coupling to other nodes of the circuit.
A separate voltage supply, SCVDD , is used for all the switched-capacitor circuits in
the ASIC to prevent the SC surge currents from affecting sensitive portions of other
circuits.
The ADC, shown in Figure 6.7 and measuring 750µm× 270µm, is located at the
6.1. FLOORPLAN 75
Figure 6.3: Charge-sensitive amplifier layout.
Figure 6.4: Signal buffer layout, including level-shifting capacitor.
76 CHAPTER 6. THE BEAN PROTOTYPE: IMPLEMENTATION
Figure 6.5: SC filter layout.
Figure 6.6: Buffer layout.
6.1. FLOORPLAN 77
Figure 6.7: SAR ADC layout.
rightmost part of the channel. It takes the inputs from the buffer outputs and uses
several references and clock lines running vertically. All of the reference and clock
lines are shielded where possible to reduce capacitive coupling effects. The ADC has
two capacitor arrays located at its left and right ends. The successive approximation
registers, digital logic, and switches are located at the center middle and bottom
portions. The comparator, implemented with cross-quadded transistors, is placed at
the center top. The ADC uses two separate sets of power supply and ground for
analog (AVDD , AG) and digital circuits (DVDD , DG).
The most critical section of the SAR ADC is the capacitor array. For matching
reasons, it is split into 1024 equal-size capacitors, surrounded by approximately 12µm
of dummy capacitors to prevent copper-dishing effects. In order to synthesize the
correct capacitance values, the capacitors are connected in parallel to form blocks. A
common-centroid layout is used among the capacitor blocks to reduce the capacitance
sensitivity to linear gradients in the process.
In a switched-capacitor SAR ADC, parasitic capacitance in parallel with a physical
capacitor degrades the ADC linearity. In order to prevent this effect, grounded shields
are placed as needed in the capacitor array. These shields produce the undesired effect
of an increased capacitance to ground.
The last significant circuit in the ASIC is the adder for fast feedback output. It
is based on the same fully-differential amplifier used in the filter, combined with an
78 CHAPTER 6. THE BEAN PROTOTYPE: IMPLEMENTATION
Figure 6.8: Layout of adder for fast feedback operation.
appropriate feedback network for summing the outputs of all channels. The adder
layout is shown in Figure 6.8.
The Bean pad frame uses pads and pad frame cells obtained from Tanner libraries.
There are pads designed for ground, positive supply voltage, analog input or output,
digital input, and digital output. All of them have ESD protection devices. The
supply pads are connected to the supply buses in the pad frame. Figure 6.9 shows
the Bean prototype layout, including the core described in this section and the pad
frame.
6.2 MOM capacitors
As mentioned earlier in this work, different versions of the ADC were fabricated. The
one included in the Bean prototype uses conservative, 16-fF MIM unit capacitors.
In separate dies, two similar ADCs using more aggressive metal-oxide-metal (MOM)
lateral field capacitors of approximately 4 fF and 2 fF were implemented.
The MOM capacitors present a lower load to the driving network, with a minimum
size that is not limited by design rules. The unit MOM capacitor design was validated
using the Space 3D layout-to-circuit extractor software [75]. The 2-fF unit capacitor
cell was made on a single layer of metal, whereas the 4-fF unit capacitor cell was
6.2. MOM CAPACITORS 79
Figure 6.9: The Bean prototype layout.
80 CHAPTER 6. THE BEAN PROTOTYPE: IMPLEMENTATION
Figure 6.10: Unit MOM capacitor layout.
implemented using two layers. Both layouts are virtually the same, except for inter-
layer connections.
Figure 6.10 shows the layout of the 2-layer, 4-fF unit MOM capacitor. The unit
capacitor horizontal pitch is 2.9µm, and its vertical pitch is 5.8µm. The outer plate is
common to all capacitors and forms a large, continuous structure, whereas the inner
plate is the individual capacitor node. In order to have the ADC linearity within the
specifications, it is crucial that the capacitance between the inner and outer plates be
due only to the unit capacitor cell, without parasitic components from other parts of
the nodes involved. Since the outer plate structure is large (hundreds of micrometers),
it must be carefully shielded to prevent any path for electric field lines to the capacitor
terminals. This was done using grounded shields in metal 3 and 6, with the capacitors
in between. The shield in Metal 3 is evident in Figure 6.10, where a hole was left to
route the inner plate node to the ADC switches.
Figure 6.11 shows a 3-dimensional representation of the MOM capacitor array
layout, and Figure 6.12 shows the same picture from a bottom point of view. Both
pictures are drawn to scale. The top shielding layer, crucial for ADC linearity, has
6.2. MOM CAPACITORS 81
been omitted.
The MOM capacitor array is roughly half the size of the MIM capacitor array,
which was implemented with minimum-size capacitors, and presents a fraction of the
load presented by the MIM capacitor array.
Figure 6.11: 3D view of the single-layer MOM capacitor array.
Figure 6.12: 3D bottom view of the single-layer MOM capacitor array.
Chapter 7
Test Results
The Bean prototype was fabricated on TSMC CM018 technology. On the same run,
different versions of the ADC and additional test structures were included. Tests on
the Bean prototype and the ADCs were carried out at the SLAC National Accelerator
Laboratory between February and July, 2010. The input stimuli were generated
by electronic circuits on custom printed circuit boards (PCBs) driven by a field-
programmable gate array (FPGA), and the outputs were recorded using a personal
computer (PC). This chapter presents the test methodology and results for the ADC
and Bean prototype integrated circuits.
7.1 Test methodology
Custom 4-layer test printed-circuit boards (PCBs) were designed for the Bean proto-
type and the ADCs. The PCBs include low-dropout (LDO) linear voltage regulators
[79], bypass capacitors, 16-bit DACs [80] for analog stimuli generation, switches [81],
adjustable voltage references, buffer-connected amplifiers, voltage translators [82],
and a connector for digital inputs and outputs. Digital inputs are generated with a
250 k gate Spartan-3E FPGA [83] on a Digilent Basys2 FPGA evaluation board [84].
The FPGA also processes the ASIC digital outputs and transmits them to a PC via
a USB port.
82
7.1. TEST METHODOLOGY 83
Figure 7.1: ADC’s testbench printed circuit board layout.
Figure 7.1 shows the ADC test PCB layout, and Figure 7.2 shows the Bean pro-
totype test PCB layout. Both use mainly surface-mounted components.
The FPGA firmware was programmed in Verilog using Xilinx ISE WebPack V10
[85]. For each test, the FPGA runs a program, previously written in simple ASCII
code and loaded onto the FPGA firmware. The program sets the registers for the
DAC inputs, clock dividers, clock masks and other constants. This makes the test
setup flexible enough so that the ASIC references, clock speed and timing can be
modified via software. When executing the program, the FPGA produces a series of
stimuli according to the program values, and records 4096 × 10-bit outputs on each
channel from the Bean, or 16384 × 10−bit outputs from the ADC board. Once the
program has been executed, data recorded on the FPGA is retrieved by the PC into
a file that can be immediately processed using Scilab [86].
The PC communication software was programmed in C++, using the Digilent
Adept SDK libraries [87], and includes routines to load a program onto the FPGA
and to retrieve the FPGA recorded data.
The stimuli for the ADC was generated using an off-chip DAC driven by the
FPGA. The generation of stimuli for the Bean prototype is done with a pulser circuit
implemented on the PCB. The pulser circuit, similar to the precharger circuit shown
84 CHAPTER 7. TEST RESULTS
Figure 7.2: The Bean prototype testbench printed circuit board layout.
7.2. ADC TEST RESULTS 85
in Figure 5.6, is capable of injecting a known amount of charge at a certain time
of each cycle. The pulser reference voltage is driven by an off-chip DAC, and the
switches are driven by the FPGA.
7.2 ADC test results
The ADC tests aim to determine the ADC static performance, in particular, the
integral nonlinearity, or INL, and differential nonlinearity, or DNL. Comparing these
results for the three different versions of ADC (MIMCap, dual-layer MOMCap and
single-layer MOMCap) provides an indication of the relative mismatch among unit
capacitors.
The ADC linearity tests were done with a 50-MHz main clock, enabling a new
conversion every 32 clock cycles. Figures 7.3, 7.4 and 7.5 show the ADC tests results
for the different ADCs.
The three INL plots present a cubic shape that can be attributed to a systematic
design imperfection in the capacitor array, which adds a correlated component to the
unit capacitor mismatch. The design imperfection can be explained as follows. To
reduce the effect of linear gradients on capacitor mismatch, a common-centroid layout
was used, and to reduce the effect of copper dishing or other radial gradients, the
capacitor array was enclosed by approximately 12µm of dummy capacitors. However,
the connection layout in the thermometer-coded portion of the capacitor array is not
random, having the least and most significant portions of the array closer to the edges,
exacerbating the mismatch effects of radial gradients. This theory was confirmed with
behavioral simulations, where a similar cubic-like INL shape was obtained when the
outer capacitors in the array are made larger than the inner capacitors. The effect can
be prevented in future revisions of the ASIC by randomizing the thermometer-coded
capacitor locations, which can be done without affecting the common centroid layout.
The dual-layer MOMCap ADC exhibits a much larger INL than the MIMCap-
based ADC, which can be explained due to a higher sensitivity of MOM capacitors
to the process gradient that produces the correlated portion of the capacitance mis-
match. This explanation points to radial variations of the metal thickness producing
86 CHAPTER 7. TEST RESULTS
0 255 511 767 1023−1.0−0.8−0.6−0.4−0.20.00.20.40.60.81.0
Code
INL
(LS
B)
0 255 511 767 1023−0.20−0.15−0.10−0.050.000.050.100.150.20
Code
DN
L (L
SB
)
Figure 7.3: MIMCap ADC linearity test results.
7.2. ADC TEST RESULTS 87
0 255 511 767 1023−2.0−1.5−1.0−0.50.00.51.01.52.0
Code
INL
(LS
B)
0 255 511 767 1023−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
Code
DN
L (L
SB
)
Figure 7.4: Dual-layer MOMCap ADC linearity test results.
88 CHAPTER 7. TEST RESULTS
0 255 511 767 1023−2.5−2.0−1.5−1.0−0.50.00.51.01.52.02.5
Code
INL
(LS
B)
0 255 511 767 1023−0.5−0.4−0.3−0.2−0.10.00.10.20.30.40.5
Code
DN
L (L
SB
)
Figure 7.5: Single-layer MOMCap ADC linearity test results.
7.2. ADC TEST RESULTS 89
Cap. implementation Unit capacitance Unit capacitance mismatch
MIMCap 16 fF 1.74%dual-layer MOMCap 4 fF 3.91%single-layer MOMCap 2 fF 5.86%
Table 7.1: Unit capacitance values and estimated mismatch for the three differentADCs.
appreciable changes where the lateral-field capacitance is dominant. The single-layer
MOMCap ADC exhibits a larger INL than the dual-layer design, possibly because
the additional layer in the dual-layer design is subject to a smaller process gradient.
The DNL plots show that the three ADCs exhibit no missing codes. From the
DNL amplitudes it is observed that capacitance random mismatch increases as the
unit capacitance is reduced.
From the three ADC test results, the standard deviation of capacitance mismatch
was estimated by computing the relative size of the capacitors in the array. The
capacitance mismatch results are shown in Table 7.1 and include both the random
mismatch component and the correlated mismatch due to radial process variations.
Random mismatch is the dominant component. Correlated mismatch is evident only
when its effect is integrated over a range of codes, such as in INL measurements.
Since the single-layer MOM unit capacitors are half the capacitance of the dual-
layer MOM unit capacitors, if it is assumed that there is no correlation among capac-
itor values, then the expected mismatch is√2× higher. Considering that only one
sample of each ADC was tested, the measured ratio of 1.5 is reasonably consistent
with the proposed explanation of the experimental results.
The single-layer MOMCap ADC DNL is still far from the lower limit of −1, that
would be met if missing codes were present. Therefore, the unit capacitances can be
reduced further, possibly down to 1 fF, without adding missing codes.
The designed ADC power dissipation is 203µW at full speed. However, the first
tests showed a design flaw that caused the bias circuits oscillate due to a poor phase
margin in the feedback loop. To reduce the negative effects of the bias oscillations,
the ADC bias voltage was forced externally to a different value, increasing the average
ADC core power consumption to 245µW at full speed. These numbers do not consider
90 CHAPTER 7. TEST RESULTS
the power consumption of bias circuits.
7.3 The Bean prototype test results
The Bean prototype was tested for power consumption, functionality, linearity, cross-
talk, bandwidth, weighting function, noise, and operation of the fast feedback adder.
In this section, the most important test results are presented.
7.3.1 Power dissipation
The power dissipated by the Bean prototype was measured by measuring the power
supply currents. The measurements include the ASIC core and the bias circuit cur-
rents. To reduce the ripple in the current waveform, shunt capacitors were placed
between the multimeter used to measure the current and the ASIC. The test was
done at the nominal operating speed. The results, which are the same for both
modes of operation, are presented in Table 7.2, which includes SPICE estimates for
comparison.
The mismatch between the simulated and experimental currents can be explained
from operating point averaging effects. The simulated results were obtained via tran-
sient simulations for a single input value, which does not necessarily represent all pos-
sible operating conditions. The experimental measurements are current consumption
averages for an input ramp. Another source of mismatch between the simulated and
experimental results is the multimeter voltage drop, which is roughly proportional
to the measured current. However, since all bias circuits are based on a supply-
insensitive topology, it was assumed that the currents do not change considerably
because of this voltage drop.
Figure 7.6 shows the Bean prototype current distribution among the four power
supplies. Most of the current is drawn from the main analog voltage supply AVDD .
Besides some of the Bean analog circuits, this power supply also feeds 8 buffers for
monitoring purposes (drawing a total of 2.78mA), which will be removed in future
7.3. THE BEAN PROTOTYPE TEST RESULTS 91
Parameter Measurement SPICE estimation RatioI(AVDD) 10.6mA 10.7mA 0.99I(DVDD) 0.58mA 0.75mA 0.77I(SCVDD) 1.56mA 1.8mA 0.87I(CSAVDD) 2.43mA 2mA 1.2
Table 7.2: The Bean prototype current dissipation, measured and simulated.
revisions. Moreover, since the single-layer MOMCap ADC meets the required speci-
fications, this ADC could be used instead of the MIMCap ADC, and its lower input
capacitance could be driven by the filter without the need of buffers. Thus, the buffers
between the filter and the ADC can be removed from future revisions of the chip.
From Chapter 2, the Bean power dissipation specification is 2.19mW per channel,
including the prorated power dissipation of bias circuits and the fast feedback adder.
Although the Bean prototype per-channel raw power dissipation exceeds the spec-
ification, it will be reduced in future revisions by removing the buffers and adding
more channels. The latter change dilutes the bias and adder power overhead. With
these improvements, the estimated per-channel power dissipation will be close to the
specification. The power dissipation of the required LVDS driver to be included in
future revisions has not been considered.
Another means of saving power is to use a power cycling mechanism. Considering
that the beamline is silent 99.5% of the time, the power savings from rather simple
and conservative power cycling would be sufficient to achieve a total power dissipation
well below the specification.
7.3.2 Functionality
Eight of the ASIC internal nodes’ voltages were buffered using the output buffers
and monitored using a Tektronix 2465 oscilloscope: the baseline generator output,
the charge-sensitive amplifier (CSA) output, the signal buffer differential output, the
filter differential output and the ADC differential input. The measured waveforms
confirm the functionality of all blocks.
As an example, Figure 7.7 shows the filter output waveform during the DCAL
92 CHAPTER 7. TEST RESULTS
AVdd (70%)
DVdd (4%)
SCVdd (10%)
CSAVdd (16%)
Figure 7.6: The Bean prototype current distribution.
operation, running at half speed. The picture clearly shows the switched-capacitor
integrator steps1.
The noise observed in DCal mode was higher than expected. Because of the
additional noise, averaging was necessary in some tests in order to obtain meaningful
data.
7.3.3 Linearity
The full channel INL and DNL were computed for both the SDT and DCal modes
using the histogram methodology [88]. The tests were done at full speed, with an
input ramp driven by a DAC. For the SDT mode, Channel 1 was used. For the DCal
mode, Channel 3 was used. Figure 7.8 shows the INL and DNL for the SDT mode,
measured for an input ramp covering 100% of the input range. Figure 7.9 shows the
results of the same test, but using an input ramp with an amplitude 8% higher than
1Due to the limited bandwidth of the buffer, which was not intended to reproduce all the signaldetails, it is not possible to observe the high frequency components when the ASIC operates at itsnominal speed.
7.3. THE BEAN PROTOTYPE TEST RESULTS 93
Figure 7.7: Filter differential output, running at half speed.
the nominal input range. In this case, the ADC references were changed accordingly
in order to measure the out-of-range values. Figure 7.10 presents the INL and DNL
for the the DCal mode, done for a full-scale input ramp. Figure 7.11 shows the
linearity metrics for an input ramp with an amplitude 16% higher than the nominal
input range.
The CSA nonlinearity is dominant in these results. The INL plots show that the
channel linearity is well within the specified value established for the CSA in Chapter
5. This was achieved using the CSA precharge circuit, which injects a negative input
charge that shifts the CSA initial output voltage below the baseline in order to take
advantage of the full range where the CSA open-loop gain is large.
As the input charge range is extended (Figures 7.9 and 7.11), the INL plot displays
a curved shape towards the upper end of the input range. That extra nonlinearity
is due to the lower CSA open-loop gain in that region. The tests with an extended
input range show that the CSA output swing can be safely increased by a few percent,
with a consequent reduction in the feedback capacitance and an improvement in the
SNR, before exceeding the nonlinearity specification.
The DNL plots in Figures 7.8 through 7.11 evidence 10, 7, 4 and 7 missing codes,
94 CHAPTER 7. TEST RESULTS
0 255 511 767 1023−7−6−5−4−3−2−1012
Code
INL
(LS
B)
0 255 511 767 1023−1
0
1
2
3
4
5
6
Code
DN
L (L
SB
)
Figure 7.8: The Bean prototype linearity test results, SDT mode and full-scale inputrange.
0 255 511 767 1023−9−8−7−6−5−4−3−2−101
Code
INL
(LS
B)
0 255 511 767 1023−1
0
1
2
3
4
5
Code
DN
L (L
SB
)
Figure 7.9: The Bean prototype linearity test results, SDT mode and input range of108% of full scale.
7.3. THE BEAN PROTOTYPE TEST RESULTS 95
0 255 511 767 1023−6
−5
−4
−3
−2
−1
0
1
Code
INL
(LS
B)
0 255 511 767 1023−1.0−0.50.00.51.01.52.02.53.03.54.0
Code
DN
L (L
SB
)
Figure 7.10: The Bean prototype linearity test results, DCal mode and full-scale inputrange.
0 255 511 767 1023−12
−10
−8
−6
−4
−2
0
Code
INL
(LS
B)
0 255 511 767 1023−1.0−0.50.00.51.01.52.02.53.03.54.0
Code
DN
L (L
SB
)
Figure 7.11: The Bean prototype linearity test results, DCal mode and input rangeof 116% of full scale.
96 CHAPTER 7. TEST RESULTS
respectively. In principle, since ADC in the Bean prototype is the same as tested
individually, there should be no missing codes. However, the extra inductance in the
longer reference traces in the Bean prototype layout causes the reference nodes to
ring as the SAR drives the ADC switches. This affects the codes where the two or
three most significant bits transition. This problem will be solved in future revisions
of the Bean by buffering the reference voltages internally.
The DNL in the DCal mode looks smaller than in the SDT because of the higher
input-referred noise in the DCal mode, which smears out the DNL plot and hides some
of its features [89]. In the DCal mode, the input-referred noise produces dithering,
randomizing the DNL errors of the converter [90].
7.3.4 Crosstalk
The crosstalk test aims to determine the gain from the input of a channel, namely
the aggressor channel, to the output of another channel, namely the victim channel.
In order to measure the crosstalk effects, a test is executed where the victim channel
input remains unchanged, while the aggressor channel input is ramped. Measuring
the changes in the victim channel’s output, and assuming linearity, allows finding the
crosstalk gain.
The crosstalk test was done for both modes of operation. Channel 1 was the
aggressor, whereas Channels 2 (the channel adjacent to the aggressor channel) and
3 (the channel non-adjacent to the aggressor channel) were the victims. In order to
measure the output of the victim channels for zero input, the ADC references were
shifted to avoid saturation at the lower input range limit. This was done without
changing the ADC gain. To prevent the crosstalk between the pulsers from affecting
the Bean prototype crosstalk measurements, the victim channels’ inputs were left
open.
Figure 7.12 shows the crosstalk test result in the SDT mode, and Figure 7.13
shows the crosstalk test result in the DCal mode. Results in the SDT mode are raw
data, whereas results in the DCal mode are averages among 10 runs, which was done
to reduce the effects of noise.
7.3. THE BEAN PROTOTYPE TEST RESULTS 97
116 256 512 768 1024
96
98
100
102
104
106
108
Channel 1 output code
Cha
nnel
2 a
nd 3
out
puts
cod
e, c
onst
ant i
nput
Channel 2Channel 3
Figure 7.12: Crosstalk effects of Channel 1 input ramp on Channels 2 and 3, SDTmode.
98 CHAPTER 7. TEST RESULTS
256 512 768 1024
85
90
95
100
105
Channel 1 output code
Cha
nnel
2 a
nd 3
out
puts
cod
e, c
onst
ant i
nput
Channel 2Channel 3
Figure 7.13: Crosstalk effects of Channel 1 input ramp on Channels 2 and 3, DCalmode.
7.3. THE BEAN PROTOTYPE TEST RESULTS 99
Considering a crosstalk transfer function from aggressor to victim channels, the
measured crosstalk in SDT mode is not linear. The worst-case crosstalk gain, defined
as the change in the victim channel’s output due to a unit change in the aggressor
channel’s input, is approximately 1.4% of the nominal channel gain in both victim
channels. The DCal mode worst-case crosstalk gain is 1.65% of the nominal gain for
the adjacent channel, and 1.3% of the nominal gain for the non-adjacent channel.
From the similarity of the crosstalk gains between adjacent and non-adjacent
victim channels, it is concluded that most of the ASIC crosstalk in both modes of
operation is not due to direct coupling between the aggressor and victim channels, but
rather the result of second-order effects such as power supply and reference coupling.
If necessary, this can be improved in future revisions of the ASIC by increasing the
number of power supply pins and buffering the references locally.
7.3.5 Bandwidth
In the Bean operation, there will be no correlation between consecutive inputs in any
channel. Therefore, previous inputs should not affect the current output. In other
words, channel memory effects must be minimized. The bandwidth test aims to find
the residual effect of an input on the output of subsequent cycles. The test consists
of injecting a non-negligible input charge at a known moment, and measuring the
outputs on the pre- and post-injection cycles. Ideally, the outputs in the pre- and
post-injection cycles match.
The SDT mode bandwidth test result is shown in Figure 7.14, where the input
at the charge injection cycle was 82% of the full-scale range, and the output exceeds
the axis limits. The injected input occurs on cycle 12. The difference between the
outputs of cycles 13 and 11 is −1LSB.
In DCal mode, 10 runs were executed to reduce the noise effects. The input
stimulus was set at 75% of the full-scale range. The average difference between post-
and pre-injection outputs among 10 runs is 0.9LSB. Figure 7.15 shows the output of
one of the runs. The output at the charge injection cycle exceeds the axis limits.
100 CHAPTER 7. TEST RESULTS
9 10 11 12 13 14 15 1645
50
55
60
65
70
75
80
85
Cycle number
Out
put c
ode
Figure 7.14: Bandwidth test result, SDT mode.
7.3. THE BEAN PROTOTYPE TEST RESULTS 101
9 10 11 12 13 14 15 16200
205
210
215
220
225
230
235
240
Cycle number
Out
put c
ode
Figure 7.15: Bandwidth test result, DCal mode.
102 CHAPTER 7. TEST RESULTS
7.3.6 Weighting function measurements
The front end weighting function was measured according to its definition described
in Subsection 3.1.5. This was done by injecting a small charge at different times
within a cycle, and measuring the output at the measurement time. The weighting
function result is quantized in both, amplitude and time. The amplitude resolution
is related to the input signal amplitude, whereas the time resolution is limited by the
smallest time step in the clock. Since the fastest clock runs only 16× faster than the
input pulse rate, the measured weighting function time resolution is rather coarse.
Inverting the clock allowed to double the frequency of clock rising edges, and using a
special feature of the FPGA Digital Clock Manager (DCM) the clock was shifted by
90◦, making possible the measurement of 64 points per each of the weighting functions
tested.
As mentioned earlier, the slow reset-release operation reduces the positive slope
of the weighting function, thus lowering the series noise coefficient. As implemented,
the Bean is capable of eight different reset-release schemes. The slowest reset-release
scheme (namely, reset-release scheme 128) considers one subcycle in full reset, corre-
sponding to the maximum VGS in the reset transistor, followed by a long reset-release
spanning 7 subcycles. The fastest reset-release scheme (scheme 255) considers eight
subcycles in full reset, followed by an abrupt reset-release. Table 7.3 summarizes the
details on the different reset-release schemes used in the DCal mode. The schemes
were named after the decimal value of the FPGA register that establishes the reset-
release scheme. In the SDT mode, the slow reset-release scheme used corresponds to
scheme 224. In the DCal mode, the reset-release scheme 128 is not practical, since a
single subcycle for full reset is insufficient to discharge the CSA feedback capacitor
completely.
Figures 7.16 and 7.17 show the SPICE-simulated and measured weighting func-
tions in SDT mode, for slow and fast reset-release schemes. Figures 7.18 and 7.19
show the SPICE-simulated and measured weighting functions in DCal mode, bypass-
ing the filter in the signal path, for eight different reset-release schemes. Figures 7.20
and 7.21 show the SPICE-simulated and measured weighting functions in DCal mode,
7.3. THE BEAN PROTOTYPE TEST RESULTS 103
Scheme Binary value Subcycles on full reset Subcycles on reset-release128, Slow 10000000 1 7
192 11000000 2 6224 11100000 3 5240 11110000 4 4248 11111000 5 3252 11111100 6 2254 11111110 7 1
255, Fast 11111111 8 0
Table 7.3: Reset-release schemes used in the DCal mode.
including the filter in the signal path. Finally, Figure 7.22 shows a series of weight-
ing function measurements for different clock frequencies, where correlated double
sampling (CDS) was digitally implemented. In order to implement CDS, the channel
output is measured on two consecutive cycles. First, the CSA baseline is filtered and
measured for zero input stimulus. On the next cycle, without resetting the CSA,
the output due to an input stimulus is filtered and measured. The CDS output is
the difference between both measurements, and the random baseline fluctuations are
cancelled out. Since the digital CDS implemented relies on measuring the output in
two consecutive cycles, the maximum input rate is halved. With the exception of the
weighting functions for CDS, all weighting functions were measured at full speed.
The front-end noise coefficients were computed from the weighting functions ac-
cording to the definition presented in Subsection 3.1.3. The resulting noise coefficients
were used to compare the front-end’s filtering properties under different conditions.
Due to the negligible contributions of parallel and flicker noise components, the front-
end output noise power is proportional to the series noise coefficient NW .
Table 7.4 presents examples of the series noise coefficients NW computed from
measured weighting functions. The computed series noise coefficients have been nor-
malized with respect to the fast reset-release value, filter bypassed. The results show
that the slow reset-release noise filtering ability is not sensitive to the reset scheme
as long as there are at least two cycles for slow reset-release. The results also show
that the combined effect of a switched-capacitor filter and a slow reset-release scheme
is effective in reducing the readout noise power in the DCal mode. Particularly,
104 CHAPTER 7. TEST RESULTS
0 154 3080.0
0.2
0.4
0.6
0.8
1.0
time (ns)
Wei
ghtin
g fu
nctio
n
Fast reset
Slow reset
Figure 7.16: SPICE-simulated weighting functions, SDT mode.
0 154 3080.0
0.2
0.4
0.6
0.8
1.0
time (ns)
Wei
ghtin
g fu
nctio
n
Fast reset
Slow reset
Figure 7.17: Measured weighting functions, SDT mode.
7.3. THE BEAN PROTOTYPE TEST RESULTS 105
0 154 3080.0
0.2
0.4
0.6
0.8
1.0
time (ns)
Wei
ghtin
g fu
nctio
nSlow reset
Reset 192
Reset 224
Reset 240
Reset 248
Reset 252
Reset 254
Fast reset
Figure 7.18: SPICE-simulated weighting function, DCal mode, no filter.
0 154 3080.0
0.2
0.4
0.6
0.8
1.0
time(ns)
Wei
ghtin
g fu
nctio
n
Slow reset
Reset 192
Reset 224
Reset 240
Reset 248
Reset 252
Reset 254
Fast reset
Figure 7.19: Measured weighting function, DCal mode, no filter.
106 CHAPTER 7. TEST RESULTS
0 154 3080.0
0.2
0.4
0.6
0.8
1.0
time (ns)
Wei
ghtin
g fu
nctio
n
Slow reset
Reset 192
Reset 224
Reset 240
Reset 248
Reset 252
Reset 254
Fast reset
Figure 7.20: SPICE-simulated weighting function, DCal mode.
0 154 3080.0
0.2
0.4
0.6
0.8
1.0
time(ns)
Wei
ghtin
g fu
nctio
n
Slow reset
Reset 192
Reset 224
Reset 240
Reset 248
Reset 252
Reset 254
Fast reset
Figure 7.21: Measured weighting function, DCal mode.
7.3. THE BEAN PROTOTYPE TEST RESULTS 107
0 154 308 462 6160.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
time (stretch * ns)
Nor
mal
ized
wei
ghtin
g fu
nctio
n
stretch = 4
stretch = 8
stretch = 16
stretch = 32
stretch = 64
Figure 7.22: Measured weighting function with CDS scheme, DCal mode.
the series noise coefficient NW computed from the measured weighting function of
the reset-240 scheme, including filter, has a relative series noise coefficient of 61%
with respect to that of a fast reset-release when bypassing the filter. An analysis of
the components of NW due to the positive and negative slopes shows that 75% of
the series noise coefficient comes from the positive slope (slow reset-release action),
whereas only 25% comes from the negative slope (filtering action). Further analysis
shows that the component of NW due to the negative slope is reduced by 56% due to
the filter action, whereas the slow reset-release action reduces the component due to
the positive slope by 30%. Although the accuracy of these measurements is affected
by the clock jitter in the weighting function measurement, they are representative of
the values expected from the design equations.
7.3.7 Noise measurements
The front-end input-referred noise, including contributions from the pulser, the CSA,
the buffers, the filter and the ADC, was measured using the histogram method [91].
By comparing the results with oscilloscope-based noise measurements, it was found
that dominant noise contributors in the front-end are the CSA, the filter, and the
108 CHAPTER 7. TEST RESULTS
Reset scheme NW for DCal, filtered NW for DCal, no filter128 0.63 0.71192 0.66 0.71224 0.7 0.73240 0.61 0.7248 0.64 0.72252 0.69 0.75254 0.7 0.79255 0.96 1
Table 7.4: Series noise coefficients computed from measured weighting functions,normalized to the series noise coefficient for the fast reset-release scheme, non-filtered.
ADC.
In the SDT mode, the RMS noise has an average of 0.6LSB. This measurement
results do not change appreciably with the slow reset-release scheme, which in princi-
ple should reduce noise by 20% compared to the fast reset-release in SDT. Therefore,
it is concluded that most of the noise is due to the ADC and can be reduced in fu-
ture revisions by increasing the transconductance of the input transistors in the ADC
comparator preamplifier. The measured noise is low enough so no off-chip digital
averaging was needed in order to process data in SDT mode.
In the DCal mode, the RMS noise was higher than expected, and it was not dom-
inated by the ADC noise. Although it is still possible to use the ASIC and calibrate
the detectors for known input signals when the front-end is noisy, by averaging a large
number of samples in the digital domain, it is important to understand the source of
the excess of noise.
One cause for the excess of noise is the input node capacitance, since it is not
well defined and noise is proportional to it. The input node capacitance has several
components, but is dominated by the board capacitance in the current test setup.
Once installed in an actual detector system, the input capacitance should be close to
40 pF due to detector capacitance and wires. Measurements in the unpopulated test
PCB yield an input node capacitance of 49 pF. This result does not include the ad-
ditional capacitance components due to connectors, capacitors, the Bean ASIC, and
other board components. For a more accurate estimate of the input node capacitance
7.3. THE BEAN PROTOTYPE TEST RESULTS 109
in the DCal mode, intentionally large, known shunt capacitors of various sizes were
added at the input node, and noise was measured. A linear regression among five
results made it possible to estimate the base input capacitance in the DCal mode to
be 75.5 pF. The ratio between this value and the specified value of 40 pF partially
explains the excess noise found at the channel output. Noise measurements in DCal
mode were scaled according to the ratio between the designed and actual input ca-
pacitances. Thus, the RMS noise measurements in the DCal mode are estimates of
the noise that would be measured if the input node capacitance were 40 pF.
The estimated noise in the DCal mode is 0.62LSB when the filter is bypassed,
and 1.41LSB when the filter is placed in the signal path. Considering that the filter
and the slow reset-release were designed to reduce the dominant (series) noise power
component by 35%, there is approximately 1.35LSB of RMS noise added by the filter
due to its internal noise sources. That amount of noise is a consequence of a design
flaw in the filter design: in Equation 5.17, the factor N was not considered.
In order to demonstrate the series noise filtering effects of the integrator, the front-
end input-referred series noise was artificially increased so that the filter internal noise
could be neglected in measurements of the output noise. This was done by adding
known, large shunt capacitors at the front-end input since the front-end series noise
is proportional to the input capacitance. Then the noise measurements for different
signal paths, including and bypassing the filter, will show the filter effectiveness.
The experiment was run for all of the different reset schemes at a clock rate 32×slower than the nominal clock rate, which reduces the effects of the input capacitance
dependent CSA bandwidth on the front-end filtering.
Output noise measurements were made in the DCal mode for three different signal
paths: bypassing the filter, including the filter, and including a digital CDS scheme
along with the filter. Due to the lower clock frequency, it is expected that the slow
reset-release scheme is not as effective as in the nominal clock condition. Therefore
the CDS scheme will be considerably better than the simple filtered case. The results
for reset scheme 240 are shown in Figure 7.23.
110 CHAPTER 7. TEST RESULTS
0 100 200 300 400 500 6000
10
20
30
40
50
60
70
80
90
Total capacitance at input node (pF)
Out
put n
oise
(LS
B)
Non−filtered
Filtered
CDS
Figure 7.23: Measured noise as a function of total input capacitance, for three differentsignal paths.
The input capacitance, shown on the horizontal axis, includes the 75.5 pF esti-
mated board capacitance. The lines exhibit some curvature at high input capaci-
tances due to the CSA bandwidth reduction, which affects the weighting function
positive and negative slopes. The measurements show an average noise reduction of
29% in the filtered case, and 73% in the filter+CDS scheme. These results are in
agreement with the expectations from weighting function calculations for the specific
test conditions. All the noise measurements consistently show that the slow reset-
release technique is effective in reducing the reset noise, although not as effective as
CDS.
7.3.8 Fast feedback adder
The fast feedback adder was designed for a gain of 1/3 per channel. The adder
operation was tested by injecting known inputs in all channels and measuring the
adder output. The measured gains for the three channels are shown in Table 7.5,
and include the influence of both the intrinsic channel gain due to the CSA feedback
capacitor and the adder gain.
7.3. THE BEAN PROTOTYPE TEST RESULTS 111
Channel Adder gain
1 0.3452 0.3443 0.329
Table 7.5: Adder gain from all channels.
500 1000 1500 2000 2500 3000 3500 40000
100
200
300
400
500
600
700
800
900
Sample number
Out
put c
ode
Ch01
Ch02
Ch03
Adder
Figure 7.24: Adder test results.
Figure 7.24 shows the outputs of the three channels and the adder, when the three
channels inputs are ramps that span nearly the full-scale range. The discontinuity
slightly visible in the plots around codes 256, 512 and others is due to the effect of the
inductance in the ADC reference nodes, exacerbated in this test since all the ADC
inputs are alike. This problem, not seen in the standalone ADCs, can be fixed by
buffering the references internally.
112 CHAPTER 7. TEST RESULTS
VDDVDD
VBout
CPad
M1M2
M3
M4
M5
R1
R2
R3
C1
C2
C3
Adj
Pad connection
Figure 7.25: Supply-insensitive bias circuit used in the Bean prototype. The padconnection is shown.
7.4 Summary of design flaws
The first Bean prototype has two design flaws that must be corrected in future re-
visions. Fortunately, it was still possible to overcome these problems and obtain
meaningful data from the ASIC tests.
The first flaw found is located in the supply-insensitive bias circuits. A schematic is
shown in Figure 7.25. Due to a poor phase margin, all the Bean prototype bias circuits
oscillate at nearly 8MHz. The internal RC filters implemented with resistors Ri and
capacitors Ci reduce the amplitude of the oscillations considerably, but the oscillatory
behavior moves the bias circuits’ DC voltages to useless levels. The problem occurred
because of the 1-pF pad capacitance (CPad), which loaded the bias circuits’ external
nodes and moved their nondominant poles closer to the dominant poles. The flaw
was not evident in post-layout transient simulations because a step in the power
supply was necessary to trigger the oscillatory behavior. The problem was fixed by
modifying the ASIC, by cutting the metal traces that connect the pads to the bias
circuits. Upon removing the pad connections, the bias circuits worked as designed.
The second flaw found is in the filter amplifier design. Due to an error in Equation
5.17, the factor N was omitted, and the contribution of the filter amplifier to the noise
power was 8× higher than intended.
Chapter 8
Conclusion
8.1 Summary
Microelectronics has played a crucial role in instrumentation systems for modern
particle physics experiments. With the introduction of custom monolithic circuits,
particle physicists are able to obtain highly detailed images of the outcome of millions
of collisions, and to process them in colossal computer networks. The information
captured by millions of detector channels makes it possible to reconstruct the trajec-
tories of thousands of particles leaving the collision point, and to measure the energy
and its distribution among different regions of the detector.
The instrumentation for particle physics experiments has reached maturity in the
sense that state-of-the-art techniques in circuit and devices design are systematically
used. Among others, it is common to find custom detectors [92] [93], radiation-
tolerant circuits [94] [95], high-speed analog memory [5] [96], active pixel sensors [97]
[98], and integrated ADCs [99]. With ever-increasing collision energy, the electronic
design for newer particle physics experiments instrumentation becomes more chal-
lenging. Among the challenges addressed by this work are a signal path designed
to cope with 100% occupancy, achieved with real-time analog-to-digital conversion,
and a low-latency output consisting on the sum of all channels, implemented using
an analog adder. The latter will be used for diagnosing and real-time tuning of the
colliding beams in the ILC.
113
114 CHAPTER 8. CONCLUSION
Although ubiquitous, switched-capacitor circuits do not have a strong presence
in the particle physics arena, where they have been used mainly in analog memory
and ADCs. In this work, switched-capacitor circuits are used to implement a pulse
shaper, demonstrating that it is possible to produce quasi-triangular and trapezoidal
weighting functions with great accuracy. Although suboptimal in terms of noise-
filtering properties due to the finite sampling frequency and consequent aliasing, a
switched-capacitor pulse shaper can produce precisely-defined weighting functions
with time constants that depend only on capacitor ratios and an external clock.
This is a competitive alternative for RC-defined time constants, which depend on
on-chip resistors and capacitors values subject to different process variations. As
newer technologies enter into the area of particle physics experiments electronics, it
is foreseeable to find in the future more pulse shapers based on switched-capacitor
circuits. The analysis and design techniques in this work can thus serve as a starting
point for future research.
In this work, switched-capacitor circuits were also used to implement a slow reset-
release technique. Through capacitance charging, charge sharing and discharging,
VGS is reduced slowly in order to slowly open the reset switches, thus reducing the
corresponding slope in the weighting function. This reduces the output noise due to
split doublets. Although not as effective as CDS in terms of noise filtering, the slow
reset-release technique is simpler and represents a competitive solution when the time
allocated for processing signals is limited.
As process miniaturization advances, transistors become more difficult to model,
and the gm/ID design technique has become increasingly important. Particularly
relevant in instrumentation for particle physics experiments is noise characterization,
which can be done effectively using the gm/ID technique as described in Chapter 3.
If properly used, it allows the convergence to an optimal design in fewer iterations.
The scaling of mainstream VLSI technology leads to severe constraints on dynamic
range. Noise does not scale as the power supply voltage, and circuit designers must use
ingenious techniques to circumvent the problems related to the decreasing dynamic
range. In the circuit presented in this work, this issue was addressed using two
different techniques: the use of charge-sensitive amplifier (CSA) precharge to take
8.2. SUGGESTIONS FOR FUTURE WORK 115
full advantage of the amplifier output range over which the linearity is acceptable,
and the use of fully-differential circuits, to increase the output swing while keeping
all transistors operating in the active region. In the future, on-chip digital calibration
will make it possible to correct the distortion of a CSA with an increased output
range that exceeds the limits for an acceptable linearity.
The improvements in photolithography over the last decade have made it possible
to create precise structures in the layout level of a circuit. As an example, passive RF
components can be carefully tailored in CMOS technologies. The matching of lateral
field capacitors has been improved. This makes it possible to create capacitor arrays
out of the parasitic capacitances between metal lines. Proper metal shielding through
a careful layout, as presented in this work, permitted the successful implementation of
a capacitor array sufficiently linear for a 10-bit successive-approximation register ADC
using 2-fF unit capacitors in a 180-nm process. The low resulting input capacitance
is easy to drive and produces savings in area and power consumption.
Although not part of the design process, testing a chip with a large number of
control lines can be a challenge. In this work, an FPGA provided the digital control
signals and produced the analog input stimuli via on-board DACs. The FPGA also
served as an off-chip digital memory, providing a seamless link to the personal com-
puter used for post processing the Bean outputs. Although it takes longer to set up
an FPGA-based ASIC testbench than to use conventional laboratory equipment, the
FPGA is fully programmable at the level of logic gates and eliminates the need of a
stack of signal generators and logic analyzers.
8.2 Suggestions for future work
There is no such thing as amagic bullet in instrumentation systems for particle physics
experiments. Design tradeoffs aim to address specific goals at the inevitable cost of
other variables in the design space. The classic signal path architecture for parti-
cle physics experiments, including a detector, a CSA and a filter, has not changed,
and will surely remain for some time. The design process, involving a minimization
116 CHAPTER 8. CONCLUSION
of power consumption while meeting noise and other specifications, requires a thor-
ough understanding on the coupling among detector, CSA and filter variables. One
part cannot be optimized without considering the whole. And although the three
basic blocks have not suffered major changes from a behavioral point of view, new
techniques can provide more choices in the actual implementation.
One of the most important topics in particle physics instrumentation in the 70’s
was finding the optimal pulse shape for noise minimization. Although some optimal
shapes, such as the cusp [20], were impossible to synthesize using real circuits, it was
interesting to determine the fundamental lower limit of noise that could be achieved
through them. Departure from the optimal pulse shape leads to additional noise.
However, with the use of switched-capacitor circuits, it may be possible to synthesize
arbitrary weighting functions by implementing different integrator gains in different
cycles. Provided a sufficiently high sampling rate and an appropriate anti-alias filter,
the resulting pulse shape can be near optimal. This work may serve as a base for
future research on the synthesis of optimal pulse shapes using switched-capacitor
circuits.
The analog sampled data processing in switched-capacitor circuits, benefiting from
high speeds achieved by transistors with shorter channel, can certainly improve the
weighting function synthesis techniques. A completely different approach, still ex-
pensive in terms of power consumption due to more stringent ADC specifications,
is to process the CSA output in the digital domain. However, with the state-of-
the-art ADC architectures in newer technologies, future instrumentation systems for
particle physics experiments will certainly include more processing in the digital do-
main. This approach is worth exploring, especially as technology continues to scale
to smaller dimensions.
The lessons learned during the design and testing of the Bean prototype will
prompt corrections, improvements, and upgrades for future revisions. The most ur-
gent corrections consist of designing the bias circuit feedback loop to achieve adequate
stability margins, and editing the filter OTA design to meet the noise specifications.
The performance of the MOMCap ADC, along with its reduced capacitive input
capacitance and area make it an attractive candidate for the next Bean prototype
8.2. SUGGESTIONS FOR FUTURE WORK 117
version. The capacitor array can be corrected in order to reduce its sensitivity to radial
gradients and improve its linearity. Moreover, since the effects of radial gradients
appeared in all of the ADCs tested, the ADC nonlinearity might be leveraged to
cancel out the CSA nonlinearity, allowing for an extended output swing. For a fixed
target SNR, this would imply a reduction in the CSA current consumption.
It was found during testing that the wire bonds and the long vertical metal lines
in the Bean layout add a non-negligible parasitic inductance in series to the reference
voltages. Combined with the lines’ parasitic capacitance, this can produce ringing in
the voltage references. The most noticeable effects of such ringing are missing codes
in the ADC. In order to mitigate the effects of ringing in future revisions of the Bean,
the reference nodes should be buffered internally using source followers.
A clock recovery circuit will be necessary to extract the clock information from
the collisions. Another needed feature is the implementation of power cycling in order
to meet the power consumption specifications. Finally, for complete functionality, a
digital memory array with error-correcting capabilities and an LVDS output driver
can be included in the next revision.
The natural radiation tolerance of the 180-nm process should be studied using the
enclosed layout transistors (ELTs) fabricated in the Bean prototype run. The infor-
mation from this study will allow the design of future revisions of the ASIC to meet
radiation tolerance specifications. The ESD protection circuits must be improved in
order to minimize the leakage current, and to prevent such leakage from increasing
after irradiation.
The 2-fF capacitor matching in the MOM capacitor array exceeds the expectations
based on the matching data provided by the foundry and other work in the area.
The capacitors are fully compatible with any digital CMOS process. It would be
interesting to further investigate the capacitor matching limit and determine how it
varies among technologies.
Appendix A
The Bean and ADC pinout
The Bean prototype has 72 pads and was bonded to an 80-lead package from Spectrum
Semiconductor Material (SSM). The package SSM part number is CQZ08004. The
Bean bonding diagram is shown in Figure A.1.
The MIMCap ADC prototype has 24 pins, and the MOMCap ADCs have 20 pins.
Both were bonded to a 44-lead package, SSM part number CQZ04408. The three
ADC bonding diagrams are shown in Figures A.2 through A.4
Table A.1 shows the Bean pinout and Table A.2 shows the ADC pinout, common
for the three ADCs.
Pin number Pin name Description
1 En_PrChrg_Int Internal precharging circuit enable
2 En_PrChrg_Ext External precharging circuit enable
3 V_Ck_CSA CSA clock
4 VRST_CSA CSA reset
5 VRST_Full CSA full reset
6 V_OpMode_CSA Operation mode select
7 VRST_Bffr Buffer reset
8 VSH_Fltr Filter sample/hold
9 VRST_Fltr Filter reset
10 V_Ck_Fltr Filter clock
118
119
Pin number Pin name Description
11 V_OpMode_Out Filter bypass/select
12 V_Icm_Des_FF Adder input common mode reference
13 VCM_Addr Adder amplifier output common mode reference
14 V_Smpl_Addr Adder sample/hold
15 V_Ck_ADC ADC clock
16 En_ADC ADC enable
17 En_FF_ADC Adder ADC enable
18 AG Analog ground
19 NC No connection
20 NC No connection
21 NC No connection
22 NC No connection
23 AG Analog ground
24 AVdd Analog Vdd
25 DVdd Digital Vdd
26 DVdd Digital Vdd
27 Do_FF Adder digital output
28 Do_Ch03 Channel 3 digital output
29 Do_Ch02 Channel 2 digital output
30 Do_Ch01 Channel 1 digital output
31 DG Digital ground
32 DG Digital ground
33 Vbaseline_Mon Baseline voltage monitor
34 Vo_CSA_Mon CSA output voltage monitor (Ch01)
35 VadcinP_Mon ADC positive input (Ch01)
36 VadcinM_Mon ADC negative input (Ch01)
37 Vfip_Mon Filter positive input (Ch01)
38 Vfim_Mon Filter negative input (Ch01)
39 Vfop_Mon Filter positive output (Ch01)
120 APPENDIX A. THE BEAN AND ADC PINOUT
Pin number Pin name Description
40 Vfom_Mon Filter negative output (Ch01)
41 NC No connection
42 NC No connection
43 Vref_P ADC positive reference
44 V_CM_ADC ADC common-mode reference
45 Vref_COM ADC common reference
46 Vref_M ADC negative reference
47 V_icm_Des Filter input common mode reference
48 Vcm_Fltr Filter output common mode reference
49 Vgnd_Shift Ground reference (voltage shifting)
50 V_Shift Shifting voltage reference
51 Adj_Comp Comparator bias adjust
52 Adj_OutBffr_1 Output buffer bias adjust (1)
53 Adj_OutBffr_2 Output buffer bias adjust (2)
54 Adj_Fltr_1st Filter bias adjust (1)
55 Adj_Fltr_2nd Filter bias adjust (2)
56 Adj_Bffr Signal buffer bias adjust
57 Adj_CSA_PMOS CSA PMOS bias adjust
58 Adj_CSA_NMOS CSA NMOS bias adjust
59 Vdd_Ref Precharge Vdd reference
60 Vdd_CSA CSA Vdd
61 Vdd_CSA CSA Vdd
62 AG Analog ground
63 AG Analog ground
64 AVdd Analog Vdd
65 Vi_Ch01 Ch01 input
66 V_PrChrg_01 Ch01 precharge node for external capacitor
67 AG Analog ground
68 AVdd Analog Vdd
121
Pin number Pin name Description
69 Vi_Ch02 Ch02 input
70 V_PrChrg_02 Ch02 precharge node for external capacitor
71 AG Analog ground
72 AVdd Analog Vdd
73 Vi_Ch03 Ch03 input
74 V_PrChrg_03 Ch03 precharge node for external capacitor
75 SCVdd SC Vdd
76 SCVdd SC Vdd
77 SCVdd SC Vdd
78 AG Analog ground
79 NC No connection
80 NC No connection
Table A.1: The Bean pinout.
Pin number Pin name Description
1 NC No connection
2 AG Analog ground (NC in MOMCap ADC)
3 Vim ADC negative input
4 Vcom ADC common reference
5 Vm ADC negative reference
6 Vp ADC positive reference
7 Vcom ADC common reference
8 Vip ADC positive input
9 AG Analog ground (NC in MOMCap ADC)
10 NC No connection
11 NC No connection
12 NC No connection
13 NC No connection
122 APPENDIX A. THE BEAN AND ADC PINOUT
Pin number Pin name Description
14 NC No connection
15 AG Analog ground
16 AG Analog ground
17 Vcm ADC common-mode reference
18 RST ADC reset
19 NC No connection
20 NC No connection
21 NC No connection
22 NC No connection
23 NC No connection
24 NC No connection
25 AG Analog ground (NC in MOMCap ADC)
26 Dout ADC digital output
27 DG Digital ground
28 Ck ADC clock
29 DVdd Digital Vdd
30 En ADC enable
31 DG Digital ground
32 AG Analog ground (NC in MOMCap ADC)
33 NC No connection
34 NC No connection
35 NC No connection
36 NC No connection
37 NC No connection
38 Vadj ADC bias adjust
39 AVdd Analog Vdd
40 AVdd Analog Vdd
41 AG Analog ground
42 NC No connection
123
Pin number Pin name Description
43 NC No connection
44 NC No connection
Table A.2: ADC pinout.
124 APPENDIX A. THE BEAN AND ADC PINOUT
Figure A.1: The Bean bonding diagram.
125
Figure A.2: Dual-layer MOMCap ADC bonding diagram.
126 APPENDIX A. THE BEAN AND ADC PINOUT
Figure A.3: Single-layer MOMCap ADC bonding diagram.
127
Figure A.4: MIMCap ADC bonding diagram.
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