tfp410 ti panelbus™ digital transmitter

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TFP410SLDS145C –OCTOBER 2001–REVISED DECEMBER 2014

TFP410 TI PanelBus™ Digital Transmitter1 Features 3 Description

The TFP410 device is a Texas Instruments1• Digital Visual Interface (DVI) Compliant(1)

PanelBus™ flat-panel display product, part of a• Supports Pixel Rates up to 165 MHz (Including comprehensive family of end-to-end DVI 1.0-1080 p and WUXGA at 60 Hz) compliant solutions, targeted at the PC and consumer

• Universal Graphics Controller Interface electronics industry.– 12-Bit, Dual-Edge and 24-Bit, Single-Edge The TFP410 device provides a universal interface to

Input Modes allow a glueless connection to most commonlyavailable graphics controllers. Some of the– Adjustable 1.1 V to 1.8 V and Standard 3.3 Vadvantages of this universal interface includeCMOS Input Signal Levelsselectable bus widths, adjustable signal levels, and– Fully Differential and Single-Ended Input differential and single-ended clocking. The adjustable

Clocking Modes 1.1-V to 1.8-V digital interface provides a low-EMI,– Standard Intel 12-Bit Digital Video Port high-speed bus that connects seamlessly with 12-bit

or 24-bit interfaces. The DVI interface supports flat-Compatible as on Intel™ 81x Chipsetspanel display resolutions up to UXGA at 165 MHz in• Enhanced PLL Noise Immunity24-bit true color pixel format.

– On-Chip Regulators and Bypass Capacitors forThe TFP410 device combines PanelBus circuitReducing System Costsinnovation with TI’s advanced 0.18 μm EPIC-5 CMOS• Enhanced Jitter Performance process technology and TI’s ultralow ground

– No HSYNC Jitter Anomaly inductance PowerPAD package. The result is acompact 64-pin TQFP package providing a reliable,– Negligible Data-Dependent Jitterlow-current, low-noise, high-speed digital interface• Programmable Using I2C Serial Interfacesolution.

• Monitor Detection Through Hot-Plug and ReceiverDetection Device Information(1)

• Single 3.3-V Supply Operation PART NUMBER PACKAGE BODY SIZE (NOM)• 64-Pin TQFP Using TI’s PowerPAD™ Package TFP410 HTQFP (64) 10.00 mm × 10.00 mm

• TI’s Advanced 0.18-µm EPIC-5™ CMOS Process (1) For all available packages, see the orderable addendum atthe end of the data sheet.Technology

• Pin Compatible With SiI164 DVI Transmitter Typical HDMI Interface(1) The digital visual interface (DVI) specification is an industry

standard developed by the digital display working group(DDWG) for high-speed digital connection to digital displaysand has been adopted by industry-leading PC and consumerelectronics manufacturers. The TFP410 is compliant to theDVI Revision 1.0 specification.

2 Applications• DVD• Blu-ray• HD Projectors• DVI/HDMI Transmitter(2)

(2) HDMI video-only

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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TFP410SLDS145C –OCTOBER 2001–REVISED DECEMBER 2014 www.ti.com

Table of Contents7.5 Programming........................................................... 171 Features .................................................................. 17.6 Register Maps ........................................................ 182 Applications ........................................................... 1

8 Application and Implementation ........................ 253 Description ............................................................. 18.1 Application Information............................................ 254 Revision History..................................................... 28.2 Typical Application ................................................. 255 Pin Configuration and Functions ......................... 3

9 Power Supply Recommendations ...................... 286 Specifications......................................................... 69.1 DVDD...................................................................... 286.1 Absolute Maximum Ratings ...................................... 69.2 TVDD ...................................................................... 286.2 ESD Ratings ............................................................ 69.3 PVDD ...................................................................... 286.3 Recommended Operating Conditions....................... 6

10 Layout................................................................... 296.4 Thermal Information .................................................. 610.1 Layout Guidelines ................................................. 296.5 Electrical Characteristics........................................... 710.2 Layout Example .................................................... 306.6 Timing Requirements ................................................ 710.3 TI PowerPAD 64-Pin HTQFP Package................. 336.7 Typical Characteristics .............................................. 9

11 Device and Documentation Support ................. 347 Detailed Description ............................................ 1011.1 Trademarks ........................................................... 347.1 Overview ................................................................. 1011.2 Electrostatic Discharge Caution............................ 347.2 Functional Block Diagram ....................................... 1111.3 Glossary ................................................................ 347.3 Feature Description................................................. 11

12 Mechanical, Packaging, and Orderable7.4 Device Functional Modes........................................ 12Information ........................................................... 34

4 Revision History

Changes from Revision B (May 2011) to Revision C Page

• Added ESD Ratings table, Thermal Information table, Typical Characteristics section, Feature Description section,Device Functional Modes, Application and Implementation section, Power Supply Recommendations section,Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Informationsection. .................................................................................................................................................................................. 1

2 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated

Product Folder Links: TFP410


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60

62

23

21

19

DATA0 PVDD63 18

PGNDDGND 64 17

TFADJDATA1

DATA2 TGND61 20

TXC-DATA3

DATA4 TVC+59 22

DATA5 TVDD58

TX0-57 24IDCK+

TX0+56 25IDCK-

TGND55 26DATA6

TX1-DATA7 54 27

DATA8 TX1+53 28

DATA9 TVDD52 29

DATA10 TX2-51 30

DATA11 TX2+50 31

NC TGND49 32

DV

DD

DG

ND

1

48

DE

DA

TA

12

2

47

VR

EF

DA

TA

13

3

46

HS

YN

CD

AT

A14

4

45

DA

TA

15V

SY

NC

5

44

CT

L3/A

3/D

K3

DA

TA

16

6

43

DG

ND

DV

DD

16

33

BS

EL/

SC

LR

ES

ER

VE

D

15

34

DS

EL/

SD

AD

KE

N

14

35

ISE

L/R

ST

DA

TA

23

13

36

DV

DD

DA

TA

22

12

37

MS

EN

/PO

1D

AT

A21

11

38

PD

DA

TA

20

10

39

CT

L2/A

2/D

K2

DA

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17

7

42

CT

L1/A

1/D

K1

DA

TA

18

8

41

ED

GE

/HT

PLG

DA

TA

19

9

40

TFP410www.ti.com SLDS145C –OCTOBER 2001–REVISED DECEMBER 2014

5 Pin Configuration and Functions

PAP Package64 Pin HTQFP

Top View

Pin FunctionsPIN

TYPE DESCRIPTIONNAME NO.

INPUTThe upper 12 bits of the 24-bit pixel busIn 24-bit, single-edge input mode (BSEL = high), this bus inputs the top half of the 24-bit pixel bus. In12-bit, dual-edge input mode (BSEL = low), these bits are not used to input pixel data. In this mode,DATA[23:12] 36−47 Ithe state of DATA[23:16] is input to the I2C register CFG. This allows 8 bits of user configuration datato be read by the graphics controller through the I2C interface (see the Register Maps section).Note: All unused data inputs should be tied to GND or VDD.The lower 12 bits of the 24-bit pixel bus/12-bit pixel bus input

50−55, In 24-bit, single-edge input mode (BSEL = high), this bus inputs the bottom half of the 24-bit pixelDATA[11:0] I58−63 bus. In 12-bit, dual-edge input mode (BSEL = low), this bus inputs 1/2 a pixel (12 bits) at every latchedge (both rising and falling) of the clock.

Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 3



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Pin Functions (continued)PIN


Differential clock input. The TFP410 supports both single-ended and fully differential clock inputmodes. In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the

IDCK– 56 single-ended clock source and the IDCK− input (pin 56) should be tied to GND. In the differentialI clock input mode, the TFP410 uses the crossover point between the IDCK+ and IDCK– signals asIDCK+ 57the timing reference for latching incoming data DATA[23:0], DE, HSYNC, and VSYNC. Thedifferential clock input mode is only available in the low signal swing mode.Data enable. As defined in DVI 1.0 specification, the DE signal allows the transmitter to encode pixeldata or control data on any given input clock cycle. During active video (DE = high), the transmitterDE 2 I encodes pixel data, DATA[23:0]. During the blanking interval (DE = low), the transmitter encodesHSYNC, VSYNC and CTL[3:1].

HSYNC 4 I Horizontal sync inputVSYNC 5 I Vertical sync input

The operation of these three multifunction inputs depends on the settings of the ISEL (pin 13) andDKEN (pin 35) inputs. All three inputs support 3.3-V CMOS signal levels and contain weak pulldownresistors so that if left unconnected they default to all low.When the I2C bus is disabled (ISEL = low) and the de-skew mode is disabled (DKEN = low), thesethree inputs become the control inputs, CTL[3:1], which can be used to send additional information

CTL3/A3/DK3 6 across the DVI link during the blanking interval (DE = low). The CTL3 input is reserved for HDCPCTL2/A2/DK2 7 I compliant DVI TXs (TFP510) and the CTL[2:1] inputs are reserved for future use.CTL1/A1/DK1 8

When the I2C bus is disabled (ISEL = low) and the de-skew mode is enabled (DKEN = high), thesethree inputs become the de-skew inputs DK[3:1], used to adjust the setup and hold times of the pixeldata inputs DATA[23:0], relative to the clock input IDCK±.When the I2C bus is enabled (ISEL = high), these three inputs become the 3 LSBs of the I2C slaveaddress, A[3:1].

CONFIGURATION/PROGRAMMINGMonitor sense/programmable output 1. The operation of this pin depends on whether the I2Cinterface is enabled or disabled. This pin has an open-drain output and is only 3.3-V tolerant. Anexternal 5-kΩ pullup resistor connected to VDD is required on this pin.When I2C is disabled (ISEL = low), a low level indicates a powered on receiver is detected at theMSEN/PO1 11 O differential outputs. A high level indicates a powered on receiver is not detected. This function is onlyvalid in dc-coupled systems.When I2C is enabled (ISEL = high), this output is programmable through the I2C interface (see theI2C register descriptions section).I2C interface select/I2C RESET (active low, asynchronous)If ISEL is high, then the I2C interface is active. Default values for the I2C registers can be found inthe Register Maps section.

ISEL/RST 13 I If ISEL is low, then I2C is disabled and the chip configuration is specified by the configuration pins(BSEL, DSEL, EDGE, VREF) and state pins (PD, DKEN).If ISEL is brought low and then back high, the I2C state machine is reset. The register values arechanged to their default values and are not preserved from before the reset.Input bus select/I2C clock input. The operation of this pin depends on whether the I2C interface isenabled or disabled. This pin is only 3.3-V tolerant.When I2C is disabled (ISEL = low), a high level selects 24-bit input, single-edge input mode. A low

BSEL/SCL 15 I level selects 12-bit input, dual-edge input mode.When I2C is enabled (ISEL = high), this pin functions as the I2C clock input (see the Register Mapssection). In this configuration, this pin has an open-drain output that requires an external 5-kΩ pullupresistor connected to VDD.DSEL/I2C data. The operation of this pin depends on whether the I2C interface is enabled ordisabled. This pin is only 3.3-V tolerant.When I2C is disabled (ISEL = low), this pin is used with BSEL and VREF to select the single-ended or

DSEL/SDA 14 I/O differential input clock mode (see Table 1).When I2C is enabled (ISEL = high), this pin functions as the I2C bidirectional data line. In thisconfiguration, this pin has an open-drain output that requires an external 5-kΩ pullup resistorconnected to VDD.




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Pin Functions (continued)PIN


Edge select/hot plug input. The operation of this pin depends on whether the I2C interface is enabledor disabled. This input is 3.3-V tolerant only.When I2C is disabled (ISEL = low), a high level selects the primary latch to occur on the rising edgeof the input clock IDCK+. A low level selects the primary latch to occur on the falling edge of theEDGE/HTPLG 9 I input clock IDCK+. This is the case for both single-ended and differential input clock modes.When I2C is enabled (ISEL = high), this pin is used to monitor the hot plug detect signal. When usedfor hot-plug detection, this pin requires a series1-kΩ resistor.Data de-skew enable. The de-skew function can be enabled either through I2C or by this pin whenI2C is disabled. When de-skew is enabled, the input clock to data setup/hold time can be adjusted indiscrete trim increments. The amount of trim per increment is defined by t(STEP).When I2C is disabled (ISEL = low), a high level enables de-skew with the trim increment determinedDKEN 35 I by pins DK[3:1] (see the Data De-skew Feature section). A low level disables de-skew and thedefault trim setting is used.When I2C is enabled (ISEL = high), the value of DKEN and the trim increment are selected throughI2C. In this configuration, the DKEN pin should be tied to either GND or VDD to avoid a floating input.Input reference voltage. Selects the swing range of the digital data inputs (DATA[23:0], DE, HSYNC,VSYNC, and IDCK±).For high-swing 3.3-V input signal levels, VREF should be tied to VDD.

VREF 3 IFor low-swing input signal levels, VREF should be set to half of the maximum input voltage level. SeeRecommended Operating Conditions for the allowable range for VREF.The desired VREF voltage level is typically derived using a simple voltage-divider circuit.Power down (active low). In the powerdown state, only the digital I/O buffers and I2C interface remainactive.When I2C is disabled (ISEL = low), a high level selects the normal operating mode. A low levelselects the powerdown mode.

PD 10 IWhen I2C is enabled (ISEL = high), the power-down state is selected through I2C. In thisconfiguration, the PD pin should be tied to GND.Note: The default register value for PD is low, so the device is in powerdown mode when I2C is firstenabled or after an I2C RESET.

RESERVEDRESERVED 34 I This pin is reserved and must be tied to GND for normal operation.DVI DIFFERENTIAL SIGNAL OUTPUT PINSTX0+ 25 Channel 0 DVI differential output pair. TX0± transmits the 8-bit blue pixel data during active videoO andHSYNC and VSYNC during the blanking interval.TX0− 24TX1+ 28 Channel 1 DVI differential output pair. TX1± transmits the 8-bit green pixel data during active videoO and CTL[1] during the blanking interval.TX1− 27TX2+ 31 Channel 2 DVI differential output pair. TX2± transmits the 8-bit red pixel data during active video andO CTL[3:2] during the blanking interval.TX2− 30TXC+ 22 O DVI differential output clock.TXC− 21

Full-scale adjust. This pin controls the amplitude of the DVI output voltage swing, determined by theTFADJ 19 I value of the pullup resistor RTFADJ connected to TVDD.POWER AND GROUND PINSDVDD 1, 12, 33 Power Digital power supply. Must be set to 3.3 V nominal.PVDD 18 Power PLL power supply. Must be set to 3.3 V nominal.TVDD 23, 29 Power Transmitter differential output driver power supply. Must be set to 3.3 V nominal.

16, 48,DGND Ground Digital ground64PGND 17 Ground PLL ground

20, 26,TGND Ground Transmitter differential output driver ground32NC 49 NC No connection required. If connected, tie high.




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6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITDVDD, PVDD, Supply voltage range –0.5 4 VTVDD

Input voltage, logic/analog signals –0.5 4 VRT External DVI single-ended termination resistance 0 to open circuit Ω

External TFADJ resistance, RTFADJ 300 to open circuit ΩCase temperature for 10 seconds 260 °CJEDEC latch-up (EIA/JESD78) 100 mA

Tstg Storage temperature 260 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD RatingsVALUE UNIT

Human body model (HBM), per DVI pins ±4000V(ESD) Electrostatic discharge VANSI/ESDA/JEDEC JS-001 (1)

All other pins ±2000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITVDD Supply voltage (DVDD, PVDD, TVDD) 3.0 3.3 3.6 V

Low-swing mode 0.55 VDDQ/2 (1) 0.9 VVREF Input reference voltage

High-swing mode DVDD VAVDD DVI termination supply voltage (2) DVI receiver 3.14 3.3 3.46 VRT DVI Single-ended termination resistance (3) DVI receiver 45 50 55 ΩR(TFADJ) TFADJ resistor for DVI-compliant V(SWING) range 400 mV = V(SWING) = 600 mV 505 510 515 ΩTA Operating free-air temperature range 0 25 70 °C

(1) VDDQ defines the maximum low-level input voltage, it is not an actual input voltage.(2) AVDD is the termination supply voltage of the DVI link.(3) RT is the single-ended termination resistance at the receiver end of the DVI link.

6.4 Thermal InformationTFP410

THERMAL METRIC (1) PAP UNIT64 PINS

RθJA Junction-to-ambient thermal resistance 26.6RθJC(top) Junction-to-case (top) thermal resistance 14.1RθJB Junction-to-board thermal resistance 11.3

°C/WψJT Junction-to-top characterization parameter 0.4ψJB Junction-to-board characterization parameter 11.2RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).




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6.5 Electrical Characteristicsover recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITDC SPECIFICATIONS

VREF = DVDD 0.7 VDDVIH High-level input voltage (CMOS input) V0.5 V ≤ V ≤ 0.95 V VREF + 0.2VREF = DVDD 0.3VDDVIL Low-level input voltage (CMOS input) V0.5 V ≤V ≤ 0.95 V VREF – 0.2

High-level digital output voltage (open-drainVOH VDD = 3 V, IOH = 20 μA 2.4 Voutput)Low-level digital output voltage (open-drainVOL VDD = 3.6 V, IOL = 4 mA 0.4 Voutput)

IIH High-level input current VI = 3.6 V ±25 µAIIL Low-level input current VI = 0 ±25 µAVH DVI single-ended high-level output voltage AVDD – 0.01 AVDD + 0.01 V

AVDD = 3.3 V ± 5%,VL DVI single-ended low-level output voltage AVDD – 0.6 AVDD – 0.4 VRT

(1) = 50 Ω ± 10%,VSWING DVI single-ended output swing voltage 400 600 mVP-PRTFADJ = 510 Ω ± 1%VOFF DVI single-ended standby/off output voltage AVDD – 0.01 AVDD + 0.01 VIPD Power-down current (2) 200 500 µAIIDD Normal power supply current Worst-case pattern (3) 200 250 mAAC SPECIFICATIONSf(IDCK) IDCK frequency 25 165 MHztr DVI output rise time (20-80%) (4) 75 240 pstf DVI output fall time (20-80%) (4) 75 240 ps

f(IDCK) = 165 MHzDVI output intra-pair + to − differential skew (5),tsk(D) 50 pssee Figure 4tojit DVI output clock jitter, max. (6) 150 pst(STEP) De-skew trim increment DKEN = 1 350 ps

(1) RT is the single-ended termination resistance at the receiver end of the DVI link(2) Assumes all inputs to the transmitter are not toggling.(3) Black and white checkerboard pattern, each checker is one pixel wide.(4) Rise and fall times are measured as the time between 20% and 80% of signal amplitude.(5) Measured differentially at the 50% crossing point using the IDCK+ input clock as a trigger.(6) Relative to input clock (IDCK).

6.6 Timing RequirementsMIN NOM MAX UNIT

t(pixel) Pixel time period (1) 6.06 40 ns

t(IDCK) IDCK duty cycle 30% 70%

t(ijit) IDCK clock jitter tolerance 2 ns

tsk(CC) DVI output inter-pair or channel-to-channel skew (2), see Figure 2 f(IDCK) = 165 MHz 1.2 ns

Data, DE, VSYNC, HSYNC setup time to IDCK+ falling edge, seetsu(IDF) 1.2 nsFigure 2 Single edge (BSEL=1, DSEL=0,DKEN=0, EDGE=0)Data, DE, VSYNC, HSYNC hold time to IDCK+ falling edge, seeth(IDF) 1.3 nsFigure 2

Data, DE, VSYNC, HSYNC setup time to IDCK+ rising edge, seetsu(IDR) 1.2 nsFigure 2 Single edge (BSEL=1, DSEL=0,DKEN=0, EDGE=1)Data, DE, VSYNC, HSYNC hold time to IDCK+ rising edge, seeth(IDR) 1.3 nsFigure 2

Dual edge(BSEL=0,Data, DE, VSYNC, HSYNC setup time to IDCK+ falling/risingtsu(ID) 0.9 nsedge, see Figure 3 DSEL=1, DKEN=0)

Dual edge (BSEL=0,Data, DE, VSYNC, HSYNC hold time to IDCK+ falling/rising edge,th(ID) 1 nssee Figure 3 DSEL=1, DKEN=0)

(1) t(pixel) is the pixel time defined as the period of the TXC output clock. The period of IDCK is equal to t(pixel).(2) Measured differentially at the 50% crossing point using the IDCK+ input clock as a trigger.




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tsk(CC)

50%

50%

TXN

TXM

tsk(D)

50%

TX+

TX−

tsu(ID) th(ID)

VIH

VIL

IDCK+

DATA[23:0], DE,

HSYNC, VSYNC

th(ID)

tsu(ID)

th(IDF)

tsu(IDF) th(IDR)

tsu(IDR)

VIH

VIL

IDCK+

DATA[23:0], DE,

HSYNC, VSYNC

IDCK−

tr tf

80% VOD

20% VOD

DVI

Outputs


Figure 1. Rise and Fall Time for DVI Outputs

Figure 2. Control and Single-Edge-Data Setup/Hold Time to IDCK±

Figure 3. Dual Edge Data Setup/Hold Times to IDCK+

Figure 4. Analog Output Intra-Pair ± Differential Skew

Figure 5. Analog Output Channel-to-Channel Skew




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RTFDAJ(ohm)

Vswing(mV)

0

100

200

300

400

500

600

700

800

900


6.7 Typical Characteristics

Figure 6. RTFDAJ vs Vswing




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7 Detailed Description

7.1 OverviewThe TFP410 is a DVI-compliant digital transmitter that is used in digital host monitor systems to T.M.D.S. encodeand serialize RGB pixel data streams. TFP410 supports resolutions from VGA to WUXGA (and 1080p) and canbe controlled in two ways:1. Configuration and state pins2. The programmable I2C serial interface (see Table 1)

The host in a digital display system, usually a PC or consumer electronics device, contains a DVI-compatibletransmitter such as the TI TFP410 that receives 24-bit pixel data along with appropriate control signals. TheTFP410 encodes the signals into a high speed, low voltage, differential serial bit stream optimized fortransmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor,requires a DVI compatible receiver like the TI TFP401 to decode the serial bit stream back to the same 24-bitpixel data and control signals that originated at the host. This decoded data can then be applied directly to theflat panel drive circuitry to produce an image on the display. Because the host and display can be separated bydistances up to 5 meters or more, serial transmission of the pixel data is preferred (see the T.M.D.S. Pixel Dataand Control Signal Encoding section, Universal Graphics Controller Interface Voltage Signal Levels section, andUniversal Graphics Controller Interface Clock Inputs section).

The TFP410 integrates a high-speed digital interface, a T.M.D.S. encoder, and three differential T.M.D.S. drivers.Data is driven to the TFP410 encoder across 12 or 24 data lines, along with differential clock pair and syncsignals. The flexibility of the TFP410 allows for multiple clock and data formats that enhance systemperformance.

The TFP410 also has enhanced PLL noise immunity, an enhancement accomplished with on-chip regulators andbypass capacitors.

The TFP410 is versatile and highly programmable to provide maximum flexibility for the user. An I2C hostinterface is provided to allow enhanced configurations in addition to power-on default settings programmed bypin-strapping resistors.

The TFP410 offers monitor detection through receiver detection, or hot-plug detection when I2C is enabled. Themonitor detection feature allows the user enhanced flexibility when attaching to digital displays or receivers (seethe Hot Plug/Unplug (Auto Connect/Disconnect Detection) section and the Register Maps section).

The TFP410 has a data de-skew feature allowing the users to de-skew the input data with respect to the IDCK±(see the Data De-skew Feature section).




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12/24 Bit

I/F

Data

Format

Universal Input T.M.D.S. Transmitter

Serializer

Serializer

Serializer

Control

I2C Slave I/F

For DDC1.8-V Regulators

With Bypass

Capacitors

PLL

TX2±

TX1±

TX0±

TXC±

TFADJ

IDCK±

DATA[23:0]

DE

VSYNC

HSYNC

EDGE/HTPLG

MSEN

PD

ISEL/RST

BSEL/SCL

DSEL/SDA

VREF

Encoder

Encoder

Encoder

CTL/A/DK[3:1]

DKEN


7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 T.M.D.S. Pixel Data and Control Signal EncodingFor transition minimized differential signaling (T.M.D.S.), only one of two possible T.M.D.S. characters for a givenpixel is transmitted at a given time. The transmitter keeps a running count of the number of ones and zerospreviously sent and transmits the character that minimizes the number of transitions and approximates a dcbalance of the transmission line. Three T.M.D.S. channels are used to transmit RGB pixel data during the activevideo interval (DE = High). These same three channels are also used to transmit HSYNC, VSYNC, and threeuser definable control signals, CTL[3:1], during the inactive display or blanking interval (DE = Low). The followingtable maps the transmitted output data to the appropriate T.M.D.S. output channel in a DVI-compliant system.

INPUT PINS TRANSMITTED PIXEL DATAT.M.D.S. OUTPUT CHANNEL(VALID FOR DE = High) ACTIVE DISPLAY (DE = High)DATA[23:16] Channel 2 (TX2 ±) Red[7:0]DATA[15:8] Channel 1 (TX1 ±) Green[7:0]DATA[7:0] Channel 0 (TX0 ±) Blue[7:0]

INPUT PINS TRANSMITTED CONTROL DATAT.M.D.S. OUTPUT CHANNEL(VALID FOR DE = Low) BLANKING INTERVAL (DE = Low)CTL3, CTL2 (1) Channel 2 (TX2 ±) CTL[3:2]CTL1 (1) Channel 1 (TX1 ±) CTL[1]HSYNC, VSYNC Channel 0 (TX0 ±) HSYNC, VSYNC

(1) The TFP410 encodes and transfers the CTL[3:1] inputs during the vertical blanking interval. The CTL3 input is reserved for HDCPcompliant DVI TXs and the CTL[2:1] inputs are reserved for future use. When DE = high, CTL and SYNC pins must be held constant.




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7.3.2 Universal Graphics Controller Interface Voltage Signal LevelsThe universal graphics controller interface can operate in the following two distinct voltage modes:• The high-swing mode where standard 3.3-V CMOS signaling levels are used.• The low-swing mode where adjustable 1.1-V to 1.8-V signaling levels are used.

To select the high-swing mode, the VREF input pin must be tied to the 3.3-V power supply.

To select the low-swing mode, the VREF must be 0.55 to 0.95 V.

In the low-swing mode, VREF is used to set the midpoint of the adjustable signaling levels. The allowable range ofvalues for VREF is from 0.55 V to 0.9 V. The typical approach is to provide this from off chip by using a simplevoltage-divider circuit. The minimum allowable input signal swing in the low-swing mode is VREF ±0.2 V. In low-swing mode, the VREF input is common to all differential input receivers.

7.3.3 Universal Graphics Controller Interface Clock InputsThe universal graphics controller interface of the TFP410 supports both fully differential and single-ended clockinput modes. In the differential clock input mode, the universal graphics controller interface uses the crossoverpoint between the IDCK+ and IDCK− signals as the timing reference for latching incoming data (DATA[23:0], DE,HSYNC, and VSYNC). Differential clock inputs provide greater common-mode noise rejection. The differentialclock input mode is only available in the low-swing mode. In the single-ended clock input mode, the IDCK+ input(Pin 57) should be connected to the single-ended clock source and the IDCK− input (Pin 56) should be tied toGND.

The universal graphics controller interface of the TFP410 provides selectable 12-bit dual-edge, and 24-bit single-edge, input clocking modes. In the 12-bit dual-edge, the 12-bit data is latched on each edge of the input clock. Inthe 24-bit single-edge mode, the 24-bit data is latched on the rising edge of the input clock when EDGE = 1 andthe falling edge of the input clock when EDGE = 0.

DKEN and DK[3:1] allow the user to compensate the skew between IDCK± and the pixel data and controlsignals. See Table 10 for details.

7.4 Device Functional Modes

7.4.1 Universal Graphics Controller Interface ModesTable 1 is a tabular representation of the different modes for the universal graphics controller interface. The 12-bit mode is selected when BSEL=0 and the 24-bit mode when BSEL=1. The 12-bit mode uses dual-edgeclocking and the 24-bit mode uses single-edge clocking. The EDGE input is used to control the latching edge in24-bit mode, or the primary latching edge in 12-bit mode. When EDGE=1, the data input is latched on the risingedge of the input clock; and when EDGE=0, the data input is latched on the falling edge of the input clock. A fullydifferential input clock is available only in the low-swing mode. Single-ended clocking is not recommended in thelow-swing mode as this decreases common-mode noise rejection.

Note that BSEL, DSEL, and EDGE are determined by register CTL_1_MODE when I2C is enabled (ISEL=1) andby input pins when I2C is disabled (ISEL=0).

Table 1. Universal Graphics Controller Interface Options (Tabular Representation)VREF BSEL EDGE DSEL BUS WIDTH LATCH MODE CLOCK EDGE CLOCK MODE

0.55 V − 0.9 V 0 0 0 12-bit Dual-edge Falling Differential (1) (2)

0.55 V − 0.9 V 0 0 1 12-bit Dual-edge Falling Single-ended0.55 V – 0.9 V 0 1 0 12-bit Dual-edge Rising Differential (1) (2)

0.55 V − 0.9 V 0 1 1 12-bit Dual-edge Rising Single-ended0.55 V – 0.9 V 1 0 0 24-bit Single-edge Falling Single-ended0.55 V – 0.9 V 1 0 1 24-bit Single-edge Falling Differential (1) (3)

0.55 V – 0.9 V 1 1 0 24-bit Single-edge Rising Single-ended0.55 V – 0.9 V 1 1 1 24-bit Single-edge Rising Differential (1) (3)

(1) The differential clock input mode is only available in the low signal swing mode (that is, VREF ≤ 0.9 V).(2) The TFP410 does not support a 12-bit dual-clock, single-edge input clocking mode.(3) The TFP410 does not support a 24-bit single-clock, dual-edge input clocking mode.




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P0 P1 PN-1 PN

DSEL=0

EDGE=0

DSEL=0

EDGE=1

DSEL=1

EDGE=0

DSEL=1

EDGE=1

Single-Ended

Clock Input

Mode

Differential

Clock Input

Mode (Low

Swing Only)

DE

D[23:0]

IDCK+

IDCK+

{(IDCK+) − (IDCK−)}


First Latch Edge

24-Bit, Single-Edge Input Mode (BSEL = 1)

P L0 P H0 P L1 P H1 P LN−1 P LN P HN PN+1L

DSEL=1

EDGE=0

DSEL=1

EDGE=1

DSEL=0

EDGE=0

DSEL=0

EDGE=1

Single-Ended

Clock Input

Mode

Differential

Clock Input

Mode (Low

Swing Only)

DE

D[11:0]

IDCK+

IDCK+



First Latch Edge

12-Bit, Dual-Edge Input Mode (BSEL = 0)

L = Low Half Pixel

H = High Half Pixel


Device Functional Modes (continued)Table 1. Universal Graphics Controller Interface Options (Tabular Representation) (continued)

VREF BSEL EDGE DSEL BUS WIDTH LATCH MODE CLOCK EDGE CLOCK MODEDVDD 0 0 X 12-bit Dual-edge Falling Single-ended (4)

DVDD 0 1 X 12-bit Dual-edge Rising Single-ended (4)

DVDD 1 0 X 24-bit Single-edge Falling Single-ended (4)

DVDD 1 1 X 24-bit Single-edge Rising Single-ended (4)

(4) In the high-swing mode (VREF = DVDD), DSEL is a don’t care; therefore, the device is always in the single-ended latch mode.

Figure 7. Universal Graphics Controller Interface Options for 12-Bit Mode (Graphical Representation)

Figure 8. Universal Graphics Controller Interface Options for 24-Bit Mode (Graphical Representation)




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Table 2. 12-Bit Mode Data MappingP0 P1 P2

PIN NAME P0L P0H P1L P1H P2L P2HLOW HIGH LOW HIGH LOW HIGH

D11 G0[3] R0[7] G1[3] R1[7] G2[3] R2[7]D10 G0[2] R0[6] G1[2] R1[6] G2[2] R2[6]D9 G0[1] R0[5] G1[1] R1[5] G2[1] R2[5]D8 G0[0] R0[4] G1[0] R1[4] G2[0] R2[4]D7 B0[7] R0[3] B1[7] R1[3] B2[7] R2[3]D6 B0[6] R0[2] B1[6] R1[2] B2[6] R2[2]D5 B0[5] R0[1] B1[5] R1[1] B2[5] R2[1]D4 B0[4] R0[0] B1[4] R1[0] B2[4] R2[0]D3 B0[3] G0[7] B1[3] G1[7] B2[3] G2[7]D2 B0[2] G0[6] B1[2] G1[6] B2[2] G2[6]D1 B0[1] G0[5] B1[1] G1[5] B2[1] G2[5]D0 B0[0] G0[4] B1[0] G1[4] B2[0] G2[4]

Table 3. 24-Bit Mode Data MappingPIN NAME P0 P1 P2 PIN NAME P0 P1 P2

D23 R0[7] R1[7] R2[7] D11 G0[3] G1[3] G2[3]D22 R0[6] R1[6] R2[6] D10 G0[2] G1[2] G2[2]D21 R0[5] R1[5] R2[5] D9 G0[1] G1[1] G2[1]D20 R0[4] R1[4] R2[4] D8 G0[0] G1[0] G2[0]D19 R0[3] R1[3] R2[3] D7 B0[7] B1[7] B2[7]D18 R0[2] R1[2] R2[2] D6 B0[6] B1[6] B2[6]D17 R0[1] R1[1] R2[1] D5 B0[5] B1[5] B2[5]D16 R0[0] R1[0] R2[0] D4 B0[4] B1[4] B2[4]D15 G0[7] G1[7] G2[7] D3 B0[3] B1[3] B2[3]D14 G0[6] G1[6] G2[6] D2 B0[2] B1[2] B2[2]D13 G0[5] G1[5] G2[5] D1 B0[1] B1[1] B2[1]D12 G0[4] G1[4] G2[4] D0 B0[0] B1[0] B2[0]

7.4.2 Data De-skew FeatureThe de-skew feature allows adjustment of the input setup/hold time. Specifically, the input data DATA[23:0] canbe latched slightly before or after the latching edge of the clock IDCK± depending on the amount of de-skewdesired. When de-skew enable (DKEN) is enabled, the amount of de-skew is programmable by setting the threebits DK[3:1]. When disabled, a default de-skew setting is used. To allow maximum flexibility and ease of use,DKEN and DK[3:1] are accessed directly through configuration pins when I2C is disabled, or through registers ofthe same name when I2C is enabled. When using I2C mode, the DKEN pin should be tied to ground to avoid afloating input.




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−t(CD)

000

−4 × t(STEP)

100

0

Default Falling

111

3 × t(STEP)

000

−4 × t(STEP)

100

0

Default Rising

111

3 × t(STEP)

DATA[23:0]

IDCK±

DK[3:1]

t(CD)

t(CD) −t(CD) t(CD)


The input setup/hold time can be varied with respect to the input clock by an amount t(CD) given by the formula inEquation 1.

t(CD) = (DK[3:1] – 4) × t(STEP)

where• t(STEP) is the adjustment increment amount• DK[3:1] is a number from 0 to 7 represented as a 3-bit binary number• t(CD) is the cumulative de-skew amount (1)

(DK[3:1]-4) is simply a multiplier in the range {-4,-3,-2,-1, 0, 1, 2, 3} for t(STEP). Therefore, data can be latched inincrements from 4 times the value of t(STEP) before the latching edge of the clock to 3 times the value of t(STEP)after the latching edge. Note that the input clock is not changed, only the time when data is latched with respectto the clock.

Figure 9. A Graphical Representation of the De-Skew Function

7.4.3 Hot Plug/Unplug (Auto Connect/Disconnect Detection)TFP410 supports hot plug/unplug (auto connect/disconnect detection) for the DVI link. The receiver sense input(RSEN) bit indicates if a DVI receiver is connected to TXC+ and TXC–. The HTPLG bit reflects the current stateof the HTPLG pin connected to the monitor via the DVI connector. When I2C is disabled (ISEL=0), the RSENvalue is available on the MSEN pin. When I2C is enabled, the connection status of the DVI link and HTPLGsense pins are provided by the CTL_2_MODE register. The MSEL bits of the CTL_2_MODE register can beused to program the MSEN to output the HTPLG value, the RSEN value, an interrupt, or be disabled.

The source of the interrupt event is selected by TSEL in the CTL_2_MODE register. An interrupt is generated bya change in status of the selected signal. The interrupt status is indicated in the MDI bit of CTL_2_MODE andcan be output via the MSEN pin. The interrupt continues to be asserted until a 1 is written to the MDI bit,resetting the bit back to 0. Writing 0 to the MDI bit has no effect.

7.4.4 Device Configuration and I2C RESET DescriptionThe TFP410 device configuration can be programmed by several different methods to allow maximum flexibilityfor the user’s application. Device configuration is controlled depending on the state of the ISEL/RST pin,configuration pins (BSEL, DSEL, EDGE, VREF) and state pins (PD, DKEN). I2C bus select and I2C RESET (activelow) are shared functions on the ISEL/RST pin, which operates asynchronously.

Holding ISEL/RST low causes the device configuration to be set by the configuration pins (BSEL, DSEL, EDGE,and VREF) and state pins (PD, DKEN). The I2C bus is disabled.

Holding ISEL/RST high causes the chip configuration to be set based on the configuration bits (BSEL, DSEL,EDGE) and state bits (PD, DKEN) in the I2C registers. The I2C bus is enabled.

Momentarily bringing ISEL/RST low and then back high while the device is operating in normal or power-downmode will RESET the I2C registers to their default values. The device configuration will be changed to the defaultpower-up state with I2C enabled. After power up, the device must be reset. It is suggested that this pin be tied tothe system reset signal, which is low during power up and is then asserted high after all the power supplies arefully functional.




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Actual Display Area

DE_CNT

DE_LIN

Full Vertical FrameDE_TOP

V_RES

H_RES

DE_DLY


7.4.5 DE GeneratorThe TFP410 contains a DE generator that can be used to generate an internal DE signal when the original datasource does not provide one. There are several I2C programmable values that control the DE generator (seeFigure 10). DE_GEN in the DE_CTL register enables this function. When enabled, the DE pin is ignored.

DE_TOP and DE_LIN are line counts used to control the number of lines after VSYNC goes active that DE isenabled, and the total number of lines that DE remains active, respectively. The polarity of VSYNC must be setby VS_POL in the DE_CTL register.

DE_DLY and DE_CNT are pixel counts used to control the number of pixels after HSYNC goes active that DE isenabled, and the total number of pixels that DE remains active, respectively. The polarity of HSYNC must be setby HS_POL in the DE_CTL register.

The TFP410 also counts the total number of HSYNC pulses between VSYNC pulses, and the total number ofpixels between HSYNC pulses. These values, the total vertical and horizontal resolutions, are available inV_RES and H_RES, respectively. These values are available at all times, whether or not the DE generator isenabled.

Figure 10. DE Generator Register Functions




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SCL

1 2 3 4 5 6 7 8 9

SDA

1 2 3 4 5 6 7 8 9 2 3 4 5 6 71

Slave Address Sub-Address Data Stop

8 9

Start Condition (S) Stop Condition (P)

SDA

SCL


7.5 Programming

7.5.1 I2C interfaceThe I2C interface is used to access the internal TFP410 registers. This two-pin interface consists of the SCLclock line and the SDA serial data line. The basic I2C access cycles are shown in Figure 11 and Figure 12.

Figure 11. I2C Start and Stop Conditions

The basic access write cycle consists of the following:1. A start condition2. A slave address cycle3. A sub-address cycle4. Any number of data cycles5. A stop condition

The basic access read cycle consists of the following:1. A start condition2. A slave write address cycle3. A sub-address cycle4. A restart condition5. A slave read address cycle6. Any number of data cycles7. A stop condition

The start and stop conditions are shown in Figure 11. The high to low transition of SDA while SCL is high definesthe start condition. The low to high transition of SDA while SCL is high defines the stop condition. Each cycle,data or address, consists of 8 bits of serial data followed by one acknowledge bit generated by the receivingdevice. Thus, each data/address cycle contains 9 bits as shown in Figure 12.

Figure 12. I2C Access Cycles

Following a start condition, each I2C device decodes the slave address. The TFP410 responds with anacknowledge by pulling the SDA line low during the ninth clock cycle if it decodes the address as its address.During subsequent sub-address and data cycles, the TFP410 responds with acknowledge as shown inFigure 13. The sub-address is auto-incremented after each data cycle.




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S Slave Address W A Sub-Address A Sr Slave Address R A Data A Data /A P

Where:

From Master A Acknowledge

From Slave S Start condition

/A Not acknowledge (SDA high) P Stop ConditionR Read Condition = 1 Sr Restart ConditionW Write Condition = 0

S Slave Address W A Sub-Address A Data A Data A P

Where:

From Master A Acknowledge

From Slave S Start condition

P Stop Condition


Programming (continued)The transmitting device must not drive the SDA signal during the acknowledge cycle so that the receiving devicemay drive the SDA signal low. The master indicates a not acknowledge condition (A) by keeping the SDA signalhigh just before it asserts the stop condition (P). This sequence terminates a read cycle as shown in Figure 14.

The slave address consists of 7 bits of address along with 1 bit of read/write information (read = 1, write = 0) asshown below in Figure 12 and Figure 13. For the TFP410, the selectable slave addresses (including the R/W bit)using A[3:1] are 0x70, 0x72, 0x74, 0x76, 0x78, 0x7A, 0x7C, and 0x7E for write cycles and 0x71, 0x73, 0x75,0x77, 0x79, 0x7B, 0x7D, and 0x7F for read cycles.

Figure 13. I2C Write Cycle

Figure 14. I2C Read Cycle

7.6 Register MapsThe TFP410 is a standard I2C slave device. All the registers can be written and read through the I2C interface(unless otherwise specified). The TFP410 slave machine supports only byte read and write cycles. Page mode isnot supported. The 8-bit binary address of the I2C machine is 0111 A3A2A1X, where A[3:1] are pinprogrammable or set to 000 by default. The I2C base address of the TFP410 is dependent on A[3:1] (pins 6, 7and 8 respectively) as shown below.

WRITE ADDRESS READ ADDRESSA[3:1] (Hex) (Hex)000 70 71001 72 73010 74 75011 76 77100 78 79101 7A 7B110 7C 7D111 7E 7F

SUB-REGISTER RW BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0ADDRESS

VEN_ID R 00 VEN_ID[7:0]

R 01 VEN_ID[15:8]

DEV_ID R 02 DEV_ID[7:0]

R 03 DEV_ID[15:8]




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SUB-REGISTER RW BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0ADDRESS

REV_ID R 04 REV_ID[7:0]

RESERVED R 05-07 Reserved

CTL_1_MODE RW 08 RSVD TDIS VEN HEN DSEL BSEL EDGE PD

CTL_2_MODE RW 09 VLOW MSEL TSEL RSEN HTPLG MDI

CTL_3_MODE RW 0A DK DKEN CTL RSVD

CFG RW 0B CFG

RESERVED RW 0C-31 Reserved

DE_DLY RW 32 DE_DLY[7:0]

DE_CTL RW 33 RSVD DE_GEN VS_POL HS_POL RSVD DE_DLY[8]

DE_TOP RW 34 RSVD DE_DLY[6:0]

RESERVED RW 35 Reserved

DE_CNT RW 36 DE_CNT[7:0]

RW 37 Reserved DE_CNT[10:8]

DE_LIN RW 38 DE_LIN[7:0]

RW 39 Reserved DE_LIN[10:8]

H_RES R 3A H_RES[7:0]

R 3B Reserved H_RES[10:8]

V_RES R 3C V_RES[7:0]

R 3D Reserved V_RES[10:8]

RESERVED R 3E−FF

7.6.1 VEN_ID Register (Sub-Address = 01−00 ) [reset = 0x014C]

Figure 15. VEN_ID Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0VEN_ID[15:8] VEN_ID[7:0]

Table 4. VEN_ID Field DescriptionsBit Field Type Description

15:8 VEN_ID R These read-only registers contain the 16-bit Texas Instruments vendor ID. VEN_ID ishardwired to 0x014C.7:0 VEN_ID R

7.6.2 DEV_ID Register (Sub-Address = 03–02) [reset = 0x0410]

Figure 16. DEV_ID Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0DEV_ID[15:8] DEV_ID[7:0]

Table 5. DEV_ID Register Field DescriptionsBit Field Type Description

15:8 DEV_ID R These read-only registers contain the 16-bit device ID for the TFP410. DEV_ID ishardwired to 0x0410.7:0 DEV_ID R




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7.6.3 REV_ID Register (Sub-Address = 04) [reset = 0x00]

Figure 17. REV_ID Register

7 6 5 4 3 2 1 0REV_ID[7:0]

Table 6. REV_ID Register Field DescriptionsBit Field Type Description7:0 REV_ID R This read-only register contains the revision ID.

7.6.4 Reserved Register (Sub-Address = 07–05) [reset = 0x641400]

Figure 18. Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RESERVED[15:8] RESERVED[7:0]

Table 7. Reserved Field DescriptionsBit Field Type Description

15:8 RESERVED Read Only —7:0 RESERVED Read Only —

7.6.5 CTL_1_MODE (Sub-Address = 08) [reset = 0xFE]

Figure 19. CTL_1_MODE Register

7 6 5 4 3 2 1 0RSVD TDIS VEN HEN DSEL BSEL EDGE PD

Table 8. CTL_1_MODE Field DescriptionsBit Field Type Description7 RSVD R/W Reserved

This read/write register contains the T.M.D.S. disable mode6 TDIS R/W 0: T.M.D.S. circuitry enable state is determined by PD.

1: T.M.D.S. circuitry is disabled.This read/write register contains the vertical sync enable mode.

5 VEN R/W 0: VSYNC input is transmitted as a fixed low1: VSYNC input is transmitted in its original stateThis read/write register contains the horizontal sync enable mode.

4 HEN R/W 0: HSYNC input is transmitted as a fixed low1: HSYNC input is transmitted in its original stateThis read/write register is used in combination with BSEL and VREF to select the

3 DSEL R/W single-ended or differential input clock mode. In the high-swing mode, DSEL is adon’t care because IDCK is always single-ended.This read/write register contains the input bus select mode.

2 BSEL R/W 0: 12-bit operation with dual-edge clock1: 24-bit operation with single-edge clockThis read/write register contains the edge select mode.

1 EDGE R/W 0: Input data latches to the falling edge of IDCK+1: Input data latches to the rising edge of IDCK+This read/write register contains the power-down mode.

0 PD R/W 0: Power down (default after RESET)1: Normal operation




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7.6.6 CTL_2_MODE Register (Sub-Address = 09) [reset = 0x00]


7 6 5 4 3 2 1 0VLOW MSEL[3:1] TSEL RSEN HTPLG MDI

Table 9. CTL_2_MODE Field DescriptionsBit Field Type Description

This read only register indicates the VREF input level.7 VLOW R/W 0: This bit is a logic level (0) if the VREF analog input selects high-swing inputs

1: This bit is a logic level (1) if the VREF analog input selects low-swing inputsThis read/write register contains the source select of the monitor sense output pin.000: Disabled. MSEN output high

6:4 MSEL[3:1] R/W 001: Outputs the MDI bit (interrupt)010: Outputs the RSEN bit (receiver detect)011: Outputs the HTPLG bit (hot plug detect)This read/write register contains the interrupt generation source select.

3 TSEL R/W 0: Interrupt bit (MDI) is generated by monitoring RSEN1: Interrupt bit (MDI) is generated by monitoring HTPLGThis read only register contains the receiver sense input logic state, which is validonly for dc-coupled systems.

2 RSEN R/W 0: A powered-on receiver is not detected1: A powered-on receiver is detected (that is, connected to the DVI transmitteroutputs)This read only register contains the hot plug detection input logic state.

1 HTPLG R/W 0: Logic level detected on the EDGE/HTPLG pin (pin 9)1: High level detected on the EDGE/HTPLG pin (pin 9)This read/write register contains the monitor detect interrupt mode.

0 MDI R/W 0: Detected logic level change in detection signal (to clear, write one to this bit)1: Logic level remains the same

7.6.7 CTL_3_MODE Register (Sub-Address = 0A) [reset = 0x80]


7 6 5 4 3 2 1 0DK[3:1] DKEN CTL[3:1] RSVD

Table 10. CTL_3_MODE Register Field DescriptionsBit Field Type Description

This read/write register contains the de-skew setting, each increment adjusts theskew by t(STEP).000: Step 1 (minimum setup/maximum hold)001: Step 2010: Step 3

7:5 DK[3:1] RW 011: Step 4100: Step 5 (default)101: Step 6110: Step 7111: Step 8 (maximum setup/minimum hold)This read/write register controls the data de-skew enable.

4 DKEN RW 0: Data de-skew is disabled, the values in DK[3:1] are not used1: Data de-skew is enabled, the de-skew setting is controlled through DK[3:1]This read/write register contains the values of the three CTL[3:1] bits that are3:1 CTL[3:1] RW output on the DVI port during the blanking interval.

0 RSVD RW —




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7.6.8 CFG Register (Sub-Address = 0B)

Figure 22. CFG Register

7 6 5 4 3 2 1 0CFG[7:0]

Table 11. CFG Register Field DescriptionsBit Field Type Description

This read-only register contains the state of the inputs D[23:16]. These pins can7:0 (D[23:16]) CFG Read Only be used to provide the user with selectable configuration data through the I2C

bus.

7.6.9 RESERVED Register (Sub-Address = 0E–0C) [reset = 0x97D0A9]

Figure 23. RESERVED Register

7 6 5 4 3 2 1 0RESERVED

Table 12. RESERVED Register Field DescriptionsBit Field Type Description7:0 RESERVED R/W —

7.6.10 DE_DLY Register (Sub-Address = 32) [reset = 0x00]

Figure 24. DE_DLY Register

7 6 5 4 3 2 1 0DE_DLY[7:0]

Table 13. DE_DLY Field DescriptionsBit Field Type Description7:0 DE_DLY R/W This read/write register defines the number of pixels after HSYNC goes active

that DE is generated, when the DE generator is enabled.

7.6.11 DE_CTL Register (Sub-Address = 33) [reset = 0x00]

Figure 25. DE_CTL Register

7 6 5 4 3 2 1 0Reserved DE_GEN VS_POL HS_POL Reserved DE_DLY[8]

Table 14. DE_CTL Register Field DescriptionsBit Field Type Description7 Reserved R/W —

This read/write register enables the internal DE generator.6 DE_GEN R/W 0: DE generator is disabled. Signal required on DE pin

1: DE generator is enabled. DE pin is ignored.This read/write register sets the VSYNC polarity.0: VSYNC is considered active low.5 VS_POL R/W 1: VSYNC is considered active high.Line counts are reset on the VSYNC active edge.This read/write register sets the HSYNC polarity.

4 HS_POL R/W 0: HSYNC is considered active low.1: HSYNC is considered active high. Pixel counts are reset on the HSYNC active edge.

1:3 Reserved R/W —0 DE_DLY[8] R/W This read/write register contains the top bit of DE_DLY.




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7.6.12 DE_TOP Register (Sub-Address = 34) [reset = 0x00]

Figure 26. DE_TOP Register

7 6 5 4 3 2 1 0DE_TOP[7:0]

Table 15. DE_TOP Register Field DescriptionsBit Field Type Description

This read/write register defines the number of pixels after VSYNC goes active7:0 DE_TOP R/W that DE is generated, when the DE generator is enabled.

7.6.13 DE_CNT Register (Sub-Address = 37–36) [reset = 0x0000]

Figure 27. DE_CNT Register

7 6 5 4 3 2 1 0DE_CNT[7:0]

Reserved DE_CNT[10:8]

Table 16. DE_CNT Register Field DescriptionsBit Field Type Description

10:8 DE_CNT R/W These read/write registers define the width of the active display, in pixels, when theDE generator is enabled.7:0 DE_CNT R/W

7.6.14 DE_LIN Register (Sub-Address = 39–38) [reset = 0x0000]

Figure 28. DE_LIN Register

7 6 5 4 3 2 1 0DE_LIN[7:0]

Reserved DE_LIN[10:8]

Table 17. DE_LIN Register Field DescriptionsBit Field Type Description

10:8 DE_LIN R/W These read/write registers define the height of the active display, in lines, when theDE generator is enabled.7:0 DE_LIN R/W

7.6.15 H_RES Register (Sub-Address = 3B−3A)

Figure 29. H_RES Register

7 6 5 4 3 2 1 0H_RES[7:0]

Reserved H_RES[10:8]

Table 18. H_RES Register Field DescriptionsBit Field Type Description

10:8 H_RES Read Only These read-only registers return the number of pixels between consecutiveHSYNC pulses.7:0 H_RES Read Only




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7.6.16 V_RES Register (Sub-Address = 3D−3C)

Figure 30. V_RES Register

7 6 5 4 3 2 1 0V_RES[7:0]

Reserved V_RES[10:8]

Table 19. V_RES Register Field DescriptionsBit Field Type Description

10:8 V_RES Read Only These read-only registers return the number of lines between consecutiveVSYNC pulses.7:0 V_RES Read Only




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8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationThe TFP401 is a DVI (Digital Visual Interface) compliant digital receiver that is used in digital flat panel displaysystems to receive and decode T.M.D.S. encoded RGB pixel data streams. In a digital display system a host,usually a PC or workstation, contains a DVI compliant transmitter that receives 24 bit pixel data along withappropriate control signals and encodes them into a high-speed, low voltage differential serial bit stream fit fortransmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, willrequire a DVI compliant receiver like the TI TFP401 to decode the serial bit stream back to the same 24-bit pixeldata and control signals that originated at the host. This decoded data can then be applied directly to the flatpanel drive circuitry to produce an image on the display. Because the host and display can be separated bydistances up to 5 meters or more, serial transmission of the pixel data is preferred. The TFP401 will supportresolutions up to UXGA.

8.2 Typical Application

Figure 31. Typical Application for the TFP410 Device

8.2.1 Design Requirements

PARAMETER VALUEPower supply 3.3 V dc at 1 AInput clock Single-endedInput clock frequency range 25 MHz — 165 MHzOutput format 24 bits/pixelInput clock latching Rising edgeI2C EEPROM support NoDe-skew No




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8.2.2 Detailed Design Procedure

8.2.2.1 Data and Control SignalsThe trace length of data and control signals out of the receiver should be kept as close to equal as possible.Trace separation should be approximately 5 times the height. As a general rule, traces also should be less than2.8” if possible (longer traces can be acceptable).

Delay = 85 × SQRT × er

where• er = 4.35; relative permativity of 50% resin FR-4 @ 1 GHz• Delay = 177 pS/in (2)

Length of rising edge = Tr(ps) / Delay; Tr = 3 ns

where• = 3000 ps / 177 ps per inch• = 16.9 inches (3)

Length of rising edge / 6 = Max length of trace for lumped circuit. (4)16.9 / 6 = 2.8 inches (5)

Figure 32. Data Signals

8.2.2.2 Configuration OptionsThe TFP410 can be configured in several modes depending on the required input format, for example 1byte/clock, 2 bytes/clock, falling/rinsing clock edge.

Refer to Table 1 for more information about configuration options.




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Pixel samples

Pix

el V

alue

(de

c)

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 340

20

40

60

80

100

120

140

160

180

200

220

240

260

D001

B2 B1 = GND, B0=1B2 B1 B0 = B7 B6 B5

Pixel samples

Pix

el V

alue

(de

c)

0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 640

20

40

60

80

100

120

140

160

180

200

220

240

260

D002

x=GND, y=1x=B7, y=B6


8.2.2.3 Power Supplies DecouplingDigital, analog, and PLL supplies must be decoupled from each other to avoid electrical noise on the PLL and thecore.

Figure 33. Power Decoupling

8.2.3 Application CurvesSometimes the Panel does not support the same format as the GPU (graphics processor unit). In these casesthe user must decide how to connect the unused bits.

Figure 34 and Figure 35 show the mismatches between the 18-bit GPU and a 24-bit LCD where “x” and “y”represent the 2 LSB of the Panel.

Figure 34. 16b GPU to 24b LCD Figure 35. 18b GPU to 24b LCD




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9 Power Supply RecommendationsUse solid ground planes. Tie ground planes together with as many vias as is practical. This will provide adesirable return path for current. Each supply should be on separate split power planes, where each power planeshould be as large an area as possible. Connect PanelBus receiver power and ground pins and all bypass capsto appropriate power or ground plane with via. Vias should be as fat and short as practical, the goal is tominimize the inductance.

9.1 DVDDPlace one 0.01-µF capacitor as close as possible between each DVDD device pins and ground. A 22-µFtantalum capacitor should be placed between the supply and 0.01-µF capacitors. A ferrite bead should be usedbetween the source and the 22-µF capacitor.

9.2 TVDDPlace one 0.01-µF capacitor as close as possible between each TVDD device pins and ground. A 22-µFtantalum capacitor should be placed between the supply and 0.01-µF capacitors. A ferrite bead should be usedbetween the source and the 22-µF capacitor.

9.3 PVDDPlace three 0.01-µF capacitors in parallel as close as possible between the PVDD device pin and ground. A22-µF tantalum capacitor should be placed between the supply and 0.01-µF capacitors. A ferrite bead should beused between the source and the 22-µF capacitor.




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10 Layout

10.1 Layout Guidelines

10.1.1 Layer StackThe pinout of Texas Instruments' High Speed Interface (HSI) devices features differential signal pairs and theremaining signals comprise the supply rails, VCC and ground, and lower-speed signals, such as control pins. Asan example, consider a device X which is a repeater/re-driver, so both inputs and outputs are high-speeddifferential signals. These guidelines can be applied to other high-speed devices such as drivers, receivers,multiplexers, and so on.

A minimum of four layers is required to accomplish a low-EMI PCB design. Layer stacking should be in thefollowing order (top-to-bottom): high-speed differential signal layer, ground plane, power plane and control signallayer.

Figure 36. PCB Stack Up

10.1.2 Routing High-Speed Differential Signal Traces(RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)

Trace impedance should be controlled for optimal performance. Each differential pair should be equal in lengthand symmetrical and should have equal impedance to ground with a trace separation of 2 times to 4 times theheight. A differential trace separation of 4 times the height yields about 6% cross-talk (6% effect on impedance).

We recommend that differential trace routing should be side-by-side, though it is not important that the differentialtraces be tightly coupled together, because tight coupling is not achievable on PCB traces. Typical ratios onPCBs are only 20% to 50%; 99.9% is the value of a well balanced twisted pair cable. Each differential traceshould be as short as possible (< 2 inches is preferable) with no 90° angles. These high-speed transmissiontraces should be on layer 1, which is the top layer.

RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+ signals all route directly from the DVI connector pins to thedevice, no external components are needed.

10.1.3 DVI ConnectorClear-out holes for connector pins should leave space between pins to allow continuous ground through the pinfield. Allow enough spacing in ground plane around signal pins vias however, keep enough copper between viasto allow for ground current to flow between the vias. Avoid creating a large ground plane slot around the entireconnector, because minimizing the via capacitance is the goal.




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10.2 Layout ExampleDVI connector trace matching is shown in Figure 37.

Figure 37. DVI Signal Routing

Keep the data lines as far as possible from each other as shown in Figure 38.




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Layout Example (continued)

Figure 38. Data Signal Routing

Connect the thermal pad to ground as shown in Figure 39.




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Layout Example (continued)

Figure 39. Ground Routing




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10.3 TI PowerPAD 64-Pin HTQFP PackageThe TFP410 is available in TI’s thermally enhanced 64-pin TQFP PowerPAD package. The PowerPAD packageis a 10-mm × 10-mm × 1.0-mm TQFP outline with 0,5 mm lead-pitch. The PowerPAD package has a speciallydesigned die mount pad that offers improved thermal capability over typical TQFP packages of the same outline.The TI 64-pin TQFP PowerPAD package offers a backside solder plane that connects directly to the die mountpad for enhanced thermal conduction. For thermal considerations, soldering the backside of the TFP410 to theapplication board is not required because the device power dissipation is well within the package capability whennot soldered.

Soldering the backside of the device to the PCB ground plane is recommended for electrical considerations.Because the die pad is electrically connected to the chip substrate and hence chip ground, connecting the backside of the PowerPAD package to a PCG ground plane provides a low-inductance, low-impedance connection tohelp improve EMI, ground bounce, and power supply noise performance.

Table 20 contains the thermal properties of the TI 64-pin TQFP PowerPAD package. The 64-pin TQFP non-PowerPAD package is included only for reference.

Table 20. TI 64-Pin TQFP (10-mm × 10-mm × 1.0-mm) / 0.5-mm Lead-PitchPowerPAD™ PowerPAD™WITHOUTPARAMETER NOT CONNECTED TO CONNECTED TO PCBPowerPAD™ PCB THERMAL PLANE THERMAL PLANE (1)

RθJA Thermal resistance, junction-to-ambient (1) (2) 75.83°C/W 42.20°C/W 21.47°C/WRθJC Thermal resistance, junction-to-case (1) (2) 7.80°/W 0.38°C/W 0.38°C/W

Power handling capabilities of packagePD 0.92 W 1.66 W 3.26 W(1) (2) (3)

(1) Specified with the PowerPAD bond pad on the backside of the package soldered to a 2-oz. Cu plate PCB thermal plane.(2) Airflow is at 0 LFM (no airflow)(3) Specified at 150°C junction temperature and 80°C ambient temperature.




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11 Device and Documentation Support

11.1 TrademarksPowerPAD, EPIC-5, PanelBus are trademarks of Texas Instruments.Intel is a trademark of Intel Corporation.All other trademarks are the property of their respective owners.

11.2 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

11.3 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.




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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TFP410PAP ACTIVE HTQFP PAP 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TFP410PAP

TFP410PAPG4 ACTIVE HTQFP PAP 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TFP410PAP

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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PACKAGE OPTION ADDENDUM

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Addendum-Page 2

OTHER QUALIFIED VERSIONS OF TFP410 :

• Enhanced Product: TFP410-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

http://focus.ti.com/docs/prod/folders/print/tfp410-ep.html

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device PackageName

PackageType

Pins SPQ Unit arraymatrix

Maxtemperature

(°C)

L (mm) W(mm)

K0(µm)

P1(mm)

CL(mm)

CW(mm)

TFP410PAP PAP HTQFP 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13

TFP410PAPG4 PAP HTQFP 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1

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GENERIC PACKAGE VIEW

This image is a representation of the package family, actual package may vary.Refer to the product data sheet for package details.

HTQFP - 1.2 mm max heightPAP 64QUAD FLATPACK10 x 10, 0.5 mm pitch

4226442/A

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