Introduction

This document guides youthrough the design-test-optimizeloop associated with usingAgilent Technologies’ serial linkoptimizer with Xilinx FPGAs. Itoutlines the process of specifyinga high-speed serial interfaceusing Xilinx RocketIO technology,creating an internal bit errorratio test (IBERT) core withXilinx ChipScope Pro Serial I/OToolkit, using Agilent’s serial linkoptimizer with that IBERT core toanalyze and optimize the link’sBER, and incorporating theresults back into the designsource. You will find moredetailed information on the

Table of Contents

Specifying the Xilinx RocketIO Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Using the RocketIO Architecture Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

RocketIO Architecture Wizard results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Creating an IBERT Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Using the Agilent E5910A Serial Link Optimizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Incorporating Serial Link Optimizer Results in Your Design . . . . . . . . . . . . . . . . . . . . . . . 19

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Sales and Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

configuration options for Xilinx RocketIO multi-gigabittransceivers in the Xilinx UG076Virtex-4 RocketIO Multi-GigabitTransceiver User Guide.

The Agilent E5910A serial linkoptimizer uses the IBERT core to enable channel-oriented BERmeasurements on your serial link.You can measure BER, analyzemargin with eye maps generatedfrom BER measurements, andperform automatic tuning of transmitter and receiverequalization settings. Serial linkoptimizer saves you considerabletime and automates the tasks ofdebugging, testing and tuningyour serial link.

Testing and OptimizingHigh-Speed Serial Links with theAgilent E5910A serial link optimizer

Technical Overview

2

Specifying the Xilinx RocketIO Core

Xilinx recommends the use of theRocketIO Architecture Wizard toinsert multi-gigabit transceivers(MGTs) into designs. The wizardcreates hardware descriptionlanguage (HDL) instantiationtemplates and code that definethe attributes for customapplications. The wizard alsocreates a user constraints file(UCF) containing the MGTattributes.

Using the RocketIO Architecture Wizard

This wizard is normally aseparate installation fromXilinx’s integrated softwareenvironment (ISE). You candownload the wizard from theXilinx update Web site atwww.xilinx.com/download. Whenyou are ready to insert an MGTinto your design, launch theRocketIO Architecture Wizard.You add a new source file to yourdesign, specifying the use of theRocketIO Wizard.

Figure 1. Launch the RocketIO Architecture Wizard

3

Specifying the Xilinx RocketIO Core (continued)

Step 1Specify your protocolThe first screen of the RocketIOWizard asks you for the intendedprotocol and the silicon versionof your target FPGA. You haveseveral common serial I/Ostandards to choose from or youcan select a custom protocol.Note that the device is specifiedwhen the ISE project is created.

Figure 2. RocketIO Architecture Wizard – Step 1

Step 2Specify MGT placement and referenceclock setupContinue configuring the designwith the MGT placement andreference clock(s) setup. The MGTplacement will depend on yourPCB layout. The reference clockuses dedicated routing, and theclock is multiplied inside the MGTto serialize/deserialize the data.The reference clock is verysensitive to noise because anyerror in the clock is multiplied.

Figure 3. RocketIO Architecture Wizard – Step 2

4

Specifying the Xilinx RocketIO Core (continued)

Step 4Select digital settingsThe next step includes selectingcomma alignment options,choosing a comma detectionscheme, and configuringsynchronization. Alignment isnecessary to convert the serial bit stream into parallel data. Thereceiver looks for and aligns thedata to a predefined comma.Comma detection is a set ofcontrol signals that can be usedby your specific application. TheMGT blocks have a transmit FIFOand a receiver buffer that can bebypassed to reduce data latency.

Figure 5. RocketIO Architecture Wizard – Step 4

Step 3Specify the data pathSpecify the data path, whichincludes the data width and line rate. You also select theencoding/decoding scheme in this step. You can also choose tobypass encoding/decoding andimplement a custom scheme inthe FPGA fabric.

Figure 4. RocketIO Architecture Wizard – Step 3

5

Specifying the Xilinx RocketIO Core (continued)

Step 5Configure channel bondingChannel bonding is a way toincrease bandwidth by treatingmultiple channels as a single data channel. Data is split and transmitted by multipletransmitters and received bymultiple receivers. When data istransmitted, the data is perfectlyaligned. Channel bondingeliminates channel-to-channelskew and aligns the data in thereceive buffer. Select the channelbonding settings that correspondto your design.

Figure 6. RocketIO Architecture Wizard – Step 5

Step 6Configure clock correctionWith serial transmission the clockis embedded in the data stream.The receiver extracts the clockusing clock and data recovery. By selecting the appropriate clock correction settings in thisstep, you can account for smalldifferences in the transmitter andreceiver clock frequencies.

Figure 7. RocketIO Architecture Wizard – Step 6

6

Specifying the Xilinx RocketIO Core (continued)

Step 7Select analog settingsIn this step, you select the analogsettings for the phase-locked loopand equalization controls thatwill best match your design.

Figure 8. RocketIO Architecture Wizard – Step 7

Step 8Configure special features Cyclic redundancy check (CRC) is a method of error checking.Before transmission, data isencapsulated into packetsbounded by start-of-packet (SOP) and end-of-packet (EOP)sequences. CRC is calculated inthe transmitter and the 4-byteCRC is inserted at the end of eachpacket. The receiver will calculateCRC on the received data andcompare it to the transmittedCRC. Errors are flagged.

This step allows you to selectoptional features of the RocketIOcore that enable error checking(CRC) and other special features.Select the options consistent withyour design and the additionalcapability you need for debug. Figure 9. RocketIO Architecture Wizard – Step 8

7

Specifying the Xilinx RocketIO Core (continued)

Step 9Check your setupWhen you have completed theRocketIO setup using the wizard,you’ll see a summary of thesettings you chose. Check thesummary to make sure your setupappears as you intended.

Please see the Xilinx RocketIOWizard for Virtex-4 FPGAsGetting Started Guide for moreinformation.

Figure 10. RocketIO Architecture Wizard – Step 9

8

Specifying the Xilinx RocketIO Core (continued)

RocketIO Architecture Wizard results

The RocketIO ArchitectureWizard creates the directorystructure displayed in Figure 11.

The architecture wizardgenerates an example designbased on the settings you chose in steps 1-9. You can test theexample design in hardware; it is built using a perl script locatedin the scripts folder. The scriptwill synthesize, build, map, place,

Figure 11. Wizard results

and route the example design,producing a bitmap file. Thisdesign includes severalChipScope modules to drive and monitor the signals.

The example design can also besimulated. The wizard provides acommand line script to simulateand observe the behavior of the design.

The example folder also containsHDL instantiation templates thatare sometimes called “wrappers.”

The wrapper is the primarymodule that wraps one or moreMGT primitives configured for theapplication by the wizard. Youcan instantiate this module inyour design instead of individualMGT primitives, and you canrefer to the example design fordetails. The Verilog and VHDLsource code is located in the srcdirectory. You can modify MGTattributes directly in the sourcecode or at a higher level in the.ucf file located in the ucf folder.

9

Creating an IBERT Core

IBERT is a configurable core that provides all of the resourcesneeded to perform bit error ratiotest on channels composed ofMGTs. The ChipScope Pro CoreGenerator generates the IBERTcore as part of a full standalonedesign including a bitstream.Please refer to the XilinxChipScope Pro Serial I/O ToolkitUser Guide for more information.In this chapter, an IBERT corewill be generated that will beused to make measurements onserial channels with the Agilentserial link optimizer.

IBERT core generation

You will need to install theChipScope Pro Serial I/O Toolkitwith the proper license enabledto generate IBERT cores. TheChipScope Pro Core Generator is used to generate the core byfirst selecting IBERT as the coretype, as shown in Figure 12. Thegenerator walks you throughIBERT core configuration with astep-by-step “wizard,” as follows.

Figure 12. IBERT Core Generation

10

Step 1Specify the device and silicon revisionSpecify the device you are usingand the silicon revision using thepulldown menus.

Figure 13. IBERT Core Generator – Step 1

Step 2Select clock source settingsTo use an MGT, at least oneMGTCLK on a given side must beenabled. Enable the MGTCLK thatmatches the REFCLK in yourRocketIO Architecture Wizardsetup. The maximum frequencyshould match that of the REFCLK,and it will be multiplied internally.

Figure 14. IBERT Core Generator – Step 2

Creating an IBERT Core (continued)

11

Step 3MGT placementThis setup should also match thesetup in your design, as specifiedin the RocketIO ArchitectureWizard.

Figure 15. IBERT Core Generator – Step 3

Creating an IBERT Core (continued)

12

Creating an IBERT Core (continued)

Step 4Add GPIO output pinsAdd GPIO output pins to theIBERT core if desired, and selectwhether to drive them from thevirtual I/O (VIO) core.

Figure 16. IBERT Core Generator – Step 4

13

Creating an IBERT Core (continued)

Step 5Select example and output optionsIf you wish, Core Generator cancreate an argument file (.arg) soyou can generate the next IBERTcore from the command line.Simply check the box to selectthis option, and select whether ornot Core Generator will producea log file.

Figure 17. IBERT Core Generator – Step 5

14

Creating an IBERT Core (continued)

Step 6Generate the coreClicking Generate Design, as shownin Figure 17, will produce the coreas an entire Xilinx design. Thefinal output is a bitstream (.bit)file for programming your FPGA.

Figure 18. IBERT Core Generator – Step 6

15

Creating an IBERT Core (continued)

You must repeat the IBERT coregeneration process for each FPGAbeing used. A user design with anMGT pair is shown in Figure 19.

MGT MGT

Tx

Rx

Rx

Tx

Virtex-4 FXVirtex-4 FX

Figure 19. Setup using multiple FPGAs

The links will be analyzed one ata time with the Agilent serial linkoptimizer. This first link to bemeasured is illustrated inFigure 20. Tx Rx Virtex-4 FXVirtex-4 FX

Figure 20. First serial link to be analyzed

16

Using the Agilent E5910A Serial Link Optimizer

In this chapter, you will use theIBERT core(s) generated in theprevious chapter in conjunctionwith the Agilent E5910A seriallink optimizer to optimize eachserial link.

This section of the technicaloverview describes the use of the Agilent E5910A serial linkoptimizer. Start by configuringthe JTAG controllers to enabledevice communication via yourXilinx programming cable(s).

You can add up to two JTAGcontrollers to support devices on different JTAG scan chains.Xilinx does not support multipleUSB cables on a single PC, so onecable will be a USB cable and thesecond will be a parallel cable ora remote connection to anotherPC with a Xilinx cable connected.

Once you have established devicecommunication, configure thedevice(s) with the IBERT .bitfile(s) generated using XilinxChipScope Pro Core Generator, if necessary.

Figure 21. Agilent serial link optimizer

Figure 22. Device configuration fromserial link optimizer

17

Using the Agilent E5910A Serial Link Optimizer (continued)

Next, you specify the transmitterand receiver pair that define the link to be tested from thedropdown menu. The choicesavailable will depend on what youenabled in the IBERT core usingthe ChipScope Pro CoreGenerator.

Once the channel is specified,select the line rate and testpattern to use. There arenumerous patterns you can chosefrom, including various PRBSpatterns. Clicking Tx Settingsor Rx Settings will display thecurrent MGT settings and allowyou to manually adjust them ifyou choose.

With the setup complete, you areready to move to measurements.These are presented by way ofthree tabs on the right side of thescreen; the first is the BERT tab,as shown in Figure 24.

Click Run to display the wordcount transmitted along with the resulting error count and biterror ratio. You also can injecterrors. Click Inject Error to checkfor a working test.

Figure 23. Transmitter/receiver selections

Figure 24. BERT measurement with serial link optimizer

18

Using the Agilent E5910A Serial Link Optimizer (continued)

The second tab provides you withan eye map using the currentMGT settings, allowing easyvisualization of margin. The eyemap shows bit error ratio plottedas a function of time. The timeaxis can be displayed in terms ofunit interval (UI) fraction, phaseoffset (in %), or actual time(provided line rate is set),selectable in the pull-down menu.The eye map is generated byperforming BER test at each of 32sample positions within the unitinterval. Controls are provided forsetting the maximum amount oftime BER is tested at each sampleposition (dwell time) as well asallowing cumulative display ofmeasurements over multiple runs(select Run Repetitively).

Now select the Tuning tab. ClickingRun will perform automatictuning of transmitter and receiversettings (or receiver only) for thebest eye (BER). When tuning iscomplete, the window will displayeye maps representing linkmargin before and after tuning.

When the tuning is complete, youcan export the results. Simplyclick Export Settings and a .txt file is created containing themodified (after tuning) MGTsettings. Use of these settings iscovered in the next chapter.

Figure 25. Eye map with serial link optimizer

Figure 26. Automatic tuning with serial link optimizer

19

Incorporating Serial Link Optimizer Results in Your Design

The final step in this technicaloverview is to apply the seriallink optimizer tuning results to your design. The serial linkoptimizer will provide a templateif you click Export Settings whentuning is complete. This opens aNotepad window containing atext (.txt) file with the modifiedMGT attributes. The attributesare provided in HDL (both Verilogand VHDL) syntax along withUCF syntax. This gives you theflexibility of applying the resultsto your HDL source code (simplycut and paste) or at a higher levelin the UCF file.

Figure 27. Exporting tuning results

Summary

In this document we haveprovided an overview of the stepsto follow for implementing ahigh-speed serial data channelwith Xilinx Virtex-4 MGTs andtesting that serial channel withAgilent’s serial link optimizer.The four chapters in this guidecomprise the four main tasks

associated with this process,namely configuring andimplementing the MGTsthemselves, generating an IBERTcore for performing tests withserial link optimizer, using seriallink optimizer with the core tomake measurements and tune the

channel, and finally feeding backthe results of the tuning into theoriginal design. While you willneed to adapt some of the detailsin the steps in this overview to your specific design, thisdocument provides a reference ofthe basic process to be followed.

www.agilent.com/find/open

Agilent Open simplifies the process of

connecting and programming test systems

to help engineers design, validate and

manufacture electronic products. Agilent

offers open connectivity for a broad range

of system-ready instruments, open industry

software, PC-standard I/O and global

support, which are combined to more easily

integrate test system development.

www.agilent.com

For more information on Agilent

Technologies’ products, applications

or services, please contact your local

Agilent office. The complete list is

available at:

www.agilent.com/find/contactus

Phone or Fax

United States:(tel) 800 829 4444(fax) 800 829 4433

Canada:(tel) 877 894 4414(fax) 800 746 4866

China:(tel) 800 810 0189(fax) 800 820 2816

Europe:(tel) 31 20 547 2111

Japan:(tel) (81) 426 56 7832(fax) (81) 426 56 7840

Korea:(tel) (080) 769 0800(fax) (080) 769 0900

Latin America:(tel) (305) 269 7500

Taiwan:(tel) 0800 047 866 (fax) 0800 286 331

Other Asia Pacific Countries:(tel) (65) 6375 8100 (fax) (65) 6755 0042Email: tm_ap@agilent.comRevised: 11/08/06

Product specifications and descriptions

in this document subject to change

without notice.

© Agilent Technologies, Inc. 2007

Printed in USA, January 16, 2007

5989-6048EN

www.agilent.com/find/emailupdates

Get the latest information on the products

and applications you select.

www.agilent.com/find/agilentdirect

Quickly choose and use your test

equipment solutions with confidence.

Agilent Email Updates

Agilent Direct

AgilentOpen

Remove all doubt

Our repair and calibration services will get

your equipment back to you, performing

like new, when promised. You will get

full value out of your Agilent equipment

throughout its lifetime. Your equipment

will be serviced by Agilent-trained

technicians using the latest factory

calibration procedures, automated repair

diagnostics and genuine parts. You will

always have the utmost confidence in

your measurements.

Agilent offers a wide range of additional

expert test and measurement services for

your equipment, including initial start-up

assistance onsite education and training,

as well as design, system integration,

and project management.

For more information on repair and

calibration services, go to

www.agilent.com/find/removealldoubt

References

Xilinx UG076 Virtex-4 RocketIO Multi-Gigabit Transceiver User GuideXilinx UG246 RocketIO Wizard for Virtex-4 FPGAs Gettting Started GuideXilinx ChipScope Pro Serial I/O Toolkit User Guide

Related literature

Publication title Publication type Publication number

Agilent E5910A Serial Link Optimizer Data sheet 5989-5969EN

www.agilent.com/find/fpga