testbench_ececpe_pt1

7/30/2019 Testbench_ECECPE_pt1

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TESTBENCH


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Introduction to Verilog Testbench

Writing a testbench is as complex as writingthe RTL code itself. These days ASICs aregetting more and more complex and thusverifying these complex ASIC has become a

challenge.

Developing tests for your designs can takemuch more time and more code than the

original models. Typically 60-70% of time needed for any ASIC

is spent on verification/ validation/ testing.


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Introduction to Verilog Testbench

The main purpose of modeling testbench To determine if you are designing and building the

correct circuit or system.

To simulate the environment in which the circuit will

function, and to exercise all of the functionality of yourcircuit.

To exercise every possible scenario that the circuitmay encounter.


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Type of Test

1) Functional Testing2) Regression Testing

3) Sign-Off


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Functional Testing

The most common types of tests because theytest the expected functionality.

These tests apply the expected inputs and lookfor correct responses.

During the development of your model, your firsttests will exercise what you expect to happen.

Functional tests do not necessarily test every

possible manufacturing fault, nor do theynecessarily test every possible set of inputs.


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Regression Testing

During the progress of a design, you should developa set of tests with known responses. Each time youmake a change to the design, you should rerun thetests and compare the results from the new model to

the results from the old model. This rerunning of tests and matching the results to a

known, good set of results is called regressiontesting.

The purpose of regression testing is to verify that noerrors are introduced into the circuit as the designevolves.


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Sign-Off

When your design is ready for fabrication, youwill need a set of tests that will be run againstthe design when it is fabricated. The purpose ofthe sign-off tests is to detect any manufacturing

faults. There are special simulators (called faultsimulators) that can determine if your testsexercise and detect all possible manufacturingfaults.


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Unit Test vs. System Test

A un it test , tests an individual module, ora small set of modules, that form afunctional unit in your design.

A sys tem test , tests a larger group ofmodules that forms a complete system. Alarge design project will have acombination of both system and unit tests.


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Review Operators

Binary Arithmetic OperatorsOperators Name+ Addition- Subtraction* Multiplication/ Division% Modulus

Relational OperatorsOperators Name

> Greater than>= Greater than or equal< Less than


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Review Operators

Logical OperatorsOperators Name

! Logical negation

&& Logical and|| Logical or

Bitwise OperatorsOperators Name

~ Bitwise negation

& Bitwise and| Bitwise or

^ Bitwise xor

~& Bitwise nand

~| Bitwise nor

^~ Bitwise not xor


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Review Operators

Unary Reduction OperatorsOperators Name

& and Reduction

| or Reduction

^ xor Reduction~& nand Reduction

~| nor Reduction

~^ xnor Reduction

Other OperatorsOperators Name

=== Case equality

!== Case inequality

{ , } Concatenation> Shift right

? : Conditional


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Timing Control

Non-intra Assignment Delay Intra-Assignment Delay

#__ C = A + B;

In non-intra-assignment controls (delay or event control on

the left side), the right side expression is evaluated after thedelay or event control.

Intra-assignment controls always evaluate the right sideexpression immediately and assign the result after the delayor event control.

C = #__ A + B;


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Control Construct

Verilog has a rich collection of control statements whichcan used in the procedural sections of code, i. e., withinan initial or always block.

if and if else Statement

case forever

repeat

while

for


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if and if else statement

The conditional statement (or if-else statement)is used to make a decision as to whether astatement is executed or not.

EXAMPLE:

if (A == 4) begin

B = 2;

end

else beginB = 0;

end


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case

The case statement is a multiway decisionstatement that tests whether an expressionmatches one of a number of other expressionsand branches accordingly.

EXAMPLE:

case (sig)

1'bz: $display("signal is floating");

1'bx: $display("signal is unknown");

default: $display("signal is %b", sig);endcase


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forever

Forever Continuously executes a statement orblock till the end of simulation.

EXAMPLE:

initial beginclock =0;

forever begin

#10 clock = ~clock;

endend


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repeat

Executes a statement a fixed number of times. Ifthe expression evaluates to unknown or highimpedance, it shall be treated as zero, and nostatement shall be executed.

EXAMPLErepeat (16) begin

$display ("Current value of i is %d", i);

i = i + 1;

end


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while

Executes a statement until an expressionbecomes false. If the expression starts out false,the statement shall not be executed at all.

EXAMPLE:

initial beginx = 0;

while( x


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for

Controls execution of its associated statement(s) by a three-step

process, as follows:

a) Executes an assignment normally used to initialize a variablethat controls the number of loops executed.

b) Evaluates an expression if the result is zero, the for-loop shallexit, and if it is not zero, the for-loop shall execute its associatedstatement(s) and then perform step c. If the expressionevaluates to an unknown or high-impedance value, it shall betreated as zero.

c) Executes an assignment normally used to modify the value ofthe loop-control variable, then repeats step b.

EXAMPLE:

parameter loops = 8;

...

for (k=0; k


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Structured Procedures

All procedures in the Verilog HDL arespecified within one of the following fourstatements: initial construct

always construct

task

function

The initial and always constructs are

enabled at the beginning of asimulation.

The task and function construct aredisable at the beginning and it will beenable only when it is called.


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Initial

An initial block consists of a statement or agroup of statements enclosed in begin ... end ora single statement , which will be executed onlyonce at simulation time 0.

If there is more than one block, they executeconcurrently and independently.

The initial block is normally used for initialization,monitoring, generating wave forms (eg, clockpulses) and processes which are executed oncein a simulation.


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Example using initial

EXAMPLE:

initial

clock = 1'b0; // variable initialization

initial begin // multiple statements

// have to be groupedalpha = 0;

#10 alpha = 1; // waveform generation

#20 alpha = 0;

#5 alpha = 1;#7 alpha = 0;

#10 alpha = 1;

#20 alpha = 0;

end;


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Always

An always block is similar to the initialblock, but the statements inside an alwaysblock be will repeated continuously, in alooping fashion, until stopped by $finish or$stop. NOTE: the $finish command actually terminates thesimulation where as $stop command actually suspend thesimulation or merely pauses it and awaits further instructions or .Thus $finish is the preferred command.

One way to simulate a clock pulse isshown in the example below.


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Example using always

module pulse;

reg clock;

// start the clock at 0

initial

clock = 1'b0;// toggle every 10 time units

always

#10 clock = ~clock;

// end the simulation after 5000 time unitsinitial

#5000 $finish

endmodule


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Tasks and Functions

Distinctions Between Tasks and Functions A function must execute in one simulation time

unit; a task can contain time-controllingstatements.

A function cannot enable a task; a task canenable other tasks and functions.

A function must have at least one input

argument; a task can have zero or morearguments of any type.


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Task

Tasks are used to group a set of repetitive or relatedcommands that would normally be contained in an initialor always block.

The lines of code are enclosed in task ... endtaskbrackets.

Data is passed to the task, the processing done, and theresult returned. Included in the main body of code, theycan be called many times, reducing code repetition.


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Example using tasks

Sample 1: Basic structure of a tasks with separate module (this_task.v)

module this_task;

task my_task;

input a, b;

inout c;

output d, e;

reg foo1, foo2, foo3;begin

foo1 = a + b; // the set of statements that

foo2 = b + c; // performs the work of the task

foo3 = c + a;

c = foo1; // the assignments that initialize

d = foo2; // the results variablese = foo3;

end

endtask

endmodule


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Calling a tasks

The following statement enables the task in example above

module call_task;

`include this_task.v

my_task (v, w, x, y, z);

The calling arguments (v, w, x, y, z) correspond to the I/O arguments (a, b, c, d,e) defined by the my_task. At task enabling time, the input and inout

arguments (a, b, and c) receive the values passed in v, w, and x.a = v; b = w; c = x;

As part of the processing of the task, the task definition formy_task must

place the computed results values into c, d, and e. When the task completes,the processing software performs the following assignments to return thecomputed values to the calling process:

x = c; y = d; z = e;


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Function

A function cannot enable a task however functions canenable other functions.

A function will carry out its required duty in zerosimulation time.

Within a function, no event, delay or timing controlstatements are permitted.

In the invocation of a function their must be at least oneargument to be passed.

Functions will only return a single value and can not useeither output or inout statements.

Function cannot have nonblocking statements.


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Example using function

Sample 1: Basic structure of a function

module function_calling(a, b, c);

input a, b ;output c;

wire c;

function myfunction;input a, b;

beginmyfunction = (a+b);end

endfunction

assign c = myfunction (a, b);

endmodule


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End

Thank You

testbench_ececpe_pt1

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