Microelectronics Reliability 52 (2012) 974–983

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Microelectronics Reliability

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Temperature dependent drain current model for Gate Stack Insulated ShallowExtension Silicon On Nothing (ISESON) MOSFET for wide operating temperaturerange

Vandana Kumari a, Manoj Saxena b, R.S. Gupta c, Mridula Gupta a,⇑a Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi 110 021, Indiab Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, Karampura, New Delhi 110 015, Indiac Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, Rohini, Delhi 110 086, India

a r t i c l e i n f o a b s t r a c t

Article history:Received 28 June 2011Received in revised form 3 December 2011Accepted 21 December 2011Available online 14 January 2012

0026-2714/$ - see front matter � 2011 Elsevier Ltd. Adoi:10.1016/j.microrel.2011.12.021

⇑ Corresponding author. Tel.: +91 11 24115580; faxE-mail addresses: vandanakumari511@gmail.com (

yahoo.co.in (M. Saxena), rsgu@bol.net.in (R.S. Gu(M. Gupta).

This paper presents two dimensional temperature dependent analytical model of Gate Stack InsulatedShallow Extension Silicon On Nothing (ISESON) MOSFET and compares it with the simulated data usingATLAS 3D device simulator for wide operating temperature i.e. 300–500 K for channel length down to32 nm technology node. In this work, a temperature dependent analytical expression of drain currentfor sub-threshold region to saturation region has been developed. Lower sub-threshold slope and reducedleakage current in case of ISESON MOSFET (as compared to ISE and SON) results in better NMOS inverterperformance and hence ISESON can be widely used in CCD camera as well as for fast switching applica-tions. Further, we have also investigated the impact of temperature on electrical characteristics of ISESONMOSFET which are important for analog applications.

� 2011 Elsevier Ltd. All rights reserved.

1. Introduction

MOSFETs are widely used in amplifier design, analog ICs, powerelectronics and switching devices for high temperature applica-tions. Usage of bulk MOSFET in high temperature range has beenlimited by the latch-up problem [1]. The device is usually exposedto large range of temperature variation when used in the area ofnuclear power plant and for space applications [2]. The impact ofhigh temperature on electrical performance of MOSFET are: (a)reduction in threshold voltage, (b) degradation in off state current(Ioff) and (c) reduction in drain current due to mobility degradation[3] and increase in intrinsic carrier concentration [4–6]. DIBL effectis insensitive to temperature variation [7] which can be explainedby the fact that Vth roll-off results from capacitive coupling be-tween the channel and drain, which is temperature independentphenomenon. In fact, for sub-100 nm channel length, device per-formance deteriorates due to emergence of typical SCEs such asthreshold voltage roll-off and increased leakage current [8].Various novel MOSFET device architectures have been proposedin past such as super halo [9], steep source/drain junction [10] toreduce SCEs. However, the usage of these devices is limited, dueto tremendous increase in band-to-band leakage current. In order

ll rights reserved.

: +91 11 24110606.V. Kumari), saxena_manoj77@pta), mridula@south.du.ac.in

to reduce the electrostatic coupling between source and drain, ad-vance lateral channel engineered device architecture (i.e. InsulatedShallow Extension MOSFET) was proposed which reduces the elec-trostatic coupling between the source and drain through side pil-lars [11]. SOI MOSFET has also received enough attention in pastfor its usage at high temperatures [12]. However the electrostaticcoupling between the source and drain through the buried oxideis large, in case of SOI, which acts like a field guideline [13,14].Hence, as an alternative, Silicon On Nothing (SON) technologywas proposed in year 2000 [15] by Jurczak et al.

For an improved device performance and for high temperatureapplications, Silicon On Nothing (SON) MOSFET can be used in con-junction with the Insulated Shallow Extension (ISE) MOSFET. Inthis paper, the performance of ISESON MOSFET is studied for hightemperature (i.e. 300–500 K) operation. In ISESON architecture theS/D as well as the body is surrounded by the insulator which cutsoff the path of substrate leakage current [16]. For further enhance-ment, gate stack architecture [17] has been incorporated in thedevice.

In present work, an analytical expression of drain current forgate stack ISESON MOSFET is presented and compared with theresults obtained from ATLAS 3D device simulator. The analog per-formance in terms of device efficiency, intrinsic gain, output resis-tance, gmmax and early voltage of ISESON has also been studied andis compared with the ISE MOSFET and the SON MOSFET for wideoperating temperature ranges (i.e. 300–500 K). In order to studythe device performance for digital application, the performance

V. Kumari et al. / Microelectronics Reliability 52 (2012) 974–983 975

of NMOS inverter (using ATLAS 3D mixed mode simulation) isstudied and is compared with the ISE and SON based NMOS inver-ter for 300–500 K. For fair device comparison all the devices havebeen optimized for Vth = 0.25 V @ Vds = 0.5 V [18–20].

2. Device fabrication feasibility

2.1. ISE fabrication

In 2001, Jurczak et al. [11] reported experimental ISE MOSFETfor 0.12 lm gate length fabricated by implanting dielectric pillarthrough anisotropic plasma etching technique. In 2006, Wangand Wang [21] reported fabrication feasibility of ISE MOSFET inwhich dielectric pillar (Plug) was fabricated by forming an oxidelayer over exposed source and drain regions in the substrateincluding a stacked gate electrode. The oxide layers in the sourceand drain regions are then substantially removed, to expose thesubstrate in the source and drain regions, and to leave the portionof oxide layer (under the gate electrode) to form the dielectric pil-lar (Plug) and the channel between S/D regions.

2.2. SON fabrication

The first step towards the fabrication of SON MOSFET was in1999, when Jurczak et al. [22] proposed a substrate engineeringtechnique named SONCTION (SilicON Cut of juncTION). In the sameyear, Sato et al. [23] proposed a new substrate engineering tech-nique for the formation of Empty Space in silicon (ESS) in whichthe self organizing migration properties on the silicon surface wereused. In 2000, Jurczak et al. [15] demonstrated experimentallymorphological feasibility of SON MOSFET devices fabricated usingSONCTION technique and their integration within conventional sil-icon CMOS process. In 2001, Monfray et al. [24] presented the firstsub 100 nm SON MOSFET using SONCTION technique on bulk wa-fer with very thin (20 nm) silicon channel and isolated it from thebulk by a 20 nm dielectric layer. In 2006, SON was created by Sili-con-On-Void (SOV) process [25], in which a layer of voids is formedby H+/He+ co-implantation, followed by nitrogen annealing. In2007, Kilchytska et al. reported alternative approach for fabricatingSON device based on the wafer bonding of a thin silicon layer overa pre-etched cavity [26].

Therefore, fabrication feasibility of ISESON MOSFET seems pos-sible in future by integrating the individual ISE and SON MOSFETfabrication steps.

Fig. 1. Cross section view of a gate stack ISE-SON MOSFET with gate length L = 90 nm(Shallow extension depth) = 5 nm, Um = 4.77 eV, N3 = 2 � 1017 cm�3.

3. Model formulation

Two dimensional analytical models for ISE MOSFET were re-ported by Shih et al. [8] and Kaur et al. [27] based on a closed formsolution in the channel region evaluated using Evanescent ModeAnalysis (EMA). Pretet et al. [28] and Kasturi et al. [29] reportedanalytical model for SON MOSFET. Various physical models thatare used in device simulations (in present work) are concentrationdependent mobility model (CONMOB), transverse field (FLDMOB)and temperature dependent Arora model. Shockley–Read–Hall(SRH) model and Auger recombination model are also includedin the simulation [30]. The inversion layer quantum effects arenot considered in the present analysis as they are more significantfor thickness smaller than 5 nm and for channel length below10 nm [31,32]. Fig. 1 shows the schematic cross-sectional view ofa gate stacked ISESON MOSFET along with the boundary condi-tions. Vbi is the built in potential across the interface betweenthe source/drain and silicon body and is given by:

Vbi ¼ kTq ln N3

Ndn2

i

� �; where q is the electronic charge, N3 is the

channel doping, Nd is the doping of the source and drain regionand ni is the temperature dependent intrinsic carrier concentrationgiven by:

ni ¼ ðNcNvÞ0:5 expð� Eg2kTÞ; where Nc and Nv represents the density

of states in conduction band and the valance band respectively [30]and can be expressed as:

Nc ¼ 1:73� 1016T32; Nv ¼ 4:8� 1015T

32; ð1Þ

Expression of band gap Eg used in the model is given by:

Eg ¼ Egð0Þ � 6:5� 10�4 � T2

T þ 200ð2Þ

where T is the operating temperature and Eg(0) is the band gap atT = 300 K.

The Poisson’s equations in all the five different regions can beexpressed as:

d2/Fiðx; yÞdx2 þ d2/Fiðx; yÞ

dy2 ¼ qNi

eið3Þ

where i = 1,2,3,4,5 stands for the five different regions. Eq. (3) canbe solved by using superposition method and the resultant solutionof /Fi(x, y) (i = 1,2,3,4,5) can be decomposed into 1D potential

, t1 = 2 nm, t2 = 1 nm, t3 = 20 nm, t4 = 20 nm, Tst (Side pillar thickness) = 10 nm, Xe

976 V. Kumari et al. / Microelectronics Reliability 52 (2012) 974–983

solution (Poisson equation) and 2D potential solution (Laplaceequation) as:

/Fi ¼ /LchiðyÞ þ /Schiðx; yÞ ð4Þ

where /Lchi(y) is the one dimensional potential in the transversedirection and /schi(x, y) is the 2D potential in different regions ofthe device.

3.1. One-dimensional potential analysis

The 1D potential in all the five regions can be expressed as:

d2/LchiðyÞdy2 ¼ qNi

eið5aÞ

/LchiðyÞ ¼qNi

2ei

Xi

j¼1

tj � y

" #2

þ Ci1

Xi

j¼1

tj � y

" #þ Ci2 ð5bÞ

Pi�1j¼0tj 6 y 6

Pij¼0tj for all the regions. Ni specifies the doping con-

centration in all the five regions. The various one dimensional(1D) constants are obtained by using standard boundary conditions(as shown in Table 1) at the interface of the different regions. In Eq.(5b), tj and ei are the thickness and permittivity of the different re-gions in the device as shown in Fig. 1. t5 is the temperature depen-dent depletion width in the substrate region given by:

T5 ¼�Q �

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiQ 2 � 2ðqN5=e5ÞP

qqN5=e5

ð6Þ

where P and Q are given as:

P ¼ qN3

2e3t2

3 þ qN3t3t1

e1þ t2

e2

� �� Vgs þ V fb þ V sub ð6aÞ

Q ¼ qN5t1

e1þ t2

e2þ t3

e3þ t4

e4

� �ð6bÞ

where t1 (t2) are the thickness of upper (lower) gate oxide, t3 is thechannel thickness and t4 is the thickness of buried oxide region asgiven in Fig. 1.

V fb ¼ Um � vs þEg

2þ /c

� �ð6cÞ

where Vfb is the flat band voltage, vs is the electron affinity, Um isthe metal gate work function and Vsub is the substrate voltage.

3.2. Two-dimensional potential analysis

The 2D, temperature dependent electrostatic potential/Sch3(x, y) in the channel region is given by:

/Sch3ðx; yÞ ¼ A3½sinhðknðL� xÞÞ�

sinhðknLÞ sinðknðt1 þ t2 þ t3 � yÞ þ b3Þ

þ B3½sinhðknðxÞÞ�

sinhðknLÞ sinðknðt1 þ t2 þ t3 � yÞ þ b3Þ ð7aÞ

Table 1One dimensional coefficient used in analytical model in various regions of the ISESONstructure.

C11 ¼ e3e1ðK1t3Þ þ e5

e1ðK2t5Þ C12 ¼ Vgs � V fb � ½e3

e1ðK1t3Þ þ e5

e1ðK2t5Þ�t1

C21 ¼ e3e2ðK1t3Þ þ e5

e2ðK2t5Þ C22 ¼ Vgs � V fb � e3

e2ðK1t3Þ þ e5

e2ðK2t5Þ

h ie2e1

tt þ t2

h iC31 ¼ e5

e3ðK2t5Þ C32 ¼ e5

e4ðK2t5Þt4 þ K2

2 t25 þ V sub

C41 ¼ e5e4

K2t5 C42 ¼ qN52e5

t25 þ C51t5 þ V sub

C51 = 0 C52 = Vsub

The constant A3 and B3 are calculated using orthogonality of theFourier series at the side walls of the channel region using standardboundary condition given in Fig. 1. Hence the simplified expressionfor the coefficient A3 (which is temperature dependent) is given by:

A3 ¼bchR tþt2þt3

t1þt2½sinðknðt1 þ t2 þ t3 � yÞ þ b3Þ�

2 ð7bÞ

bch ¼ cosðb3ÞVbi � C32

knþ qN3

e3k3n

" #þ cosðknt3

þ b3ÞqN3t2

3

2e3kn� qN3

k3n

þ C31t3 þ C32 � Vbi

kn

" #

þ C31

k2n

" #½sinðb3Þ � sinðknt3 þ b3Þ� � sinðknt3 þ b3Þ

qN3t3

e3k2n

þ cosðknXj þ b3ÞVbi �ups

kn

� �þ ½sinðb3Þ � sinðknXj

þ b3Þ�Vbi �ups

k2nXj

" #ð7cÞ

where ups and upd are derived by using depletion approximationand the continuity requirement of the electric flux density, atx = 0 and x = L [26], Xj is the height of the side pillars and kn ¼ np

kn,

where kn is the characteristics length calculated by using the stan-dard boundary conditions of electric field and potential at the inter-faces of different regions.b3 is given by:

b3 ¼ a tane3

e4

tanðknt4Þ þ e4e5ðtanðknt5 þ pÞÞ

1� tanðknt4Þ e4e5ðtanðknt5 þ pÞÞ

" #" #ð7dÞ

Similarly B3 can be calculated by replacing Vbi with Vbi + Vds and ups

with upd in Eqs. (7b) and (7c).

3.3. Sub-threshold drain current model

Drain current can be modeled in the sub-threshold region byusing the diffusion component of current in the channel regionand is given by:

Ids ¼lWnikT 1� exp �qVds

kT

� �� �R L

0

R t1þt2þt3t1þt2

exp �/F3ðx; yÞð Þdydxð8Þ

where W is the channel width and l is the temperature dependentmobility of the charge carriers given by:

l ¼ 88T

300

� ��0:57

þ1252ð T

300 Þ�2:33

1þ NA

1:432�1017ð T300Þ

2:546

ð9Þ

The threshold voltage (Vth) is then determined as the gate voltage atthe point where the drain current (Ids) reaches 10�7 (W/L) A.

3.3.1. Sub-threshold slope modelThe sub-threshold slope in gate stack ISESON MOSFET can be

expressed as:

S ¼ lnð10Þ dVgs

d lnðIdsÞ¼ Ids lnð10Þ dðIdsÞ

dVgs

� ��1

¼ lnð10ÞKTq

dð/F3ÞdVgs

� ��1

ð10Þ

where /F3 is the channel potential.

V. Kumari et al. / Microelectronics Reliability 52 (2012) 974–983 977

3.4. Drain current model in linear regime

This section describes the drain current model in linear regionusing simple charge control model under gradual channel approx-imation for a gate stacked ISESON MOSFET. The drain current canbe written as:

IdsLinear ¼lWðCoxÞ Vgs � V th

Vds � 0:5aoV2

ds

� �1þ Vds

LEc

� �L

ð11Þ

where Cox is the gate capacitance given by Cox ¼ e2toxeff

: toxeff is theeffective oxide thickness and ao ¼ 1þ e5

t5Coxwhich accounts for the

body effect and DIBL. Ec ¼ Vsatl is the critical temperature dependent

electric field when the traveling electron reaches saturation velocity(Vsat).

(a) (b)

(d) (e)

(g) (h)

Fig. 2. Potential distribution along the channel for different temperatures (a) for T = 300T = 300 K, (e) T = 400 K, (f) T = 500 K; for L = 90 nm, Vds = 0.1 V, e1 = 3.9 (SiO2), Xe = 5 nmtransfer characteristics for (g) for T = 300 K, Vds = 0.1 V, (h) for T = 500 K, Vds = 0.1 V, (i)quantum model (symbols), analytical (line) and simulated with quantum model (doted linUm = 4.77 eV, N3 = 2�1017 cm-3.

3.5. Drain current model in saturation regime

Drain current equation incorporating channel length modula-tion (CLM) and velocity overshoot effect is given as:

Idssat ¼lWðCoxÞ Vgs � V th

Vdsat � 0:5aoV2

dsat

� �1þ Vdsat

ðL�LcÞEcþhEcðL�LcÞ Vds�Vdsatð Þ

� �ðL� LcÞ

ð12Þ

where

h ¼fð c

l2Þ 1þ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1þ ðVds�Vdsat

lEcÞ2

qh iffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1þ Vds�Vdsat

lEc

� �2r

� f cl2

� �Vds � Vdsatð Þ

ð13aÞ

Lc is the velocity saturation region due to channel length mod-ulation (CLM) given as:

(c)

(f)

(i)

K, (b) for T = 400 K and (c) for T = 500 K, Variation of drain current with Vgs for (d), Tst = 10 nm, t3 = t4 = 20 nm, Um = 4.77 eV, Vgs = 0 V, N3 = 2�1017 cm-3; Variation ofDrain current variation with Vds for T = 500 K and Vgs = 1.0 V; simulated withoute) for L = 32 nm, e1 = 3.9 (SiO2), Xe = 5 nm, Tst = 10 nm, t3 = t4 = 10 nm, t1 = t2 = 1 nm,

978 V. Kumari et al. / Microelectronics Reliability 52 (2012) 974–983

Lc ¼ l lnVds � Vdsat

lEcþ Em

Ec

� �ð13bÞ

Em is the maximum electric field given by:

Em ¼ Ec

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1þ Vds � Vdsat

lEc

� �2" #vuut ð13cÞ

l ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffie3

e2toxeff t3ð Þ

rð13dÞ

Vdsat is the drain saturation voltage given as.

Vdsat ¼ EcL �1�

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1þ 2

Vgs � V th

aoLEc

s" #ð13eÞ

where f and c has been added (fitting parameter) in the constantterm c

l2to adjust the effective saturation field [27].

4. Results and discussion

Fig. 2a–c shows the variation of surface potential (along thechannel) at different operating temperature. As the temperature in-creases, the minimum surface potential decreases (16% @ T = 400 Kand 28% @ T = 500 K) as shown in Fig. 2b and c which leads to theincrease in the threshold voltage. Fig. 2d–h shows the variation ofthe drain current with gate to source voltage (Vgs) for different oper-ating temperatures for channel length down to 32 nm. Fig. 2g–ishows (analytical and simulated) the variation of transfer and draincharacteristics respectively with and without including quantummechanical effect. The close proximity between analytical and sim-ulated data validates the analytical results for channel length downto 32 nm. However, the QMEs are significant for channel length be-low 10 nm and thickness less than 5 nm [31,32].

(a)

(b)

Fig. 3. Variation of drain current with drain to source voltage (Vds) for different temperlength at T = 300 K; for L = 90 nm, Vgs = 1.0 V, e1 = 3.9 (SiO2), Xe = 5 nm, Tst = 10 nm, t3 = t

Fig. 3 shows the variation of the drain current with drain tosource voltage (Vds) for ISESON MOSFET. As the temperature in-creases, lattice scattering dominates in the channel region andthereby mobility reduces which leads to reduction of drain current.The reduction in threshold voltage with temperature (due toenhancement in intrinsic carrier concentration) enhances the draincurrent which results in degradation in off current (Ioff) andenhancement in sub threshold slope (S), whereas the reductionin carrier mobility leads to the suppression of on state current(Ion). The point at which these two phenomenon balances out,drain current shows minimum variation with temperature whichis known as the zero temperature coefficient (ZTC) bias pointi.e.0.8 V. As temperature increases from 300 K to 500 K, Ioff changesfrom 0.12pA @ T = 300 K to 95.8pA @ T = 400 K, and 5220pA @T = 500 K. As channel length reduces from 90 nm to 65 nm, thedrain current increases due to channel length modulation (CLM)effect which can be clearly observed in Fig. 3d but the change indrain current with temperature is not so significant as observedfrom Fig. 3a–c which shows immunity of ISE-SON against temper-ature variation.

Fig. 4 shows the variation of the drain current with gate tosource voltage (Vgs) for different channel thickness and at differentbias temperatures. Reduction in channel thickness from 20 nm to10 nm leads to suppression of off state current (86%), along withthe reduction in sub threshold slope. As the channel thickness in-creases, gate controllability over the channel weakens and henceresults in the enhancement in sub-threshold slope (S) of the deviceand degrades the switching characteristics of the device.

Fig. 5 shows the variation of drain current with gate to sourcevoltage for different permittivity of buried oxide and different biastemperatures. As the permittivity of buried oxide decreases (fromSiO2 to Air) the electrostatic coupling between the channel andthe substrate decreases since air provide better isolation for chan-nel from substrate that leads to reduction in the sub threshold

(c)

(d)

atures (a) for T = 300 K, (b) for T = 400 K (c) T = 500 K, and (d) for different channel4 = 20 nm, Um = 4.77 eV, N3 = 2 � 1017 cm�3.

Fig. 4. Effect of channel thickness (t3) variation on drain current at differenttemperatures: for L = 90 nm, Vds = 0.1 V, e1 = 3.9 (SiO2), Xe = 5 nm, Tst = 10 nm, Um =4.77 eV, N3 = 2 � 1017 cm�3.

Fig. 5. Variation of drain current with gate to source voltage for different dielectricpermittivity buried oxide (e4) at different temperatures: for L = 90 nm, Vds = 0.1 V,e1 = 3.9 (SiO2), Xe = 5 nm, Tst = 10 nm, t3 = t4 = 20 nm, Um = 4.77 eV, N3 = 2 � 1017

cm�3.

Fig. 6. Effect of channel length variation on drain current at different temperatures:Vds = 0.1 V, e1 = 3.9 (SiO2), Xe = 5 nm, Tst = 10 nm, t3 = t4 = 20 nm, Um = 4.77 eV, N3 =2 � 1017 cm�3.

V. Kumari et al. / Microelectronics Reliability 52 (2012) 974–983 979

slope. It is also clear from the Fig. 5 that the sub-threshold slopedecreases when SiO2 is replaced with buried oxide. As e4 increasesfrom 1.0 to 3.9 (i.e. Air to SiO2), the change in Ioff with temperatureat e4 = 3.9 (SiO2) i.e. 83% is higher in comparison to the change ob-served at e4 = 1 (Air) i.e. 56%. This is due to the fact that the SONlayer does not extend under the source and drain regions andhence provide better heat dissipation than SOI [15].

Fig. 6 shows the variation of drain current with gate to sourcevoltage for different gate length at different operating tempera-tures. As channel length decreases to 65 nm, threshold voltage de-creases and sub-threshold slope increases i.e. the influence of drainfield on the source side increases that leads to reduction in the bar-rier potential for the charge carriers in the channel region at sourceside and therefore ZTC point increases from 0.8 V to 0.85 V but thechange in ZTC point is very small.

Table 2 shows comparison of threshold voltage (Vth) and sub-threshold slope (S) and DIBL at different operating temperatures.

As temperature increases, threshold voltage decreases due to in-crease in carrier concentration in the channel region. At high tem-peratures SCEs are more pronounced due to change in carrier’smobility that leads to the degradation of sub-threshold slope. Asthe permittivity of upper gate oxide increases, the gate controlla-bility over the channel increases and hence lead to suppressionin threshold voltage and sub-threshold slope (S). However, it canbe clearly observed that, change in sub threshold slope with (Vds)is negligible in ISESON MOSFET due to presence of side oxide pil-lars that can effectively suppress the field penetration from drainto source side.

Fig. 7 compares the DIBL of three devices under considerationoptimized to have same threshold voltage i.e. 0.25 V @ Vds = 0.5 Vby tuning the metal gate work function. It can be clearly observedfrom the Fig. 7 that the change in DIBL with temperature is small incase of ISESON as compared to ISE and SON MOSFET. This is due tothe fact that the influence of drain bias on the channel region issuppressed effectively due to the presence of insulating layers thatcuts off the path of leakage current.

Fig. 8a shows the circuit diagram of NMOS inverter in which CL

is the load capacitance and Rs is the source resistance which is usedto pull the output to high value when input is low. Fig. 8b showsthe gain of inverter for different architectures. The inverter gainis calculated by the change in output voltage corresponding tochange in input voltage. According to Fig. 8b, gain of ISESON archi-tecture is higher as compared to SON and ISE. The sharper peak ofthe curve signifies that small change in input voltage causes largechange in output voltage. Due to the high gain in transition regionin ISESON, it can also be used for analog amplifiers. As temperatureincreases, peak of the inverter gain shift to lower values of inputvoltage. Further, it can be observed that even at higher tempera-ture i.e. T = 500 K, ISESON performance in terms of inverter gainis superior than other device architectures.

Fig. 9 compares the NMOS inverter transfer characteristics andsupply current at different temperatures for ISESON, SON and ISErespectively. Inverter quality is often measured using the VoltageTransfer Curve (VTC), which is a plot of output voltage (Vout) versusinput (Vin). Ideally, the Voltage Transfer Curve (VTC) appears as aninverted step-function and this would indicate precise switchingbetween on and off, but in real devices, a gradual transition regionexists. The VTC indicates that for low input voltage, the circuit out-put is high; for high input, the output tapers off towards 0 volts.

Table 2Threshold voltage and sub-threshold slope of gate stack ISESON MOSFET with different temperatures and upper gate oxide permittivity; L = 90 nm, Xe = 5 nm, Tst = 10 nm,t3 = t4 = 20 nm, Um = 4.77 eV, N3 = 2 � 1017 cm�3.

Threshold voltage Vth (V) Sub-threshold slope (mV/decade)

Vds = 0.1 V Vds = 0.5 V Vds = 0.1 V Vds = 0.5 V

Sim. Ana. Sim. Ana. Sim. Ana. Sim. Ana.

e1 = 3.9 T = 300 K 0.500 0.529 0.460 0.500 71.48 75.79 71.90 77.11T = 400 K 0.400 0.420 0.360 0.385 97.03 103.47 97.30 104.80T = 500 K 0.285 0.287 0.240 0.250 124.30 131.30 124.60 132.35

e1 = 25 T = 300 K 0.440 0.490 0.426 0.478 65.97 69.47 66.15 70.10T = 400 K 0.350 0.390 0.333 0.373 89.24 94.59 89.31 95.24T = 500 K 0.254 0.274 0.232 0.250 113.36 120.0 113.94 120.56

0

100

200

300

400

ISESON ISE SON

DIB

L (

mV

/V)

T=300K

T=400K

17%

38%

27%

Fig. 7. Comparison of DIBL (simulated) between three devices at differenttemperatures for L = 65 nm; e1 = 3.9 (SiO2), Xe = 5 nm, Tst = 10 nm, t3 = t4 = 20 nm,N3 = 2 � 1017 m�3.

980 V. Kumari et al. / Microelectronics Reliability 52 (2012) 974–983

The slope of this transition region is a measure of quality; steep(close to �infinity) slope yield precise switching. It can be clearlyobserved from the figure that transfer characteristics are more lin-ear for ISESON MOSFET as compared to ISE and SON MOSFET. Themaximum current through the resistance remains same for all thedevices and at all temperatures but the degradation in transfer

(b)(a)

Fig. 8. (a) Circuit diagram for NMOS inverter where Vdd is the source voltage and Vin isdifferent operating temperatures; for L = 32 nm, e1 = 3.9 (SiO2), Xe = 5 nm, Tst = 10 nm, t3

characteristics is more pronounced in ISE MOSFET (i.e. 32%) fol-lowed by SON (i.e. 19%) and ISESON MOSFET (i.e. 13%) with tem-perature. Fig. 9d–f compares the effect of on resistance (at thesource terminal) on the transfer characteristics for ISESON, SONand ISE respectively. As Rs increases, VTC curve becomes moreideal (i.e. the slope of the curve decreases) and the current throughthe resistance decreases. A decreasing level for logic zero with anincreasing on resistance (Rs) is more prominent in case ISE MOSFET(45%) as compared to SON (42%) and ISESON (40%) MOSFET. Fig. 10investigates the dynamic performance of NMOS inverter by usingtransient analysis which is used to measure the propagation delayof the device at two different operating temperatures. As the tem-peratures increase, threshold voltage decreases due to reduction inelectron mobility expected which is equivalent to an increase inon-resistance (Rs) of the NMOS circuit and hence leads to reductionin maximum output (Vout) voltage. Only a slight dependence ofoutput voltage of about 16% on temperature is observed in caseof ISESON MOSFET as compared to SON (22%) and ISE (35%) NMOSinverter.

According to Fig. 11a, gm increases with drain current for fix va-lue of Vgs and Vds and it is maximum for SON followed by ISESONand ISE architecture. Furthermore, the impact of temperature var-iation on trans-conductance in ISESON is 46% however it is 50% inSON and 62% in ISE which is due to reduce electrostatic couplingbetween drain and source. The impact of temperature variationon output resistance (Rout) is shown in Fig. 11b under drain biasabove ZTC point i.e. Vgs = 1.0 V. As temperature increases, drain-conductance increases leading to reduction in Rout. The percentagereduction in Rout with operating temperature in ISESON is 9.7%

the input supply voltage. (b) Variation of inverter gain for different architectures at= t4 = 10 nm Rs = 50 Kohm.

(a) (b) (c)

(d) (e) (f)

Fig. 9. Voltage transfer characteristics and supply current for NMOS inverter at different temperatures (a) for ISESON MOSFET, (b) SON MOSFET and (c) ISE MOSFET (d) fordifferent values of Rs for ISESON (e) for different values of Rs for SON (f) for different values of Rs for ISE; for L = 32 nm, e1 = 3.9 (SiO2), Xe = 5 nm, Tst = 10 nm, t3 = t4 = 10 nmRs = 50 Kohm.

Fig. 10. Transient analysis of different architectures at different temperatures forL = 32 nm, e1 = 3.9 (SiO2), Xe = 5 nm, Tst = 10 nm, t3 = t4 = 10 nm.

V. Kumari et al. / Microelectronics Reliability 52 (2012) 974–983 981

however it is 14.3% in SON and 29.8% in ISE architecture therebyshowing immunity against temperature variation even at shortergate length i.e. 32 nm.

Table 3 shows the electrical parameters like device efficiency(gm/Ids), device gain (gm/gd), early voltage (Vea) and output resis-tance (Rout) of ISESON, ISE and SON MOSFET for different lengthsand operating temperature up to 600 K. For low voltage low poweranalog circuit applications early voltage expressed as Ids/gd (i.e.drain current to drain conductance ratio) should be as high as pos-

sible. The early voltage shows the dependence of drain conductanceon drain current and is found to be maximum for ISESON MOSFET.As temperature increases, early voltage increases for all the devicesunder consideration and the percentage change in early voltage forISESON is 29% for ISE 64% and for SON 42%. This validates the immu-nity of ISESON against temperature variation. As the channel lengthis reduced from 90 nm to 65 nm, early voltage (Vea) increases due toincrease in charge sharing between source and drain region but thepercentage change in ISESON is still lower i.e. 31%, 68% in ISE and33% in SON. Further as channel length decreases, the influence ofdrain bias on channel region increases which leads to the enhance-ment in drain-conductance and hence early voltage decreases.Intrinsic gain (gm/gd) decreases with increase in temperature dueto strong dependence of trans-conductance on the operating tem-perature. The percentage change in gm/gd with temperature is34%, 36% and 38% for ISESON, ISE and SON MOSFET respectively. Re-sults also show that intrinsic gain is higher for ISESON MOSFET incomparison to ISE and SON MOSFET due to reduced electrostaticcoupling between source/drain and substrate regions. The changein output resistance (Rout) with temperature (above room tempera-ture) is negligible for all devices under considerations. ISE MOSFETpresents lowest Rout in comparison with the SON and ISESON MOS-FET. The gm/Ids ratio can be viewed as the quality factor of the de-vice. For more efficient devices, the device efficiency should be ashigh as possible because trans-conductance represents powerdelivered by the device and drain current represents power dissi-pated to obtain that much amplification. It can be clearly observedfrom Table 3 that device efficiency of ISESON MOSFET is higher incomparison with the other devices under consideration. As temper-ature increases, device efficiency decreases (30% in ISESON, 32% in

(a) (b)

Fig. 11. Simulated variation of (a) trans-conductance with drain current at different temperature (b) output resistance with drain bias for above ZTC point (i.e. Vgs = 1.0 V) atdifferent operating temperature; solid symbols at T = 500 K and hollow symbols at T = 300 K for L = 32 nm, e1 = 3.9 (SiO2), Xe = 5 nm, Tst = 10 nm, t3 = t4 = 10 nm.

Table 3Electrical parameters (simulated) for ISESON, ISE and SON MOSFET at different temperatures and channel length; for e1 = 3.9 (SiO2), Xe = 5 nm, Tst = 10 nm, t3 = t4 = 20 nm,Um = 4.77 eV, N3 = 2 � 1017 cm�3, Vgs = 0.5 V, Vds = 0.5 V.

(K) L = 90 nm L = 65 nm

gmmax (mS/lm) gm/Ids (V�1) gm/gd Vea (V) Rout (KX) gmmax (mS/ lm) gm/Ids (V�1) gm/gd Vea (V) Rout (KX)

300 ISESON 0.426 36.00 4.40 3.00 130.0 0.514 24.77 2.90 2.11 60.00SON 0.472 35.43 4.33 2.24 90.69 0.556 23.84 2.69 1.28 23.58ISE 0.408 34.92 4.10 0.51 24.0 0.494 23.60 2.63 0.31 12.77

400 ISESON 0.324 16.00 1.70 4.40 100.44 0.381 12.50 1.33 3.01 36.35SON 0.343 15.62 1.60 3.36 67.85 0.385 11.68 1.23 2.35 22.49ISE 0.254 14.82 1.53 1.50 22.05 0.301 12.14 1.20 1.49 11.77

500 ISESON 0.234 8.84 0.87 5.60 87.56 0.285 7.50 0.75 3.81 35.90SON 0.259 8.78 0.61 4.33 60.00 0.306 7.38 0.56 2.94 22.35ISE 0.154 6.18 0.57 1.97 22.03 0.225 7.10 0.47 1.80 10.97

600 ISESON 0.179 5.68 0.55 6.65 81.57 0.218 4.90 0.49 4.50 35.37SON 0.199 5.51 0.47 5.13 56.61 0.250 4.89 0.31 3.43 21.05ISE 0.109 3.94 0.39 2.37 21.95 0.199 4.85 0.30 2.10 9.00

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ISE and 33% in SON) due to reduction in carrier mobility. With thereduction in channel length, trans-conductance increases but theimprovement in drain current at lower channel length is higherthan the trans-conductance and hence gm/Ids ratio (i.e. device effi-ciency) decreases. The effect of temperature variation on gmmax

for different channel lengths is also highlighted in Table 3. Thegmmax is maximum for SON followed by ISESON and ISE architecturedue to the increased effective channel length in ISESON (due topresence of side pillars) as compared to SON architecture. As thetemperature increases, gmmax decreases for all devices howeverthe percentage reduction in gmmax is less in ISESON (24%) as com-pared to SON (27%) and ISE (37%) architecture. As the channellength decreases, gmmax increases with 17% enhancement in ISE-SON, 15% in SON and 16% in ISE. The percentage change in gmmax

with temperature at shorter channel length i.e. 65 nm is less in ISE-SON (25%) as compared to SON (30%) and ISE (37%) due to the re-duced CLM effect because in ISESON architecture channel regionis completely surrounded by insulator except for the uppermostpat at which inversion layer is formed.

5. Conclusion

A temperature dependent drain current analytical model forgate stack ISESON has been presented and results are verified with

the simulation results obtained by ATLAS 3D device simulator forchannel length down to 32 nm. It can be observed that SCEs aremore pronounced at high temperature. However the effect of tem-perature variation can be reduce by using gate stack configuration.ISESON MOSFET shows better immunity from temperature varia-tion as compared to other devices in terms of device efficiency, de-vice gain, early voltage and output resistance hence can be used forhigh temperature applications. This paper also discusses digitalperformance of the devices by investigating the NMOS inverterperformance for wide range of temperature (300–500 K). Henceit can be easily concluded that the ISESON MOSFET is a better can-didate for digital as well as for analog applications as compared toISE and SON MOSFET for wide ranges of temperature.

Acknowledgment

The authors would like to thank University Grant commission(UGC) for providing the necessary financial support (Under theProject (F. No. 36-258/2008 (SR))) to carry out this research work.

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