tektronix confidential1 signal integrity analysis of gigabit interconnects olie kreidler tektronix,...

Tektronix Confidential1

Signal Integrity Analysisof Gigabit Interconnects

Olie Kreidler Tektronix, Inc.


Signal Integrity (SI): Digital Becomes Analog

“At high frequencies … crosstalk and signal reflections can be perceived as logic triggers, and can be responsible for erroneous signal patterns”

– EE Times, April 17, 1998, Special Section on Interconnects


Industry Trends and Issues

On-going trends and issues– Trends: faster rise times, clock frequencies, increasing

interconnect complexity– Requirement: increasing need for signal integrity analysis and

SPICE / IBIS interconnect modeling

New trends and requirements– Trends:

S-parameters and eye diagrams are becoming part of compliance testing for passive PHY

All standards currently are differential and serial– Requirements

Eye diagram and S-parameter compliance testing must be performed in differential mode

Frequency dependent losses need to be modeled


Outline

Interconnect Measurement Accuracy Issues TDR/T and VNA Measurement Basics

App Note: “TDR and VNA Measurement Primer”– Impedance Measurements and IConnect® True Impedance

Profile – Time Domain S-parameter Measurements– Eye Diagram Measurements – TDR Probing and Fixturing

2007/06/10 Confidential V1.15

High-Speed Serial Data Link Analysis The Measurement Challenge - A Closed Eye

An “Open Eye” at the Transmitter

a “Closed Eye” at the Receiver

How to measure this eye?

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The risetime of the channel is relatively slow compared to the very fast 1’st channel. i.e. modern channel’s risetime is quite longer than the UI, thus the eye blures and ‘ISI’-s itself.

http://pdfserv.maxim-ic.com/en/an/4hfdn27.pdf



High-Speed Serial Data Link Analysis The Serial Data’s Solution to a Closed Eye



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Equalize it!

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EQ.

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Rx

Equalization is the answer for the digital receiver. The eye opens at the input of the receiver, the receiver can decode the signal.



High-Speed Serial Data Link Analysis What should the Measurement do? - simple:do what your Tx/Rx does: implement equalization!



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Equalize it!

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Equalization is the answer to the eSerial receiver, so SW-implemented Equalization on the scope is also the answer to T&M.

-opens the eye for display (the scope-‘receiver’)

-Lets the user view ‘the inside’ of the Receiver This is now in your scope



Tek Solution

DSA8200 with the TDR Module

80E04 reflected rise time: – 35 ps

80E10 reflected rise time– 12ps / 15ps

8 acquisition channels– 8-port TDR– 4-port True Differential TDR

Continuously stabilized rho and impedance waveforms

All standard measurements available on rho and impedance waveforms

TDR Overview - Typical System

Incident Step

50

Step Generator

Reflections

Sampler

t = 050

Incident Step

Incident

Reflection

Test deviceTest device

Probe

Impedance reference

TDR Waveform Characteristics

TDR systems observe the superposition of incident and reflected signals at source

Time separation t1-t0 assures ability to discern difference

Timet0 t1

incidentV

reflectedV

TDR Rho Units Definition

Time

+ 1

0

- 1

t0 t1

0at 0 and ZZV

V

incident

reflected

Characteristic (Z = Z0)

Amplitude

incidentV

reflectedV

KCL Applied at Discontinuity Transmission lines support propagation with specific

characteristic impedance Z

Reflected and forward propagating signals will be such that i = 0 is satisfied at discontinuity

Can easily solve for Z knowing , Z0, and KCL for lumped circuits

StepSource

Forward

(Z = Z0)

Incident

ReflectedDiscontinui

ty

Z0

Solution for Z Units

0

0

ZZ

ZZ

1

10ZZ

Where– Z0 is the known reference impedance– the sampling oscilloscopedirectly measures – Z is the calculated test device impedance

Note textbooks usually show reversed expression

TDR Waveforms - Simple Cases

Waveforms with Open, Short and 50 terminations

AmplitudeOpen (Z =)

(Z = 50)

Short (Z = 0)

Time

reflected =+1

+ 1

0

- 1

t0 t1

incident=+1 reflected =-1


TDS Measurement Basics

TDR Block Diagram

Z termination

C ab le: Z 0, tdR source

TD

R O

scill

osc

op

e F

ron

t P

an

el

R source = 50 Z 0 = 50 then V inc ident = ½ V

V inc identV re flected

V

D U T: Z D U T

½ V

0

Z load > Z 0

Z load < Z 0

V •Z load / (Z load + Z 0)V

½ V

0

O pen c ircu it

Short c irc u it

M atched load


TDR Measurements Basics

Inductance and Capacitance Analysis

L-C d isco ntinuity

C -L -C d iscontinuity

Z 0Z 0

Z 0Z 0

S hunt C d isco ntinuity

S eries L d isco ntinui ty

Z 0 Z 0

Z 0Z 0

½ V

0

½ V

0

½ V

0

½ V

0


Measurement Tools: Z-line

Z-line-Based Measurements

2

12

1t

t

dttZL )( 2

1

1

2

1t

t

dttZ

C)(

t2

t1

t2

t1



TDR Rise Time and Resolution

Accepted rule of thumb for resolving two discontinuities

80E04 TDR rise time: 30-40ps at the end of the cable, probe, fixture– Base 1/2trise resolution: 15-20ps– 0.1”-0.12” in FR4

80E10 TDR rise time: 12-16ps at the end of the cable, probe, fixture– Base 1/2trise resolution: 6-8ps– 0.04”-0.048” in FR4

tseparateTo resolve a1 and a2 as

separate discontinuities:tseparate > tTDR_risetime /2 a1 a2




More real case: resolving a single discontinuity

Going beyond the TDR resolution and risetime: relative techniques– Signal integrity modeling – JEDEC standard– Failure analysis – golden device comparisons

tsingle a1 is not resolved iftsingle << tTDR_risetime a1




If 30-40 ps (or 12 ps) fast TDR rise time does not resolve it ….

How in the world a 80 ps signal rise time will????????????

Conclusion: for SI analysis, use the actual DUT rise time! (filter down the rise time, if necessary)



Differential TDR

Differential serial link analysis

Virtual ground plane

Even and odd mode measurements

C ab le: Z 0, tdR so urce

TD

R O

scill

osc

op

e F

ron

t Pa

ne

l

V inc ide ntV re flecte d

D U T: Z D U T

V

V

C ab le: Z 0, td

Virtual g round

R so urce



Good Measurement Practices

Perform calibration routines regularly

Minimum warm-up time 20 minutes

Maintain constant temperature in the lab and check the instrument t°

Zoom in on the DUT – but include all the DUT signature transitions (more to follow)

Use torque wrenches when mating SMA or other RF connectors


Time and Frequency Domains

VNA Block Diagram

VNA: Vector Network Analyzer

Similar diagram can be drawn for reverse measurements (port 2 to port 1)

Differential VNA: 4-port measurements

DUTV incident1 V transmitted2

V reflected1

Port 1

Port 2

Cable: Z 0, tdV

NA

Fro

nt P

anel

R source

Calibrationprocedures:- SOLT- TRL- LRRM

V



Equations for TDR vs. VNA

))(()(11 tFFTLimitedDurationfS

0)(

0)(

1

111 ZZ

ZZ

V

VS

DUTinput

DUTinput

incident

reflected

11

110)( 1

1

S

SZZ DUTinput

0

0

ZZ

ZZ

V

V

load

load

incident

reflected

1

10ZZDUTTDR

VNA




TDR vs. VNA

TDNA (Time Domain Network Analysis)– Based on TDR/T measurements:– Transient– Broadband– More intuitive for a digital designer– Dynamic range: about 50-60dB– Less expensive

FDNA (Frequency Domain Network Analysis)– Based on VNA measurements:– Steady-state measurements– Narrow-band– More intuitive for microwave/RF designer– More expensive– Higher dynamic range (up to 110 dB)



Time or Frequency Domain?

SI measurements do not require high dynamic range

Compliance testing does not require high DR– About –10 dB for insertion loss– -25 to –35 dB for return loss– Higher for frequency domain crosstalk

VHIGH

VLOW

1% (-40dB) Xtalk

-40dB equals1% in time

domain


Impedance Accuracy

TDR Basic Equations

V inc ident

0

V m easured =V inc ident + V reflec ted

2 td

measuredincident

measured

reflectedincident

reflectedincidentDUT VV

VZ

VV

VVZZZ

21

1000

0

0

ZZ

ZZVV

DUT

DUTincidentreflected

0

0

ZZ

ZZ

V

V

load

load

incident

reflected


Impedance Accuracy

TDR Multiple Reflection Effects

Issue: impedance accuracy suffers due to signal re-reflection inside the DUT

Z0 Z1 Z2 Z3 Z4

Vtransmitted1

Vreflected1 Vreflected2

t0

Time Direction of propagation


Impedance AccuracyIConnect Computation of the True Impedance Profile

nincident

incident

incident

incident

nnnnreflected

reflected

reflected

reflected

V

V

V

V

kkkk

kkk

kk

k

V

V

V

V

3

2

1

121

123

12

1

3

2

1

0

0

000

000

31222111

22

2132

22

213

2112212

111

)( incidentincidentincidentreflected

incidentincidentreflected

incidentreflected

VVtVtttV

VVtV

VV


Impedance Accuracy

Board Trace IConnect® Z-line

Multiple reflections in TDR waveform

Scope reads here about 44 Ohm instead of 50 Ohm


Impedance Accuracy

Board Trace IConnect® Z-line

Accurate impedanceprofile in IConnect®


Impedance Accuracy

Package Trace IConnect® Z-line

Raw TDR: confusing multiple reflections

Impedance profile in IConnect®:Exact failure location,improved resolution


Impedance Accuracy

IConnect® Software Z-line Algorithm

TDR measurements suffer from multiple reflections– No limited to TDR, also in TD in VNA

IConnect removes multiple reflections– Ensures accurate impedance measurements in multi-impedance

DUT– Direct and accurate readout of Z, td, L, C– Different and more accurate than Z readout in the scope

Attention!:– Data noise may interfere with accuracy

Use scope averaging Use software noise filtering

– Line loss is extracted separately


Frequency Dependent S-parameters

Why S-parameters

Compliance testing– Insertion loss (around 6-10 dB)– Return loss (around 20-30 dB)– Frequency domain crosstalk

Link performance evaluation and simulation– Simulate S-parameters directly


Frequency Dependent S-parameters Equations for TDR vs. VNA

0)(

0)(

1

111 ZZ

ZZ

V

VS

DUTinput

DUTinput

incident

reflected

11

110)( 1

1

S

SZZ DUTinput

0

0

ZZ

ZZ

V

V

load

load

incident

reflected

1

10ZZDUTTDR

VNA





Single-ended TDR

22222121

12121111

TDRSTDTS

TDTSTDRS

TDR stimulus on channel 2,response on channel 2






Correct Data Acquisition

DUT waveform to settle to steady DC

level



Return Loss = TDR

Measure TDR, compute S11 (return loss) in IConnect

What is wrong with this RL picture?



Insertion Loss = TDT

Measure TDT, compute S21 (insertion loss) in IConnect

Test casefor loss extraction



Differential and Mixed S-parameters

2222212122222121

1212111112121111

2222212122222121

1212111112121111

cccccccccdcdcdcd

cccccccccdcdcdcd

dcdcdcdcdddddddd

dcdcdcdcdddddddd

TDRSTDTSTDTSTDTS

TDTSTDRSTDTSTDRS

TDRSTDRSTDRSTDTS

TDTSTDRSTDTSTDRS

Differential TDR stimulus,differential response

(most important)

Common mode TDR stimulus,common mode response

(less important)

Differential TDR stimulus,common mode response(useful in time domain for

EMI troubleshooting)

Common mode TDR stimulus,differential response

(useful in time domain for EMItroubleshooting)



Differential TDR = S11diff

Several InfiniBand traces of different length.

Differential return loss.

Demo of TDR and S parameter measurements


Additional Material




Power Plane Resonance

Resonances between planes

Observe plane impedance profile (Z-line)



Electrical Compliance Testing

Need fixture to interface to interconnects for compliance testing

Infiniband Connector

Reference thru Traces

DUT Connection Traces



VNA Fixture De-embedding

For VNA requires additional standard to de-embed properly

Insertion loss: fixture insertion loss must be subtracted from DUT insertion loss

Return loss: no way to de-embed without additional standards!– Fixture return loss ends up being lumped with the DUT return

loss– Can be a problem even with quality fixtures



VNA Real Fixture Limitation Example

With fixture, the cable assembly is failing the

spec!Fixture is failing the assembly with VNA

measurements

Spec: -10 dB at 1.25 GHz



TD-VNA Fixture De-embedding

Simplicity of calibration allows simple fixture de-embedding

Fixture de-embedded with TDNA, the assembly is passing

Spec: -10 dB at 1.25 GHz



Correlation with Network Analyzer




-25

-20

-15

-10

-5

0

FR

EQ

, Gh

z

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

VNA SDD11, dB

IConnect®S11.wfm(dBMag). NoTDR calibration




Insertion Loss VNA TDA ComparisonData courtesy Kieran Kelly, Samtec,Inc.

-12

-10

-8

-6

-4

-2

0

000.0E+0

1.0E+9 2.0E+9 3.0E+9 4.0E+9 5.0E+9 6.0E+9 7.0E+9 8.0E+9 9.0E+9 10.0E+9

Frequency (Hz)

IL (

dB

)

VNA

TDA



Correlation with Network Analyzer: 65 GHz

The TD-VNA bandwidth is directly related to TDR/T rise time

These data were measured using the PSPL Model 4022 and a 70 GHz sampler

S-parameters correlate to65 GHz

Courtesy: Kipp Schoen, Picosecond Pulse Labs

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

0 10 20 30 40 50 60

frequency (GHz)

S2

1 m

ag

na

tud

e (

dB

)

VNA S21

4022 S21

-60

-50

-40

-30

-20

-10

0

0 10 20 30 40 50 60

frequency (GHz)

S1

1 m

ag

na

tud

e (

dB

)VNA

4022



Calibrated Results: SOLT

Excellent correlation between TDNA and FDNA data

Dashed line – Tektronix 11801 with SOLT cal

Solid line – Agilent 8510 VNA



Noise Floor and Dynamic Range

To reduce noise floor:– Increase number of averages Navg– Increase number of points Npoints– Decrease acquisition window length (increase effective incident

power)



TD-VNA Incident Effective Power

The TD-VNA bandwidth directly related to the risetime of the TDR and TDT signals

-140

-120

-100

-80

-60

-40

-20

0

0 20 40 60 80 100

frequency (GHz)

ma

gn

atu

de

(d

B)

4022 10ps

54754A 25ps

4022 10 ps TDR 25 ps


Frequency Dependent S-parametersTD-VNA Dynamic Range (with PSPL Module)



IConnect Produces S-parameters

Differential, mixed mode and single ended

Insertion, return loss and frequency domain crosstalk

Performance with base DSA8200: 50-60 dB dynamic range (vs. 100 dB for VNA), 12 GHz bandwidth

Performance with 80E10 up to 50GHz bandwidth

Cost ½ of a comparable VNA solution

Intuitive, easy to use and more than adequate dynamic range for digital designers


TDT and IConnect Eye Diagram

Efficient S-parameters Testing in IConnect

Easy, quick, efficient S-parameter measurements and electrical compliance testing– Insertion, return loss, frequency dependent crosstalk– Excellent correlation with traditional VNA techniques– Cost-effective and quick

Minimal calibration required– Only reference at the end of the fixture– Easy fixture de-embedding



Why Eye Diagram in IConnect?

Eye Diagram for Interconnects– Specification mask testing– Not just communication standards, also for new serial link

standards

IConnect benefit: no pattern generator required for interconnect eye diagram analysis– De-embed deterministic / interconnect jitter– No active component jitter



Eye Diagram Degradation in Interconnects

Interconnect losses

Pattern-dependent, crosstalk induced jitter

Method to improve the eye– Equalization, pre-emphasis and de-emphasis– Other signal conditioning techniques

Only deterministic jitter exists in interconnects, no random component!



Eye Diagram Options

TDT easily gives the eye diagram degradation– Deterministic jitter only



New Eye Mask and Jitter Measurements



Why is TDT Based Eye Better?

Easy to de-embed fixture– The same improvement as for S-parameter

measurements!

No jitter from the pattern generator



Predicted and Measured Eye Diagrams

Pattern Generator Based

IConnect K28.5

IConnectPRBS 210-1




2^10-1 IConnect eye fromTDT measurement

2^10-1 pattern generator measurement

Data Courtesy FCI Electronics




MeasuredSimulated

MeasuredSimulated

1.5Gb/s (Gen 1)

6.0Gb/s (Gen 3)

MeasuredSimulated

3.0Gb/s (Gen 2)

Serial ATA data courtesy Molex, Inc.



Efficient Eye Diagram Testing in IConnect

Easy, quick, efficient eye diagram measurements and compliance testing– Excellent correlation with traditional pattern generator

techniques– Cost-effective and quick

Minimal calibration required– Only reference at the end of the fixture– Easy fixture de-embedding


Outline

Interconnect Measurement Accuracy Issues TDR/T Probing and Fixturing

App Note: “TDR Measurement Primer”App Note: “TDR Techniques for Characterization and Modeling of Electronic Packaging”Quick Guide:“Interconnect Probing Quick Guide”

Interconnect SPICE / IBIS Modeling and Model Validation


Probing and Fixturing

TDR Measurement Setup

TDR probe with signal and ground

connection

TDR oscilloscope



Probing and Fixturing Issues

Probing is the weakest link!

Start with a probe– 50 Ohm for TDR measurements – must be rugged and inexpensive– ensure stable repeatable contact– large pitch* means small bandwidth– variable pitch means poor repeatability– ensure sufficient compliance

* Pitch: center-to-center signal to ground pad spacing



Package and Connector Probing

Use a high-quality probe (and positioner) Need an interface adapter or fixture to probe Fixturing requirements

– Reproduce the real application environment– Ensure easy fixture de-embedding (reference short and open

structures may be needed)

P ackage

S igna l-G roundP robe

V ias topackage

leads

P C B providesground

connections

F ixtu regroundp lane

P C B provides groundconnections

P C B trace toconnector lead

F ixtu regroundp lane

Via to ground for reference m easurem ents

R eferenceshort and open

S igna l-G roundP robe

H igh-S peed

C onnector



Board Probing

Ensure good contact to a via – Difficult for a microwave probe– Use TDA’s QuickTDR™ probe– Probes also available from TDR

manufacturers

Ensure ground contacts near yoursignals

Variable pitch: a sad necessity– Available from from TDR manufacturers and probe

manufacturers (Cascade Microtech, ICM)– Measurements suffer from poor repeatability and decrease the

instrument usable bandwidth



Probing vs. Fixturing

Probing advantages: Maximum flexibility for multiple

device measurements

No fixture de-embedding required

But:

Requires DUT to have easily accessible contact areas

Positioning system may be expensive

Fixturing advantages: Evaluate the DUT in its

intended environment of use (example: package on a board)

Great flexibility for specific DUT

But: Difficult to change after the

fixture has been designed Must de-embed fixturing from

measurements

These approaches are complementary!

Fixturing is thinking ahead about how you will probe!


Outline

Interconnect Measurement Accuracy Issues– Impedance, S-parameters and eye diagram measurements and

compliance testing

Interconnect SPICE / IBIS Modeling and Model Validation– Z-line, lossy line, and automatic behavioral modeling


Outline

Interconnect Measurement Accuracy Issues

Interconnect SPICE / IBIS Modeling and Model Validation Measurement Based Interconnect Analysis– Behavioral Modeling: MeasureXtractor™ – Topological Modeling:

TDT and Lossy Line Modeling Impedance Profile (Z-line) Transmission Line Modeling L and C JEDEC computation

– Examples: Power Plane Analysis Backplanes and cable assemblies


Measurement-Based Link Design

How to Analyze System Signal Integrity?

App Note: “Signal Integrity Modeling of Gigabit Backplanes, Cables and Connectors Using TDR”

Is this similar to your application?

Tx

Daughtercard

Backplane

CableAssem bly

Board C onnector(s im plified

m odel)

Rx

Connector

Connector

Connector



Interconnect Measurement Based Design

Linearize the link input and termination for initial analysis

Daughtercard

Backplane

CableAssem bly

Board C onnector(s im plified

m odel)

Connector

Connector

Connector

Receiversim plified



Measurement Based Design Details

Impedance measurement => reflections

TDR/T or S-parameters => losses, jitter, eye diagram degradation– System losses is a result of losses in components– Eye diagram is a result of losses and crosstalk in

components


IConnect Modeling Methodology

Goals and Model Validity

Goal: accurately predict interconnect performance via simulations– Need an accurate SPICE /IBIS models

Model required range of validity is defined by the fast corner rise time of the driver– Equivalent bandwidth estimated as:

fbw=0.35 / trise or harmonics of clock

It may be desired to extend the required range of model validity beyond trise and fbw

– Have a confidence guard band



Modeling Technique: Behavioral

Behavioral Modeling: MeasureXtractor™– A universal, fully automatic, exact

modeling technique– Can use time or frequency domain data – Matches exactly both time and frequency response– Perfect for…

Connector, package or socket modeling Model for a characterization fixture for a connector, a package or a

cable Model for a daughtercard board When behavioral model is acceptable

– Can create large model for a large interconnect such as a backplane or cable assembly



Modeling Technique: Topological

Lossy line and coupled lossy line modeling– When need to predict losses and crosstalk

Large lossy backplanes and motherboards Cables and cable assemblies

Impedance profile (Z-line) models– When losses are small– Need to predict impedance reflections, crosstalk only

Small daughtercards, boards Electrically long connectors, packages



Modeling Technique: Topological

JEDEC technique for L and C computation– Industry standard technique for electrically short interconnects– Electrically short: trise >> tprop delay

– Packages, connectors, sockets

trise

tprop delay



Behavioral or Topological?

Behavioral Topological Measurement Requirements

Requires two-port or four-port measurements

Just TDR (reflection) is sufficient

Topology selection

Automatic, no user intervention

User-controlled (easy and intuitive from TDR measurements)

Extraction Automatic, no user intervention

User-driven; more labor intensive than behavioral

Type of models

“Black-box,” no internal changes allowed

Intuitive, easy “what-if” scenario analysis

Limitation for long interconnects

Large model for long interconnects (backplanes, cable assemblies)

Efficient model extraction processes exist for large interconnects



Methodology: Gbit Ethernet Example

Cable and Test cards: lossy line modeling

Launch, high-speed connector:Z-line modeling

Any piece can be modeled in MeasureXtractor™

Lumped pieces can be modeledwith JEDEC technique


TDR/T or VNA Measurements

Extracted interconnect, instrument source models

Direct link to simulators

Automatic comparison of simulation and measurement in IConnect waveform viewer

SPICE


Measurement Based Approach


Outline


Interconnect SPICE / IBIS Modeling and Model Validation Behavioral Modeling: MeasureXtractor™ – Topological Modeling:

TDT and Lossy Line Modeling Impedance Profile (Z-line) Transmission Line Modeling L and C JEDEC computation



Behavioral Modeling

MeasureXtractor™ Modeling

A fully automatic algorithm for conversion of VNA S-parameter or TDR/T data into SPICE or IBIS model– Passivity of the model guaranteed– Compact and efficient– Fully automated– Not an optimization– Behavioral models


Behavioral Modeling

Lack of Passivity Produces Oscillations

Instability is a very bad

thing!

TERASPEEDCONSULTING

GROUP

Slide

courtesy:


Behavioral Modeling

Sources of Passivity Issues

Insufficient attention to measurements or calibration– Interconnects do not amplify signals!– Even if individual measurements are passive, combined system

measurements can have amplification properties

Simulator extrapolation and interpolation based on model, not original measurement

Finite measurement acquisition window (in the limit, the data is infinite!)


Behavioral ModelingExample: Correlation of Measurement and Model

Exact correlation in time and frequency domains


Behavioral Modeling

Example: Model Listing

c33 34 gnd_ 7.10021e-016

r90 35 gnd_ 3622.1

c34 35 gnd_ -7.10021e-016

r91 36 37 176812

r92 36 gnd_ 57641.7

c35 36 gnd_ 7.15572e-016

r93 37 gnd_ 3932.13

c36 37 gnd_ -7.15572e-016

r94 38 gnd_ -2488.86

c37 38 gnd_ -3.07009e-015

r95 39 gnd_ 5982.67

c38 39 gnd_ -2.49077e-014

.ends

…

…

…

…

r14 port1 15 -1898.27

r15 port1 16 -971048

r16 port1 17 2103.52

r17 port1 18 15884.8

r18 port1 19 326913

r19 port1 20 6566.94

r20 port1 21 1508.55

r21 port1 22 -885.906

r22 port1 23 4789.5

r23 port1 24 2788.21

r24 port1 25 -14075.7

r25 port1 26 -18495.7

r26 port1 27 -1786.85

r27 port1 28 -27328.6

…

.subckt DUT port1 gnd_

r1 port1 2 -24977.9

r2 port1 3 23982.9

r3 port1 4 -12111

r4 port1 5 3124.2

r5 port1 6 -2348.66

r6 port1 7 14099.3

r7 port1 8 -4392.43

r8 port1 9 1444.76

r9 port1 10 1.1046e+007

r10 port1 11 -301858

r11 port1 12 3622.64

r12 port1 13 -1221.14

r13 port1 14 6965.14

…


Behavioral Modeling

MeasureXtractor™ Summary

Converts S-parameters or TDR/T data into an exact-match model

Passivity is guaranteed

If you can measure it, and want model it with little effort, use MeasureXtractor™!


Outline


Interconnect SPICE / IBIS Modeling and Model Validation Topological Modeling:

TDT and Lossy Line ModelingApp Note: “Practical Characterization of Lossy Transmission Lines Using TDR”

Impedance Profile (Z-line) Transmission Line Modeling L and C JEDEC computation



TDT and IConnect Lossy Lines

TDT and Lossy Line Modeling Is For:

Long lossy transmission lines in backplanes and motherboards

Long lossy cables


TDT and IConnect Lossy LinesLoss Example: Time and Frequency Domain



Skin Effect vs. Dielectric Loss

Typical FR-4 50 Ohm Trace



Different Loss Modeling Approaches

Lumped (behavioral)– Defined for all frequencies– Slow for long lines

Distributed– Based on parameters (Rskin, Gdielectric)

Defined for all frequencies Not as general

– Based on RLGC data General for quasi-TEM Not defined for all frequencies



Causality in TEM Models

From basic physics, the real and imaginary parts of the dielectric constant are tightly related to ensure causality.

The same is true of the permeability constant, In TEM modeling, this means that R and L are related,

and G and C are related

Models based on RLGC data (or S-parameters) should

address this issue !!!



Our Model Extraction Approach

Assume standard simulator equations:

Two extraction methods:– Open circuit reflection (TDR, one port)– Matched circuit transmission (TDR, TDT, two-port)

Extract loss parameters: Rdc, Rac, Gdc, Gac, L, C Write resulting model in various formats

– Lumped– Distributed with parameters– Distributed with RLGC data

CjfGGY

LjfRRZ

acdc

acdc


TDT and IConnect Lossy LinesExample: Extraction Results (Transmission)

Extracted skin effect and dielectric loss parameters

Simulated and measured transmission



Symmetrical Lossy Coupled Line Model

Assumptions:– The lines are symmetrical– TDR steps are symmetrical– TDR steps arrive at the lines at the same time at the beginning

of both lines

B oard lines

TDR source 1

TDR source 2


IConnect Differential TDR Techniques

Even/Odd vs. Common/Differential

mtot

mselfodd CC

LLZ

mtotmselfodd CCLLlt

mtot

mselfeven CC

LLZ

mtotmselfeven CCLLlt

oddaldifferenti ZZ 2

oddaldifferenti tt

2even

commonZZ

evencommon tt



Even and Odd Impedance Profile Example

Note: - Odd mode = differential measurement (two TDR sources of opposite polarity) - Even mode = common mode measurement (two TDR sources of the same polarity)

Zeven>Zself>Zodd

teven>tself>todd


TDT and IConnect Lossy LinesExample: Extraction Results (Reflection, Coupled)

Both self and mutual parameters are extracted


Outline



Impedance Profile (Z-line) Transmission Line ModelingApp Note: “PCB Interconnect Characterization from TDR Measurements” App Note: “Characterization of Differential Interconnect from TDR Measurements”

L and C JEDEC computation– Examples:

Power Plane Analysis Backplanes and cable assemblies


IConnect Single-ended TDR Techniques

Single Transmission Line Modeling Is For:

Short (lossless) transmission lines

Electrically long packages (longer than Trise)

Electrically long connectors (longer than Trise)



Transmission Line Z and td

Directly available from impedance profile

Eliminate confusion about:– Exact impedance value– Exact electrical length of the lines

Z01

Z02

td



Via L and C

2

12

1t

t

dttZL )( 2

1

1

2

1t

t

dttZ

C)(

t2

t1

t2

t1



IConnect® Modeling Process

Measure and acquire

Process data

Extract model

Simulate, compare and verify



Modeling in IConnect Software

* Name: Automatically Generated

.subckt Single port1 port2 gnd_

****** Partition #1

c1 port1 gnd_ 456f

l1 port1 1 1.05n

****** Partition #2

t1 1 gnd_ 2 gnd_ Z0=50.8 TD=125p

…………..

****** Partition #4

t3 3 gnd_ port2 gnd_ Z0=48.2 TD=190p

.ends



Prepare to Simulate and Validate



Simulation and Validation Results


IConnect Single-ended TDR TechniquesUsing Rise Time Filtering to Achieve Simple Models



Coupled Transmission Line Modeling Is For:

Differential transmission lines

Differential connectors and packages that are electrically long (longer than Trise)

Crosstalk prediction (differential and single ended, forward, backward)

Crosstalk induced jitter prediction



Differential Line Modeling

Short interconnect– Use lumped-coupled model

Long interconnect– Split lines in multiple segments

Longer yet interconnect– Symmetric distributed coupled line model– For longer lines, use lossy approach instead

-Z odd/2, todd

Z ev en/2, tev en

Z odd, todd

Z odd, todd



IConnect Differential Line Modeling



Composite Model Generation

* Name: Automatically Generated.subckt Symmetric 1 2 3 4 5****** Partition #1 t1 1 5 6 5 Z0=49.7 TD=92.3p t2 3 5 7 5 Z0=49.7 TD=92.3p****** Partition #2 l1 6 8 19n c1 8 5 6.44p l2 7 9 19n c2 9 5 6.44p c3 8 9 716f k1 l1 l2 207m .ends



Model Validation in IConnect



Coupled LC Computation in IConnect


Outline



L and C JEDEC computationApp Note: “TDR Techniques for Characterization and Modeling of Electronic Packaging”



IConnect Short Interconnect Modeling

When is Interconnect Lumped?

Practical rule of “short” or “lumped” (RLC) interconnect

trise

tprop delay

trise > tprop delay• (2 or 3)



Short Interconnect Modeling is Used For:

IC packages

Connectors

Sockets

Vias on the board

Use only when short compared to Trise !!!



Single Parasitic Inductance

dtVVV

ZdttZL

t

shortrefTDR

t

t

1

2

1

0

2

1)(


TD

R O

scill

osc

op

e F

ron

t P

an

el V inc ident

V re flectedV

L

V T D R

V ref s hor tL


IConnect Short Interconnect ModelingSingle-Ended TDR: Package Lead Inductance L Measurements

TDR waveform:– TDR into package lead.

Short all the leads to ground on the inside of the package.

Short the leads that are not being measured to ground on the outside of the package.

Short waveform:– TDR into the “short”; connect the

probe signal contact to ground on a conductive (metal) pad

Induced waveform: Measure near end crosstalk with far

end of the victim shorted

Background waveform: Corrects for the noise and scope DC

offset

V background noise

V induced

Lm utual

P ackageunder testTD R in to the

package lead

M easure re flection

M easure near-endcrossta lk in ad jacent

lead

Packa

ge le

ads

S hort leadends toground

0

0

2dtWW

V

ZL shortTDRself )(

0

0

2dtWW

V

ZL backgroundinducedmutual )(

W TDR

W shortL


dtVVVZ

dttZ

Ct

TDRopenref

t

t

1

2

1 0

11

2

1

)(


TD

R O

scill

osc

op

e F

ron

t P

an

el V inc ident

V re flectedV C

Open

V T D R

V ref open

C


Single Parasitic Capacitance


IConnect Short Interconnect ModelingSingle-Ended TDR: Package Lead Capacitance C Measurements

TDR waveform:– TDR into package lead

Short the leads that are not being measured to ground on the outside of the package

Open waveform:– TDR into the “open”;disconnect the

probe from the DUT or remove the DUT from the fixture

Induced waveform:– Measure near end crosstalk with far

end of the victim open-ended

Background waveform:– Corrects for the noise and scope DC

offset

W TDR

W open

C

002

1dtWW

VZC TDRopenself )(

V background noise

V induced

Cm utual

002

1dtWW

VZC backgroundinducedmutual )(

P ackageunder testTD R in to the

package lead

M easure re flection

M easure near-endcrossta lk in ad jacent

lead

Packa

ge le

ads

K eep leadends open



Input Die Capacitance Measurement



Even-Odd Mode L and C Measurements

Compute C and L in even and odd mode

2

oddevenmutual

evenself

CCC

CC

2

2

oddevenmutual

oddevenself

LLL

LLL

TD R in to the two ad jacentsocket lead w ith d iffe rentia l and

com m on m ode stim ulus

M easure odd m ode TD R w ithd iffe rentia l stim ulus, and

even m ode TD R w ith com m onm ode stim ulus

P ackageunder test

Packa

ge le

ads



Even-Odd Mode Impedance Profile

Compute C and L from even and odd Z-line

TD R in to the two ad jacentsocket lead w ith d iffe rentia l and

com m on m ode stim ulus

M easure odd m ode TD R w ithd iffe rentia l stim ulus, and

even m ode TD R w ith com m onm ode stim ulus

P ackageunder test

Packa

ge le

ads

oddoddevenevenself tZtZL 2

1

oddoddevenevenm tZtZL 2

1

even

even

odd

oddtot Z

t

Z

tC

2

1

even

even

odd

oddm Z

t

Z

tC

2

1

Ctotal = Cself + Cm


Outline


Interconnect SPICE / IBIS Modeling and Model Validation Examples:

Power Plane Analysis Backplanes and cable assemblies


Power Plane AnalysisPower Distribution Network (PDN) Test Vehicle

3"

1 3

/8" (3

5m

m)

Top plane

Via connection to bottom plane

P robe p lacem ent a t po in to f power app lica tion

P oin t o f power de livery

Pad connection to top plane

R eference short connection forinductance m easurem ent


Power Plane Analysis

PDN Equivalent Models

R C

R C LR C 1 L

R

C

L

C 2



PDN Capacitance Measurements



PDN Impedance



PDN Resonance: Analysis for Bypass Caps



PDN Model Validation



PDN Model Accuracy


Power Plane Via

Power Via Inductance

22oddeven

mutualoddeven

self

LLL

LLL

oddoddevenevenmutualoddoddevenevenself tZtZLtZtZL 2

1

2

1


Power Plane Via

Example: Via Modeling

***** Partition #1 l1 port1 1 1.9n l2 port3 2 1.9n k1 l1 l2 200m

Correlation between simulation and measurement


Outline


Interconnect SPICE / IBIS Modeling and Model Validation Examples:

Backplanes and cable assemblies


Putting It All TogetherComplete Topological Modeling Methodology

Connectors, packages:– Short structures => use lumped elements (LC) or lossless T-

lines – Use the true impedance profile approach

Cables – lossy transmission line

Backplane traces – lossy transmission line

Combine the model and verify the accuracy with simulations

Note that MeasureXtractor™ can do any of that! (behaviorally)


Single-ended Example

Example: IConnect-Extracted Model

LCL=700pHC=280fF

T-lineZ=53 OhmTd=520ps(short => lossless)

CLCL=6nHC=1.5pF

W-lineL=198nH, C=69.7pFRo=0.18 OhmRs=0.2uOhmGd=6.7nS (nMho)(long => lossy)


Single-ended Example

Simulation Results


Differential Example

Backplane Example

Courtesy FCI Electronics



Backplane Example: PCI-X Eye Diagram



Backplane Example

Differential measurement, full mode analysis

Daughter Card Backplane Daughter Card

Connector Connector



Daughter Card and Backplane Models

Daughter Card Model (odd mode)

Backplane Model (odd mode)



Full Daughter Card Modeling



Full Backplane Modeling



Simulation Results



Jitter De-Embedding: Daughter Card Only



Jitter De-Embedding: Backplane Only


Outline

Interconnect Measurement Accuracy Issues– Impedance, S-parameters and eye diagram measurements

Interconnect SPICE / IBIS Modeling and Model Validation– Z-line, lossy line, and automatic behavioral modeling


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